Patents Issued in January 29, 2008
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Patent number: 7323739Abstract: A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.Type: GrantFiled: January 13, 2006Date of Patent: January 29, 2008Assignee: Micron Technology, Inc.Inventors: Trung Tri Doan, Tyler A. Lowrey
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Patent number: 7323740Abstract: A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells.Type: GrantFiled: June 18, 2004Date of Patent: January 29, 2008Assignee: Samsung Electronics Co., LtdInventors: Weon-Ho Park, Sang-Soo Kim, Hyun-Khe Yoo, Sung-Chul Park, Byoung-Ho Kim, Ju-Ri Kim, Seung-Beom Yoon, Jeong-Uk Han
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Patent number: 7323741Abstract: A low cost semiconductor nonvolatile memory device capable of high speed programming, using an inversion layer as the wiring, and a manufacturing method for that device. The semiconductor memory device includes an auxiliary electrode at a position between and in parallel with the source and drain regions and with no position overlap versus the source region and the drain region formed mutually in parallel; wherein the auxiliary electrode for hot electron source injection is utilized as the auxiliary electrode for programming (writing); and an inversion layer formed below the auxiliary electrode is utilized as the source region or as the drain region during the read operation.Type: GrantFiled: November 30, 2004Date of Patent: January 29, 2008Assignee: Renesas Technology Corp.Inventors: Kazuo Otsuga, Hideaki Kurata, Yoshitaka Sasago
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Patent number: 7323742Abstract: A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant region lines, with one line of the pair forming the source region and one line of the pair forming the drain region of each memory cell of the column. Each memory cell has a floating polysilicon storage gate. One of plural wordlines overlies each row of the memory cells. The portion of the wordline overlying each memory cells forms the control gate of the memory cell. Programming and erase operations occur by Fowler-Nordheim tunneling of electrons through a tunnel oxide layer between the floating gate and the source of the cell.Type: GrantFiled: October 27, 2005Date of Patent: January 29, 2008Assignee: Catalyst Semiconductor, Inc.Inventor: Sorin S. Georgescu
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Patent number: 7323743Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.Type: GrantFiled: November 22, 2006Date of Patent: January 29, 2008Assignee: Nanya Technology CorporationInventors: Ying-Cheng Chuang, Chung-Lin Huang, Chi-Hui Lin
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Patent number: 7323744Abstract: A semiconductor device includes an ONO film (17) formed on a semiconductor substrate (15), a first gate (14), the first gate (14) formed on the ONO film (17), a source (10) and a drain (12) provided at both sides of the first gate (14) to face each other, and a second gate (16), the second gate (16) being a side gate provided at a side of the first gate (14) other than the side where the source (10) and the drain (12) are provided. This makes it possible to provide the semiconductor device in which a desired circuit characteristic is obtainable in a non-destructive manner and in a non-volatile fashion while reducing the trial production times thereof for IC development.Type: GrantFiled: February 24, 2006Date of Patent: January 29, 2008Assignee: Spansion LLCInventor: Yukio Hayakawa
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Patent number: 7323745Abstract: A power MOSFET is disclosed in which the source and drain regions are reversed from their usual positions and the drain is on the top of the chip (the surface containing the junction pattern diffusions) and the source is on the bottom of the chip. A plurality of spaced trenches are formed in the top surface. One group of trenches contain gate polysilicon and a gate oxide to control an invertible channel region along the trench. A second group of the trenches have a buried source contact at their bottoms which are connected between the N source material to the P channel region to short out a parasitic bipolar transistor.Type: GrantFiled: January 25, 2005Date of Patent: January 29, 2008Assignee: International Rectifier CorporationInventor: Daniel M. Kinzer
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Patent number: 7323746Abstract: A recess gate-type semiconductor device includes a gate electrode having a recessed portion at least partially covering a recess trench in an active region, and source/drain regions disposed in the active region that are separated by the gate electrode. The recess trench is separated from sidewalls of a device isolation region in a first direction and contacts sidewalls of the device isolation region in a second direction. The width of the recess trench of the active region in the second direction may be greater than the width of the source/drain regions in the second direction, and the recessed portion of the gate electrode may have tabs protruding in the first direction at its corners. Therefore, the semiconductor device has excellent junction leakage current and excellent refresh characteristics.Type: GrantFiled: September 14, 2005Date of Patent: January 29, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Mo Park, Jae-Choel Paik, Du-Heon Song, Dong-Hyun Kim, Chang-Sub Lee
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Patent number: 7323747Abstract: In a high voltage P-channel MOS transistor formed on a silicon-on-insulator (SOI) substrate, a P+-type source region (8), an N-type body region (4) and an N+-body contact diffusion region (10) are surrounded by a P+-type drain region (9) and a P-type drift region (5). A gate electrode (7) is formed to overlap the end portion of the N-type body region (4). The end portion of the N-type body region (4) has a portion in which the gate electrode (7) and the P+-type source region (8) are not adjacent to each other.Type: GrantFiled: July 18, 2006Date of Patent: January 29, 2008Assignee: Matsushita Electric Industrial, Co., Ltd.Inventors: Teruhisa Ikuta, Hiroyoshi Ogura, Yoshinobu Sato, Toru Terashita
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Patent number: 7323748Abstract: A semiconductor device includes a substrate having first and second regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, and a first semiconductor layer formed on the first insulating film with a space provided with respect to the first epitaxial layer, having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer and having a tapered surface faced to a side surface of the first epitaxial layer.Type: GrantFiled: June 20, 2006Date of Patent: January 29, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yamada, Hajime Nagano, Takeshi Hamamoto
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Patent number: 7323749Abstract: A semiconductor device with a plurality of passive components (7,7a,8,8a) comprising a bottom substrate (1), a buried oxide layer (2) on a portion of the top surface of the bottom substrate (1), an dielectric intermediate insulating layer (3) on a portion of the buried oxide layer (2), a dielectric top insulating layer (4), and at least one implanted passive component (7a,8a) of a semiconductor material implanted under the buried oxide layer (2) within the top surface portion of the bottom substrate (1), the implanted semiconductor material having a material polarity being opposite to the bottom substrate polarity. When the implanted passive component (7a) is an AC decoupling capacitor (7a), the bottom and side portions of the implanted semiconductor material are surrounded by a depletion layer (7b) of a semiconductor material implanted between said bottom substrate (1) and said implanted semiconductor material.Type: GrantFiled: February 14, 2006Date of Patent: January 29, 2008Assignee: Seiko Epson CorporationInventor: Kazuaki Tanaka
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Patent number: 7323750Abstract: A bipolar transistor is provided, which is low in collector-to-emitter saturation voltage, small in size and to be manufactured by a reduced number of processes, and a semiconductor device formed with such a bipolar transistor and a MOS transistor on a same substrate. A high concentration region for reducing the collector-to-emitter saturation voltage VCE(sat) is formed in a manner surrounding a base region of an NPN transistor. This high concentration region is not necessarily formed in such a depth as reaching a buried layer, and can be reduced in the spread in a lateral direction. Because a high concentration region can be formed in a same process as upon forming source and drain regions for an NMOS transistor to be formed together with an NPN transistor on a same silicon substrate, it is possible to omit a diffusion process exclusive for forming a high concentration region and hence to manufacture a semiconductor device through a reduced number of processes.Type: GrantFiled: March 14, 2005Date of Patent: January 29, 2008Assignee: Rohm Co., Ltd.Inventor: Masahiro Sakuragi
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Patent number: 7323751Abstract: A thin film resistor and at least one metal interconnect are formed in an integrated circuit. A first dielectric layer is formed over a metal interconnect layer. A thin film resistor is formed on the first dielectric layer and a second dielectric layer formed over the thin film resistor. Thin film resistor vias and the at least one trench are formed concurrently in the second dielectric layer. A trench via is then formed in the at least one trench. The trench via, the at least one trench and the thin film resistor vias are filled with a contact material layer to form thin film resistor contacts and at least one conductive line coupled to the metal interconnect layer.Type: GrantFiled: June 3, 2003Date of Patent: January 29, 2008Assignee: Texas Instruments IncorporatedInventors: Eric Williams Beach, Rajneesh Jaiswal
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Patent number: 7323752Abstract: This invention discloses an electrostatic discharge (ESD) protection circuit that comprises a substrate of a predetermined type, at least one MOS transistor being coupled to a pad of an integrated circuit for dissipating an ESD current from the pad during an ESD event, a substrate contact region, and at least one floating diffusion region formed in a substrate area between the MOS transistor and the substrate contact region for reducing a trigger-on voltage of the MOS transistor during the ESD event.Type: GrantFiled: September 30, 2004Date of Patent: January 29, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hung Chu, Shao-Chang Huang, Ming-Hsiang Song
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Patent number: 7323753Abstract: To an output of an NMOS having one end connected to a power source, a capacitor and a PMOS are connected. A capacitor is connected to the output of the PMOS. The NMOS and the PMOS are turned on alternately. A pulse is applied to other end of the capacitor which is connected to the output of the NMOS, to shift the output of the NMOS for boosting. Then, a back gate of the NMOS is connected, via a PMOS in an on state, to the power source. With this structure, the PMOS provides a resistor component when the output terminal short-circuits.Type: GrantFiled: August 24, 2004Date of Patent: January 29, 2008Assignee: Sanyo Electric Co. Ltd.Inventors: Kazuo Henmi, Nobuyuki Otaka
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Patent number: 7323754Abstract: Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the first well and having a gate insulating film of a first thickness, and a second transistor formed in the second well and having a gate insulating film of a second thickness less than the first thickness. The first well has a first impurity concentration distribution having an extremum maximum value only at the depth equal to or greater than the first depth. The second well has a second impurity concentration distribution which is superposition of the first impurity concentration distribution, and another impurity concentration distribution which shows an extremum maximum value at a second depth less than the first depth, the superposition shows also an extremum maximum value at the second depth.Type: GrantFiled: June 29, 2005Date of Patent: January 29, 2008Assignee: Fujitsu LimitedInventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki
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Patent number: 7323755Abstract: Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing silicon onto an oxide substrate as a thin layer, and then thermally annealing the silicon layer in a nitrogen-containing species or exposing the silicon to a plasma source of nitrogen to nitridize the silicon layer.Type: GrantFiled: August 31, 2006Date of Patent: January 29, 2008Assignee: Micron Technology, Inc.Inventor: Ronald A Weimer
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Patent number: 7323756Abstract: Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing silicon onto an oxide substrate as a thin layer, and then thermally annealing the silicon layer in a nitrogen-containing species or exposing the silicon to a plasma source of nitrogen to nitridize the silicon layer.Type: GrantFiled: August 31, 2006Date of Patent: January 29, 2008Assignee: Micron Technology, Inc.Inventor: Ronald A Weimer
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Patent number: 7323757Abstract: A wafer having heterostructure therein is formed using a substrate with recesses formed within a dielectric layer. A magnetized magnetic layer or a polarized electret material is formed at the bottom of each recess. The magnetized magnetic layer or a polarized electret material provides a predetermined magnetic or electrical field pattern. A plurality of heterostructures is formed from on an epitaxial wafer wherein each heterostructure has formed thereon a non-magnetized magnetic layer that is attracted to the magnetized magnetic layer formed at the bottom of each recess or dielectric layer that is attracted to the polarized electret material formed at the bottom of each recess. The plurality of heterostructures is etched from the epitaxial wafer to form a plurality of heterostructure pills.Type: GrantFiled: January 24, 2003Date of Patent: January 29, 2008Assignee: Massachusetts Institute of TechnologyInventors: Clifton G. Fonstad, Jr., Markus Zahn
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Patent number: 7323758Abstract: On a light shielding film 7, an anti-oxidation layer 9 covering at least the light shielding film 7 is formed. The anti-oxidation layer 9 is formed under a condition which does not oxidize a surface of the light shielding film 7. The anti-oxidation layer 9 is formed of a high melting point metal compound film having a light shielding property or an insulating film having a light transmissive property. Thus, the scattering ratio of the incident light at the surface of the light shielding film 7 can be uniform among all the pixels, and as a result, a solid state imaging device having suppressed sensitivity non-uniformity can be realized. Since the surface of the light shielding film 7 is not oxidized, the thickness of the light shielding film 7 can be reduced. Thus, the present invention can comply with the demand for size reduction of the pixels.Type: GrantFiled: March 16, 2005Date of Patent: January 29, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Naoto Niisoe, Hiroe Ogata, Rieko Nishio, Toshihiko Yano, Hitoshi Doi
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Patent number: 7323759Abstract: A photosensor for a transmitted-light method for detecting the intensity profile of an optical standing wave, with a transparent substrate, with a semiconductor component, and with at least three contacts, is characterized by the fact that two semiconductor components are connected with each other, such that the first semiconductor component and the second semiconductor component each have a photoelectrically active first semiconductor layer, and such that the two photoelectrically active semiconductor layers have a fixed phase relation to each other, which is adjusted by at least one photoelectrically inactive layer.Type: GrantFiled: June 12, 2002Date of Patent: January 29, 2008Assignee: Forschungszentrum Jülich GmbHInventors: Dietmar Knipp, Helmut Stiebig, Hans-Joachim Büchner, Gerd Jäger
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Patent number: 7323760Abstract: When the film thickness of an insulating film on a fuse connected to a circuit is not uniform within a wafer surface, there was a problem that disconnection of the fuse might become insufficient due to the insufficient intensity of a laser or disconnection of even an adjacent fuse due to excessive laser irradiation might occur. Further, a problem also occurred that after disconnection of the fuse, moisture entered from exterior through the region in which the fuse has been disconnected, so that the quality of a film underlying the fuse was adversely affected. After a SiON film, a SiN film, and a SiO2 film have been formed to cover the fuse in this stated order, etching is performed to the SiN film, which is an etching stopper film. The SiON film having a uniform and desired film thickness is thereby formed on the fuse.Type: GrantFiled: January 19, 2005Date of Patent: January 29, 2008Assignee: NEC Electronics CorporationInventor: Takashi Sakoh
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Patent number: 7323761Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.Type: GrantFiled: November 12, 2004Date of Patent: January 29, 2008Assignee: International Business Machines CorporationInventors: Byeongju Park, Subramanian S. Iyer, Chandrasekheran Kothandaraman
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Patent number: 7323762Abstract: A semiconductor package substrate with embedded resistors and a method for fabricating the same are proposed. Firstly, an inner circuit board having a first circuit layer thereon is provided, and a plurality of resistor electrodes are formed in the fist circuit layer. Then, a patterned resistive material is formed on the inner circuit board and electrically connected to the resistor electrodes to accurately define a resistance value of resistors. Subsequently, at least one insulating layer is coated on a surface of the circuit board having the patterned resistive material. At least one patterned second circuit layer is formed on the insulating layer and electrically connected to the resistor electrodes by a plurality of conductive vias formed in the insulating layer or plated through holes formed through the circuit board.Type: GrantFiled: November 1, 2004Date of Patent: January 29, 2008Assignee: Phoenix Precision Technology CorporationInventors: Zao-Kuo Lai, Lin-Yin Wong
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Patent number: 7323763Abstract: A semiconductor device having an improved voltage control oscillator circuit is provided. The voltage control oscillator circuit includes, in combination, a variable-capacitance element and at least one bipolar transistor on a single semiconductor substrate. The variable-capacitance element includes reversely serially connected PN junctions, and junctions are formed by a single common collector layer and separated base layers on the common collector layer. The capacitance of the variable-capacitance element is generated between respective base layers of the PN junctions with the common collector layer, and varies in correspondence with the voltage applied to the common collector layer.Type: GrantFiled: July 7, 2005Date of Patent: January 29, 2008Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Satoshi Suzuki, Takayuki Matsuzuka, Kenichiro Chomei
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Patent number: 7323764Abstract: A buffer structure comprising a compositionally graded layer of a nitride alloy comprising two or more Group IIIB elements, for example La, Y, Sc or Ac, is used to modify a silicon substrate to produce a universal substrate on which a range of target materials, for example GaN, may be deposited to produce semiconductor devices for electronic and optical applications. The resulting lattice parameter L varies with thickness T through the structure.Type: GrantFiled: February 16, 2004Date of Patent: January 29, 2008Assignee: QinetiQ LimitedInventor: David J Wallis
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Patent number: 7323765Abstract: An electrical package for an integrated circuit die which comprises a die-attach paddle for mounting the integrated circuit die. The die-attach paddle has at least one down-set area located on a periphery of the die-attach paddle. The down-set area has an upper surface and a lower surface, with the upper surface configured to electrically couple a first end of a first electrically conductive lead wire. A second end of the first electrically conductive lead wire is bonded to the integrated circuit die. The upper surface is further configured to electrically couple a first end of a second electrically conductive lead wire and a second end of the second electrically conductive lead wire is bonded to a lead finger of the electrical package.Type: GrantFiled: October 13, 2004Date of Patent: January 29, 2008Assignee: Atmel CorporationInventor: Ken M. Lam
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Patent number: 7323766Abstract: A sensor module, in particular for measuring an acceleration or rotational speed, having a housing base body made of a plastic material, a lead frame extending through the housing base body and having leads which have connector pins for attachment to a circuit board, a sensor system having at least one sensor chip, the sensor system being in contact with the lead frame via conductor bonds, a cover, which is connected to the base body and at least one connector pin and is made of a conductive material. A simple construction having a high shielding effect is achieved due to the fact that the conductive cover is connected to the connector pin. The cover, a lid, for example, may be contacted directly via the connector pin together with the other connector pins when the components are mounted on the circuit board. The sensor module may be molded or may have a premolded housing. The edge or a contact of the cover may be welded, soldered, glued, or pressed to a ground lead of the lead frame.Type: GrantFiled: November 4, 2004Date of Patent: January 29, 2008Assignee: Robert Bosch GmbHInventors: Kurt Weiblen, Franz Schmich, Harald Emmerich, Klaus Offterdinger, Hansjoerg Beutel, Johann Wehrmann, Florian Grabmaier
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Patent number: 7323767Abstract: A semiconductor device, semiconductor die package, mold tooling, and methods of fabricating the device and packages are provided. In one embodiment, the semiconductor device comprises a pair of semiconductor dies mounted on opposing sides of a flexible tape substrate, the outer surfaces of the dies having one or more standoffs disposed thereon. The standoffs can be brought into contact with an inner surface of the mold plates of a mold tooling when the device is positioned between the mold plates to maintain the flexible tape substrate in a centralized position within a mold chamber and inhibit the tape from bending as a molding compound flows into the chamber during encapsulation.Type: GrantFiled: April 25, 2002Date of Patent: January 29, 2008Assignee: Micron Technology, Inc.Inventors: Stephen L. James, Vernon M. Williams
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Patent number: 7323768Abstract: A semiconductor chip is provided which includes active and inactive IP cores. The spaces on the metal layer associated with the inactive IP cores includes voltage contrast inspection structures. The voltage contrast inspection structures serve to provide improved planarization of the metal layer and provided improved inspection capabilities.Type: GrantFiled: May 18, 2005Date of Patent: January 29, 2008Assignee: LSI Logic CorporationInventor: Bruce Whitefield
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Patent number: 7323769Abstract: An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip.Type: GrantFiled: May 8, 2006Date of Patent: January 29, 2008Assignee: United Test and Assembly Center Ltd.Inventors: Hien Boon Tan, Anthony Yi Sheng Sun, Francis Koon Seong Poh
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Patent number: 7323770Abstract: A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include a plurality of electrode terminals which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.Type: GrantFiled: December 14, 2005Date of Patent: January 29, 2008Assignee: Renesas Technology Corp.Inventors: Shinji Moriyama, Tomio Yamada
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Patent number: 7323771Abstract: An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated.Type: GrantFiled: June 28, 2006Date of Patent: January 29, 2008Assignee: Renesas Technology CorporationInventors: Ryo Fujita, Osamu Kubo, Kouki Noguchi, Masaharu Kubo, Michihiro Mishima, Yasuhiko Takahashi
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Patent number: 7323772Abstract: Semiconductor device packages formed in accordance with methods of packaging semiconductor dice in grid array-type semiconductor device packages using conventional lead frame or lead lock tape assembly equipment are disclosed. Circuitry-bearing segments having an electrically insulating layer that carries redistribution circuitry and redistributed bond pads and which is supported from beneath by a support layer are secured to the active surface of a semiconductor die. The support layer may comprise an electrically conductive material, which may act as a heat sink or as a ground plane for the packaged semiconductor device. The methods provide increased accuracy with which segments are placed on a semiconductor die relative to the placement accuracies provided when pick-and-place equipment is used to position conventional grid array substrates relative to semiconductor dice.Type: GrantFiled: August 28, 2002Date of Patent: January 29, 2008Assignee: Micron Technology, Inc.Inventor: Michael W. Morrison
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Patent number: 7323773Abstract: There is disclosed a semiconductor device having first and second semiconductor chips. The first semiconductor chip has a memory circuit. The second semiconductor chip has a circuit controlling the memory circuit. The contour size of the semiconductor device is reduced down to a smaller size required by a client without impairing the testability of the first semiconductor chip having the memory circuit. The circuit controlling the memory circuit consists of an MPU. The memory circuit consists of an SDRAM. The two semiconductor chips are stacked on top of each other over the top surface of an interconnect substrate. The chips are sealed in a molding resin, thus forming an SiP (System-in-Package). First terminals electrically connected with the second chip are arranged as external terminals of the SiP on the outer periphery of the bottom surface of the interconnect substrate.Type: GrantFiled: September 9, 2005Date of Patent: January 29, 2008Assignee: Renesas Technology Corp.Inventors: Yoshinari Hayashi, Toshikazu Ishikawa, Takayuki Hoshino
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Patent number: 7323774Abstract: An integrated circuit package system includes providing a substrate having a bond finger thereon and forming a pedestal on a portion of the bond finger. A first die is mounted on the substrate and adjacent to the bond finger. A portion of the first die, a portion of the bond finger, and a portion of the pedestal are embedded in an resin layer with an exposed portion of the pedestal protruding from the resin layer. A second die is mounted on the first die and electrically coupled to the exposed portion of the pedestal.Type: GrantFiled: January 11, 2006Date of Patent: January 29, 2008Assignee: Stats Chippac Ltd.Inventor: Rajendra D. Pendse
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Patent number: 7323775Abstract: A memory module comprises a base plate and one or more IC embedding seats formed thereon to provide IC memory chip being installed in detachable manner taking the advantage of easy installation, convenient maintenance or replacement of IC memory chip, particularly no longer using SMT, soldering paste, or flux for IC maintenance and replacement; the IC embedding seat comprises a mainbody and a sliding cover formed a cover to the mainbody with sliding movement to open or close the mainbody, and the mainbody has one or more IC mounting compartments has a plurality of conducting pin units arrayed in matrix arrangement to form electric connection with the base plate; during IC maintenance and replacement, the defective IC memory chip shall be freely removed from the memory module without de-soldering to prevent other good IC memory chip from damage due to high temperature.Type: GrantFiled: November 22, 2005Date of Patent: January 29, 2008Assignee: Lih Duo International Co., Ltd.Inventor: Sung-Lai Wang
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Patent number: 7323776Abstract: The elevated heat dissipating device of the present invention comprises a thermal substrate connecting onto a heat source and at least one heat conductive pipe connecting to the thermal substrate. The heat conductive pipe further comprises a connecting part connected to a top portion of the thermal substrate, and a bending part which is bended and extended upward away from the thermal substrate. A plurality of sets of heat fins connecting to end portions of the bending part of the heat conductive pipe are supported and elevated by the heat conductive pipe so that an air space is formed between the thermal substrate and the sets of heat fins. A fan locating on a top part of the heat fins, wherein a plurality of air passages are formed in between those heat fins so that cool air ventilates from the fan through the air passages of the heat fins to the thermal substrate.Type: GrantFiled: December 2, 2005Date of Patent: January 29, 2008Assignee: Thermaltake Technology Co., Ltd.Inventor: Pei-His Lin
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Patent number: 7323777Abstract: A semiconductor substrate has an integrated circuit, an interconnect electrically connected to the inside of the semiconductor substrate, and an electrode formed on the interconnect. A plurality of resin layers are separately formed on the semiconductor substrate so that part of the semiconductor substrate is exposed. A redistribution interconnect is electrically connected to the electrode. An external terminal is formed on the redistribution interconnect and supported by the resin layers.Type: GrantFiled: April 26, 2005Date of Patent: January 29, 2008Assignee: Seiko Epson CorporationInventor: Koji Yamaguchi
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Patent number: 7323778Abstract: A semiconductor device comprises: a semiconductor chip; an extension portion formed in contact with the side surfaces so as to surround the semiconductor chip; an insulating film formed on a surface of the extension portion and the semiconductor chip; each of a plurality of wiring patterns electrically connected to each electrode pad, respectively and extended from the electrode pads to the surface of the extension portion; a sealing portion formed such that a part of each of the wiring patterns is exposed; and a plurality of external terminals provided over the wiring patterns in a region including the upper side of the extension portion.Type: GrantFiled: October 31, 2003Date of Patent: January 29, 2008Assignee: Oki Electric Industry Co., Ltd.Inventor: Yoshinori Shizuno
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Patent number: 7323779Abstract: A semiconductor device includes a semiconductor chip. A stepped member having stepped regions is provided on the semiconductor chip. The stepped member, together with a redistribution layer, is encapsulated by an encapsulating resin layer. The stepped member is exemplified by functional bumps and dummy bumps having stepped regions. The dummy bumps are electrically unconnected to the exterior, but are electrically connected to the redistribution layer.Type: GrantFiled: March 16, 2005Date of Patent: January 29, 2008Assignee: Oki Electric Industry Co., Ltd.Inventor: Soichiro Ibaraki
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Patent number: 7323780Abstract: An electrical interconnection structure and method for forming. The electrical structure comprises a substrate comprising electrically conductive pads and a first dielectric layer over the substrate and the electrically conductive pads. The first dielectric layer comprises vias. A metallic layer is formed over the first dielectric layer and within the vias. A second dielectric layer is formed over the metallic layer. A ball limiting metallization layer is formed within the vias. A photoresist layer is formed over a surface of the ball limiting metallization layer. A first solder ball is formed within a first opening in the photoresist layer and a second solder ball is formed within a second opening in the photoresist layer.Type: GrantFiled: November 10, 2005Date of Patent: January 29, 2008Assignee: International Business Machines CorporationInventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter
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Patent number: 7323781Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.Type: GrantFiled: March 24, 2004Date of Patent: January 29, 2008Assignee: Renesas Technology Corp.Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwaskai, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
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Patent number: 7323783Abstract: There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101, characterized in that the first metal film 102 is formed of Al, and the second metal film 103 is formed of at least one metal selected from the group consisting of Nb, W, Fe, Hf, Re, Ta and Zr.Type: GrantFiled: December 6, 2004Date of Patent: January 29, 2008Assignee: NEC CorporationInventors: Tatsuo Nakayama, Hironobu Miyamoto, Yuji Ando, Takashi Inoue, Yasuhiro Okamoto, Masaaki Kuzuhara
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Patent number: 7323784Abstract: Top via pattern for a bond pad structure has at least one first via group and at least one second via group adjacent to each other. The first via group has at least two line vias extending in a first direction. The second via group has at least two line vias extending in a second direction different from said first direction. The line via of the first via group does not cross the line via of the second via group.Type: GrantFiled: March 17, 2005Date of Patent: January 29, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ho-Yin Yiu, Fu-Jier Fan, Yu-Jui Wu, Aaron Wang, Hsiang-Wei Wang, Huang-Sheng Lin, Ming-Hsien Chen, Ruey-Yun Shiue
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Patent number: 7323785Abstract: A through-electrode that penetrates a semiconductor substrate and that is insulatively separated from the semiconductor substrate includes an inner through-electrode, a quadrangular ring-shaped semiconductor, and an outer peripheral through-electrode. The quadrangular ring-shaped semiconductor is formed around the inner through-electrode, and the outer peripheral through-electrode is formed around the quadrangular ring-shaped semiconductor.Type: GrantFiled: March 17, 2006Date of Patent: January 29, 2008Assignee: Elpida Memory, Inc.Inventor: Shiro Uchiyama
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Patent number: 7323786Abstract: A semiconductor device package includes a plurality of stacked semiconductor chips and a spacer interposed therebetween. The spacer includes a first spacer and a second spacer stacked on one another. The first and the second spacers have different principal surfaces. If the second spacer has a larger principal surface than the first spacer, flexure of the upper semiconductor chip can be avoided.Type: GrantFiled: February 24, 2005Date of Patent: January 29, 2008Assignee: NEC Electronics CorporationInventor: Kou Sasaki
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Patent number: 7323787Abstract: A multilayered printed wiring board having a ball grid array (BGA) land pattern in which each land in the pattern is connected to a respective via by a link connector, a method of adapting spacing between selected adjacent via and respective link pairs to receive decoupling capacitor pads, comprising rotating, elongating and/or truncating the selected adjacent pairs and rotating their respective corresponding via pairs to adapt the spacing between the selected adjacent via pairs in the BGA land pattern and applying the capacitor pads to the selected via pairs. The selected adjacent via pairs and their respective link connectors are rotated, elongated and/or truncated in mutually opposite directions.Type: GrantFiled: January 25, 2005Date of Patent: January 29, 2008Assignee: AlcatelInventor: Alex L. Chan
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Patent number: 7323788Abstract: A semiconductor device which can meet the requirement for a further increase in pins, which multi-functionalization and faster operation would entail is to be provided. Bonding pads and bonding pads are arranged in a zigzag pattern in a direction along an outer circumference of a main surface of a chip. To focus on power supply-line bonding pads among all the bonding pads, an odd number of bonding pads are to be arranged in a direction of the outer circumference of the main surface between adjoining bonding pads. A greater width is secured for the power supply-line bonding pads than for other bonding pads, and a diameter of wires to be connected to the power supply-line bonding pads is set greater than that of other wires.Type: GrantFiled: March 29, 2007Date of Patent: January 29, 2008Assignee: Renesas Technology Corp.Inventors: Yoshinori Miyaki, Kazunari Suzuki, Hirohito Ohashi
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Patent number: 7323789Abstract: A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on a memory chip at portion near the side and the other side respectively. The clock receiving pad is electrically connected to the clock output pad and the return clock receiving pad. A plurality of clock signals are supplied from the logic chip to the memory chip, and a plurality of return clock signals are returned from the memory chip to the logic chip.Type: GrantFiled: January 28, 2005Date of Patent: January 29, 2008Assignee: Fujitsu LimitedInventors: Fusao Seki, Tatsushi Otsuka, Masanori Kurita, Shinnosuke Kamata, Toshiya Uchida, Hiroyoshi Tomita, Hiroyuki Kobayashi