Abstract: A heatsink attachment assembly includes a first anchor, a second anchor and a heatsink clip. The first anchor is configured to insert into a first hole in a circuit board in an upward direction from an underside of the circuit board toward a topside of the circuit board. Similarly, the second anchor is configured to insert into a second hole in the circuit board in the upward direction. The heatsink clip has (i) a first end configured to fasten to the first anchor when the first anchor is inserted into the first hole in the circuit board, (ii) a second end configured to fasten to the second anchor when the second anchor is inserted into the second hole in the circuit board, and (iii) a middle section configured to provide force on a heatsink in a downward direction which is substantially opposite the upward direction.

Abstract: An electronic device with a heat-dissipation structure is disclosed. The electronic device comprises a housing, a printed circuit board assembly, and a heat sink. The printed circuit board assembly is disposed in an interior of the housing, and the printed circuit board assembly forms a high-temperatured heat flow area and a low-temperatured heat flow area in the electronic device. The heat sink is disposed between the printed circuit board assembly and the housing and in the low-temperatured heat flow area for balancing heat flow and homogenizing temperature of the electronic device to enhance heat-dissipation efficiency.

Abstract: A plug-in module adds functionality to a portable electronic device. The module includes a housing that is accepted by a housing port of the portable electronic device. The module includes at least one latch to secure the module to the electronic device. Each latch includes a first member, a second member, and a third member. The housing includes at least one receptacle corresponding to each latch. The receptacles are sized and positioned to accept a member of the latch and direct the latch to a groove located on the portable electronic device. Optionally, the latch includes a slip-resistant surface sized to accept a human finger or thumb. The module also preferably includes a hardware interface connector sized and positioned within the housing to engage a 120-pin hardware interface port on the portable electronic device when the module housing is positioned on the housing port of the portable electronic device.

Abstract: A memory card includes: a main body of the memory card in which a notched section is formed; a semiconductor memory; and a write/nonwrite setting element for setting the write/nonwrite state of data in the semiconductor memory, the write/nonwrite setting element being slidably fitted in the notched section, wherein the main body of the memory card includes an upper main body and a lower main body; at least one of the upper main body and the lower main body has an elastic guide formed within the notched section; the write/nonwrite setting element slides along the elastic guide so as to set the write/nonwrite state of the data in the semiconductor memory; and the elastic guide has an engagement portion for engagedly stopping the write/nonwrite setting element so as to select the position of the write/nonwrite setting element with respect to the elastic guide.

Abstract: A chassis and associated telecommunication circuit card are disclosed. The chassis has heat dissipation and flame containment features while accommodating a high density of the circuitry cards. Embodiments include an inner housing with a double-layer middle floor dividing the chassis into top and bottom chambers. Each layer has partially aligned slots, and an air gap is provided between the two layers. Embodiments also include a double-layer mesh cover with an air gap existing between the two mesh layers. Projections and grooves are provided on the inner surfaces of the inner housing to receive circuit cards having a guide on one edge and a fin on another. The circuit card includes conductor structures such as multiple board layers with paired and segregated conductors. The circuit card also includes some components positioned to cooperate with the ventilation features of the chassis and includes some components chosen for low-power consumption or reduced flammability.

Abstract: A modular component coupling apparatus includes a chassis and a plurality of guide members mounted in the chassis which define a component channel, the plurality of guide members each including a first end and a second end, the second end including a component securing member adjacent the component channel. A modular component may be coupled to the chassis by engaging the component rear securing member such that vibrations in the modular component are reduced relative to a conventional coupling apparatus.

Abstract: An apparatus and method to provide a micro-electromechanical systems (MEMS) radio frequency (RF) switch module with a vertical via. The MEMS RF switch module includes a MEMS die coupled to a cap section. The vertical via passes through the cap section to electrically couple an RF switch array of the MEMS die to a printed circuit board (PCB). In one embodiment, the MEMS die includes a trace ring surrounding at least a portion of the RF switch array so that a signal may enter or exit the MEMS RF switch module using the vertical via without crossing the trace ring.

Abstract: Provided is a wiring board including an insulating substrate with a first region and a second region adjacent to each other on a major surface, signal line groups arrayed on the first region, and connection portions arranged on the second region in correspondence with the signal line groups, wherein each connection portion includes first to third terminal groups, a first wiring line group connecting the first terminal group to the corresponding signal line group, a second wiring line group connected to the second terminal group, and a third wiring group connected to the third terminal group, wherein the second and third wiring line groups are connected to each other between each adjacent connection portions, and all of the connection portions are the same in shapes of the first to third terminal groups and the first to third wiring line groups.

Abstract: Multiple DIMM circuits or instantiations are presented in a single module. In some embodiments, memory integrated circuits (preferably CSPs) and accompanying AMBs, or accompanying memory registers, are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile.

Abstract: A shield casing of an image display apparatus including a casing which covers other than a front surface of an image display device having an electromagnetic wave emitter and shielding the electromagnetic waves, a protection panel on which a conductive film is laminated, and a mounting device which is in contact with the conductive film and attaches the protection panel to the casing, wherein the mounting device has an arm stretching toward a front side of the protection panel, a tip portion of the arm curves toward the protection panel and has a contact surface with the protection panel on an outer side surface of the tip portion, and the mounting device mounts the protection panel to the casing with the force more than supporting the protection panel.

Abstract: A wide range power supply capable of delivering 20V to 5000V is provided. The power supply of the present invention uses switch mode technology to achieve high overall operating efficiency and is capable of operating from no load to full load without loss of regulation. The power supply in accordance with the embodiments of the present invention operates directly from the utility supply (e.g., 110V/220V and 50 Hz/60 Hz). In one embodiment, the power supply's power conversion stage includes the following stages: an input rectifier; a buck converter; a quasi-resonant inverter; and a voltage multiplier. The above indicated stages are connected in series to achieve the large output voltage range. High precision is obtained from a use of a digital feedback loop, possibly in connection with an analog feedback loop.

Abstract: A DC-DC converter is provided which includes a switching element, a choke coil, a flywheel diode, an output capacitor, a diode, and an auxiliary transformer having primary and secondary windings. The primary winding and the switching element constitute a first series circuit such that one terminal of the primary winding is connected to the drain terminal of the switching element, and the secondary winding and the diode constitute a second series circuit such that one terminal of the secondary winding is connected to the cathode terminal of the diode, where the other terminal of the second winding is connected to the positive terminal of a DC power source, and the anode terminal of the diode is connected to the negative terminal of the DC power source.

Abstract: A mechanism for reducing common-mode current in a system including a first subsystem and an isolated subsystem. The isolated subsystem may receive the common-mode current from the first subsystem via an isolation mechanism. The isolation mechanism (e.g., a transformer) may isolate the isolated subsystem from the first subsystem by blocking DC signals. The first subsystem may include a pulse generation unit and compensation circuitry. The pulse generation unit may provide a first pulse and a second pulse to the compensation circuitry. The phase and duty cycle of the pulses may be varied based on measured characteristics of the isolation mechanism. The compensation circuitry may generate a cancellation signal based on the first and second pulses. Furthermore, the compensation circuitry may provide the cancellation signal to a ground plane of the isolated subsystem to reduce the common-mode current received at the isolation subsystem.

Abstract: A power supply apparatus for electric operation is provided for an electric operation apparatus, and includes an instructing signal input portion which generates a DC output voltage to a high-frequency generating circuit that generates a high frequency and which receives an instructing signal for controlling the output voltage. The instructing signal input portion includes at least a noise reducing circuit which reduces a normal-mode noise.

Abstract: In a power supply apparatus including a charge-pump type step-up circuit adapted to carry out a stand-by operation to charge a step-up capacitor by a power supply voltage, and carry out a step-up operation to step up a charged voltage of the step-up capacitor and discharge a stepped-up charged voltage of the step-up capacitor to a smoothing capacitor, the step-up operation is controlled by a clock signal and an AND logic signal between the clock signal and a negative feedback control signal of an output voltage of the charge-pump type step-up circuit. The negative feedback control signal is a pulse width modulation signal so that a frequency of the AND logic signal is always the same as that of the clock signal.

Abstract: A converter circuit for a wind power system for supplying a high-voltage direct voltage connection. The system includes a transformer with one primary winding per phase and a plurality of secondary windings per phase. Three of these secondary windings of different phase are connected to each rectifier cell. These rectifier cells are connected to one another by their inputs and outputs. The rectifier cells themselves each include one input rectifier and two series-connected upward converters, and the center tap of the secondary winding of the transformer is connected to the center points of the series circuit of the upward converters.

Abstract: Methods and apparatus for converting power from a power source are described. In one example embodiment, the method includes controlling multiple transformer and switchgear units coupled to a power source, and controlling multiple converter units connected in parallel. Each converter unit is coupled to a respective one of the transformer and switchgear units to form an individual thread. The transformer and switchgear unit and power converters are controlled so that the carrier waveforms for each individual thread are interleaved between each other over a carrier cycle.

Abstract: An inverter for use in connecting a DC power source to the utility grid includes a single DC-AC conversion stage, maximum (source) power tracking, and current control based on feed-forward compensation as a function of input power voltage error, rectified utility line voltage, and a scaled inverse of RMS utility line voltage. Various topologies of the inverter power stage are developed for bi-directional power-flow operation after those developed for unidirectional power-flow operation. Various embodiments also include over-voltage protection, over-current protection, under-voltage protection, over-temperature protection, and stand-by battery with battery management control, while still others are adapted for a multiple-channel front-end distributed power system with distributed maximum power tracking for serving as a single DC power source input to the inverter system downstream with controllers, emergency or auxiliary loads, and alternative current feedback control systems.

Abstract: A CAM cell (200) can include a compare section (206) and a configuration section (208). In a binary mode of operation, two compare data values can be driven on value lines VL1 to VL4 (216-0 to 216-3) for comparison against two stored data values. In a ternary mode of operation, one compare data value can driven on two of the value lines, while the other two value lines can be forced to a potential unrelated to a compare data value allowing for dynamic configuration between binary and ternary modes of operation.

Abstract: A memory array can be optimized for SPICE simulation by modeling the memory array as a collection of boundary elements that track the cell states of memory cells connected to a particular array terminal. By maintaining a cell state distribution for each boundary element, the simulation behavior at the array terminal associated with that boundary element can be accurately determined by modeling each unique cell state, multiplying the results by the corresponding quantities from the cell state distribution, and then adding the results to obtain final values for the array terminal. This allows accurate simulation results to be achieved without needing to simulate each cell independently. Furthermore, by removing any references to unoccupied cell states (e.g., by removing such states from the cell state distribution and/or eliminating model equations for such states), the memory and cpu usage requirements during the simulation can be minimized.

Abstract: An integrated circuit includes memory circuitry with a number of bit line structures, each including at least three bit lines; a number of word lines that intersect with the bit line structures at a number of sites; and a number of switching devices located at the sites. A number of VSS planes are interconnected with the switching devices. The switching devices and the VSS planes are formed at a first level. The VSS planes can be formed as substantially complementary interlocking regions that also form functional portions of the switching devices. The switching devices can be connected between an adjacent one of the word lines and a selected one of the bit lines of an adjacent one of the bit line structures for selective electrical conduction therebetween upon activation by the adjacent one of the word lines.

Abstract: A memory includes transistors in rows and columns providing an array, conductive lines in columns across the array, and phase change elements contacting the conductive lines and self-aligned to the conductive lines. The memory includes bottom electrodes contacting the phase change elements, each bottom electrode self-aligned to a conductive line and coupled to one side of a source-drain path of a transistor.

Abstract: A nonvolatile memory array includes a plurality of word lines, a plurality of bit lines, a plurality of source lines, and a plurality of nonvolatile memory cells. Each of at least a subset of the plurality of memory cells has a first terminal connected to one of the plurality of word lines, a second terminal connected to one of the plurality of bit lines, and a third terminal connected to one of the plurality of source lines. At least one of the memory cells includes a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element connecting to one of a corresponding first one of the bit lines and a corresponding first one of the source lines, and a metal-oxide-semiconductor device including first and second source/drains and a gate.

Abstract: A semiconductor memory cell structure having 4 F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a capacitor is formed on the semiconductor post. A vertical access transistor having a gate structure formed on the semiconductor post is configured to electrically couple the respective memory cell capacitor to the active region when accessed.

Abstract: An integrated circuit memory includes memory cells 2 is connected to a power supply Vdd via a power supply control circuit 4. The power supply control circuit includes a first gate 26 and a second gate 28. The first gate 26 is switched by a write assist circuit so as to be non-conductive when writing to the memory cell 2. The second gate 28 is conductive both when writing to the memory cell 2 and when not writing to the memory cell 2. Accordingly, when a write operation is made a relatively high resistance path is formed through the power supply control circuit 4 compared to when writing is not being performed. This increase in the resistance through the power supply control circuit 4 during write operations induces a dip in the virtual supply voltage provided at the supply output of the power supply control circuit 4 in a manner which assist writes to be made.

Abstract: An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and a smart power integrated circuit architecture formed on the same substrate using the same fabrication process technology. The fabrication process technology is a modular process having a front end process and a back end process. In the example embodiment, the smart power architecture includes a power circuit component, a digital logic component, and an analog control component formed by the front end process, and a sensor architecture formed by the back end process. The MRAM architecture includes an MRAM circuit component formed by the front end process and an MRAM cell array formed by the back end process. In one practical embodiment, the sensor architecture includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array.

Abstract: A method for determining memory element values may include: selecting a column of interest containing a desired memory element, disabling the desired memory element, measuring a first current provided to the column of interest, adjusting measurement circuitry to compensate for skew introduced by undesired memory elements, enabling the desired memory element, and measuring a second current provided to the column of interest.

Abstract: A phase change memory has an array formed by a plurality of cells, each including a memory element of calcogenic material and a selection element connected in series to the memory element; a plurality of address lines connected to the cells; a write stage and a reading stage connected to the array. The write stage is formed by current generators, which supply preset currents to the selected cells so as to modify the resistance of the memory element. Reading takes place in voltage, by appropriately biasing the selected cell and comparing the current flowing therein with a reference value.

Abstract: The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.

Abstract: A short circuit detection region includes an insulating film, plural first conductor traces and plural second conductor traces which are embedded in the insulating film with only their surfaces being exposed, and the first conductor trace is constructed by integrally forming a band-shaped portion and plural via portions which are electrically connected to a silicon semiconductor substrate.

Abstract: A core-based multi-bit memory (400) having a dual-bit dynamic referencing architecture (408, 410) fabricated on the memory core (401). A first reference array (408) and a second reference array (410) are fabricated on the memory core (401) such that a reference cell pair (185) comprising one cell (182) of the first reference array (408) and a corresponding cell (184) of the second reference array (410) are read and averaged to provide a reference voltage for reading a data array(s).

Abstract: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.

Abstract: A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of the charge storage structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. Example arrangements are a series of memory cells, and an array of series of memory cells.

Abstract: A method is described for erasing a selected data region in an NROM cell that is a member of a virtual ground NROM EEPROM array. The method provides that erasing the selected data region does not disturb the program state of unselected data regions.

Abstract: In an embodiment, a method of driving a program operation in a nonvolatile semiconductor memory device is operable without discharging a bitline connected to a memory cell to be programmed between a program period and a verifying period. This remarkably improves programming speed and reduces current consumption.

Abstract: A memory device has an array of memory cells. A column decoder is configured to address the memory cells. A charge-pump supply circuit generates a boosted supply voltage for the column decoder. A connecting stage is arranged between the supply circuit and the column decoder. The connecting stage switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device, in particular during a reading step.

Abstract: A voltage reference circuit provides a reference voltage that can be precisely programmed. The threshold voltage of a first non-volatile memory (NVM) transistor is programmed while coupled in parallel with a second NVM transistor. During programming, one or more capacitors are connected between the floating gate of the first NVM transistor and ground, and one or more capacitors are connected between the floating gate of the second NVM transistor and ground. The first and second NVM transistors are then coupled to a differential amplifier, which is used to generate a single-ended reference voltage in response to the programmed threshold voltage of the first NVM transistor. Bipolar transistors are selectively switched between the various capacitors and ground, thereby providing precise adjustment of the temperature coefficient of the voltage reference circuit.

Abstract: A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data.

Abstract: A current-mode sensing structure used in a high-density multiple-port register in logic processing and a method for the same are proposed. First, a reference current is defined by a dummy word line of a dummy cell and output. A multiple-port register file cell is then used to send out a select signal of “0” or “1” and output a cell current according to the select signal and the reference current. Finally, the cell current and the reference current are sent to a current comparator amplifier, which senses and outputs a difference value between the cell current and the reference current to perform session at once (SAO) recording. Because the difference value has only two possibilities: the reference current or its negative, the sensing time of the current comparator amplifier can be shortened.

Abstract: A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation determines the threshold voltage for each cell. When the threshold voltage reaches a pre-verify threshold, only the bit line connected to that particular cell is biased with an intermediate voltage that slows down the change in the Vt of the cell. The other cells continue to be programmed at their normal pace. As the Vt for each cell reaches the pre-verify level, it is biased with the intermediate voltage. All of the bit lines are biased with an inhibit voltage as their threshold voltages reach the verify voltage threshold.

Abstract: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

Abstract: Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufacturing molecular memories. Methods of manufacturing molecular memories that enable semiconductor devices and interconnections to be manufactured monolithically with molecular memory are also disclosed.

Abstract: A method for erasing a flash memory group is provided, which comprises the following steps. (a) Apply a erase (ERS) pulse to a first subset of the group. (b) Perform one of a soft program verification (SPGMV) and a tight soft program verification (TSPGMV) on the first subset of the group. (c) Repeat steps (a) and (b) until a first predetermined condition is true. (d) Perform an erase verification (ERSV) on a second subset of the group. (e) Repeat steps (a) to (d) until a second predetermined condition is true. And (f) fix bit line leakage in a third subset of the group with a slow program (SLPGM) and apply an ERS pulse to the third subset.

Abstract: Low power high density random access memory flash cells and arrays using Fowler Nordheim (FN) tunneling for both programming and erasing. The memory array is divided into sectors, each sector comprising a predetermined number of rows. The bit lines are similarly segmented, each global bit line being selectively connectable to a local bit line for each sector, each local bit line being connected to the drains of all floating gate cells in a respective column of each sector. The sources of all floating gate cells in a respective column of each sector are connected to a local source line for that sector, the local source lines for each sector being controllably connectable to respective global source lines. Consequently all floating gate cells within a column of a sector are connected in parallel, source to source and drain to drain. Representative programming and erase voltages not disturbing other cells are disclosed.

Abstract: A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory transistor.

Abstract: A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in column circuits of user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A remote redundancy scheme has the redundant data available from a central buffer accessible by any number of column circuits. Redundant data buffer circuits enable bus exchange with data from the user data latches except for defective locations when data are taken from the central buffer. In this way only addressing for the user portion is used for bus exchange. Also, accessibility to the redundant data will not be restricted by the locations of the column circuits relative to the redundant data latches and the buffered redundant data can be accessed at a finer granularity than that imposed by the column circuits.

Abstract: Circuits and methods are described for reducing leakage current and speeding access within dynamic random access memory circuit devices. A number of beneficial aspects are described. A circuit is described for an enhanced sense amplifier utilizing complementary drain transistors coupled to the sense or restore signals and driven by gate voltages which extend outside of the voltage range between VSS and VDD. The drain transistors are self reverse-biased in a standby mode. A method is also described for reducing leaking in non-complementary sense amplifiers by modifying the sense and restore gate voltages. Another aspect is a new negative word line method utilizing stacked pull-down transistors and a multi-step control circuit. In addition a level shifter scheme is described for preventing unwanted current flow between voltage sources while discharging control signal PX.

Abstract: A method (200) for determining various bit failure modes in a static random access memory device. A hard/soft bit failure test sequence is performed on each cell of the memory device to determine whether the cell exhibits a hard bit failure or a soft bit failure, then a data retention test is performed on the cell having soft bit failure to determine whether the cell exhibits a data retention failure. A write or disturb test sequence is then performed on the cell not having data retention failure, and a read or disturb test sequence is performed on the cell having write or disturb failure. Finally, a disturb test sequence is performed on the cell having read or disturb failure, and then an analysis is performed on the data from the tests to determine whether the cell exhibits one of a write, read, or disturb failure.

Abstract: This invention uniquely partitions the pBIST ROM for storing program and data information. The pBIST unit selectively loads both the algorithm and data, the algorithm only or the data only for each test set stored in the pBIST ROM into read/write registers. These registers are memory mapped readable/writable. A configuration register has an algorithm bit and a data bit which determines whether the corresponding algorithm or data is loaded from the pBIST ROM. The pBIST unit includes another configuration register having one bit corresponding to each possible test set stored in the pBIST ROM. The pBIST unit runs a test set if the corresponding bit in the configuration register has a first digital state.

Abstract: One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.