Abstract: A method and apparatus for managing power in a server system having clustered server modules. A remote power-on signal delivered to a particular server module is routed to a baseboard management controller (BMC) of the server module. The BMC communicates with a central power management controller (MC) of the server system to ensure that the system currently has sufficient power to power-on the server module.

Abstract: A system for generating, delivering and distributing electrical power to network elements over a data communication network infrastructure within a building, campus or enterprise. Consolidating power distribution and data communications over a single network simplifies and reduces the cost of network element installation and provides a means of supplying uninterrupted or backup power to critical network devices in the event of a power failure. The invention includes power/data combiners that combine a data communication signal with a low frequency power signal. The combined signal is transported over the LAN infrastructure where a power/data splitter extracts the data signal and the power signal and generates two separate outputs. The power over LAN system of the present invention operates with high bandwidth data communication networks, i.e., 10 Mbps, 100 Mbps, 1000 Mbps.

Abstract: Disclosed is a program product for directing the information processing apparatus to control an execution mode of a central processing unit(CPU) provided, the CPU having a plurality of execution modes, whose types and power consumptions of executable processing are different from one another, the program product comprising: an apparatus readable medium; recovery time acquisition means for acquiring a recovery time which is a time required for the CPU to recover from a low power mode to a high power mode of which power consumption is higher than that of the low power mode; allowed time acquisition means for acquiring the longest allowed time from a request for processing unprocessable in the low power mode and processable in the high power mode to a start of the processing after the CPU recovers to the high power mode, the request being made by an input/output device; and execution mode setting means for settingthe CPU in a state of being shiftable to the low power mode if it is determined that the CPU is able

Abstract: A synchronous signal generator is provided that contains a first and second counting and delay circuit, which both are in a subhierarchical position with respect to a reset signal synchronization/delay circuit. The reset signal synchronization/delay circuit and the first and second counting and delay circuit are triggered by a basic clock signal or a first clock signal derived therefrom to be identical in frequency and phase, and contain counting means whose initial and final counting state are adjustable in order to set, in a clocked fashion, the temporal positions of a first and second load signal that are output by the first counting and delay circuit as well as of a FIFO read clock signal that is output by the second counting and delay circuit and thus adapt them to the temporal requirements of a semiconductor memory system containing the synchronous signal generator.

Abstract: A method to obtain configuration data for a data processing apparatus by calculating (110) a time interval between the commencement of a mode (104) and a subsequent event (108). The calculated time interval is then compared (112) with one or more reference values (114). The result of the comparison is used to derive configuration data (116). The method may be further refined by including a calibration stage to reduce the error in the calculated time interval, thereby allowing comparison with a larger set of reference values (114), which in turn permits more configuration data to be derived from the calculated time interval.

Abstract: An information processing system is provided. The information processing system comprises: an information processing subsystem including a processor and a processor support chip in data communication therewith. The processor support chip is operable to provide processor support functions for the processor, and comprises a local management entity. The system further comprises a remote management entity connected to communicate with a remote management network. The local management entity is connected to communicate with the remote management entity via a first management communication channel; and the local management entity is operable to monitor the remote management entity and, in response to detection of an error status of the remote management entity, to divert management communications to a second management communications channel bypassing the remote management entity to maintain communications with the remote management network.

Abstract: An embedded system with reduced susceptibility to single event upset effects. The system includes an instruction memory that can store at least one instruction set. The instruction memory utilizes a parity checking error-detection scheme. The system also includes a non-volatile memory that can store a copy of the at least one instruction set, and a data memory that can store at least one data sequence. The data memory utilizes an error correction coding (ECC) scheme. A controller, which is responsive to the instruction memory, the non-volatile memory, and the data memory, replaces the at least one instruction set in the instruction memory with the copy of the at least one instruction set from the non-volatile memory, if a parity error is detected in connection with the at least one instruction set in the instruction memory. The controller also operates in conjunction with the data memory to implement the ECC scheme.

Abstract: In one embodiment, and under control of resources belonging to a controller domain of a data center, a farm server for which a backup operation is to be performed is identified. Interfaces of backup services belonging to the controller domain are then virtually associated with the first farm network. Thereafter, the farm server and backup services are registered in a backup domain of the data center, the backup domain being associated with backup storage. Via the backup services that have been associated with the first farm network, and during execution of the backup operation by the farm server, movement of backup data from the first farm network to the backup storage is facilitated by the method. After completing the backup operation, the farm server and backup services are un-registered from the backup domain, and the interfaces of the backup services are de-associated from the first farm network.

Abstract: Embodiments of the present invention provide a magnetic memory. In one embodiment, the magnetic memory comprises an array of memory cells and a control circuit. The control circuit is configured to receive data, sort the received data to obtain unchanged data and ECC encoded data, and store the unchanged data and the ECC encoded data in the array of memory cells.

Abstract: A method for operating a data processing system and a redundancy data processing unit for executing the method is disclosed. Two or more active data processing units are assigned to each redundancy data processing unit. The redundancy data processing unit stores a copy of the active data stock of each active data processing unit assigned to it. Each of the active data processing units periodically ascertains changes in its current active data relative to the copy of its active data stored in the redundancy data processing unit and transfers correction data describing any changes. By means of the transferred correction data, the redundancy data processing unit updates its stored copy of the active data and, in the event of the failure of an assigned active data processing unit, assumes the function of the failed data processing unit based upon its stored data copy from the failed data processing unit.

Abstract: In a continuous data protection system having a primary volume and a secondary volume, a method for data recovery begins by selecting a snapshot of the primary volume to be recovered and a location on which the snapshot is to be loaded. A point in time (PIT) map is created for the selected snapshot, and the selected snapshot is loaded at the selected location. A data block from the PIT map is resolved to determine which block on the secondary volume is presented as being part of the snapshot. The snapshot is accessed via a host computer as if the snapshot was the primary volume at an earlier point in time, corresponding to the time of the selected snapshot.

Abstract: An integrated multi-application data processing system for generating, storing, and retrieving data files, each data file having an array of data cells, which includes a program framework providing a common user interface for at least one application program for user interaction with one or more of the data files. Each of the data cells, which can contain a single data object that includes an object type code and object content, has a unique address with respect to all cells in data files generated by the system.

Abstract: In one embodiment, a recovery manager may define a plurality of recovery target sets. Each recovery target set comprises a recovery point target, a recovery time target, and at least one other property. The recovery manager also defines a plurality of recovery classes. Each recovery class comprises at least one recovery target set of the plurality of recovery target sets. Each recovery class describes recovery requirements over an asset state life cycle. The recovery manager applies a first recovery class of the plurality of recovery classes to a first asset dependent on an importance of the first asset to an owner of the first asset. In some cases, the first recovery class and/or other recovery classes of the plurality of recovery classes may each be applied to multiple assets. In another embodiment, a recovery manager defines one or more recovery target sets to be applied to one or more assets and saves the one or more recovery target sets. In some embodiments, recovery classes are also saved.

Abstract: Certain exemplary embodiments of the present invention provide a control system device, comprising a multiple channel discrete output module, said module storing a plurality of fail-state parameters, each fail-state parameter from the plurality of fail-state parameters corresponding to one channel of the multiple channels. Certain exemplary embodiments of the present invention provide a method for controlling the operation of each of a plurality of channels coupled to a discrete output module upon failure or shutdown of a control system coupled to the discrete output module, comprising, for each of the plurality of channels, storing a predetermined value for a fail-state parameter in a multi-channel discrete output module adapted to control the channel; and upon detecting a control system failure or shutdown, causing the channel to operate in a mode corresponding to the stored value for the channel's fail-state parameter.

Abstract: A method and computer program product for error monitoring partitions in a computer system. A global supervisor mapping (GSM) associates each supervised partition with a supervisor partition that monitors the supervised partition. A partition status buffer (PSB) denotes a status (GOOD, BAD, NOCARE) of the partition. The BAD status denotes that the partition has encountered at least one error that is currently unrepaired. The supervisor partition determines its supervised partition from the GSM and ascertains the status of its supervised partition from the PSB. If the status of the supervised partition is BAD then a recovery procedure is performed by the supervisor partition. The recovery procedure: obtains a grant of access to physical and logical resources of the supervised partition which contains error data of the supervised partition; gathers the error data; and sets the status of the supervised partition to the NOCARE status.

Abstract: Test circuitry is incorporated on a chip die together with a circuit to be tested, such as an ASIC or microprocessor, to provide external access to signals that are internal to an integrated circuit chip package. A controller provides the arm command and issues appropriate configuration controls to collect signal samples. In particular, a network responds to these commands from the controller to selectively provide signal samples from a device under test. A trigger event generator responds to logic or other characteristics of the signal samples to provide trigger events. These trigger events are counted by a trigger event counter in the armed state of the state machine to identify the final trigger event corresponding to an occurrence of a programmable number of the trigger events. A store event generator also responds to a programmed characteristic or combination(s) of the signal samples to provide a store event. Either or both of the event generators may use a mask to provide these events.

Abstract: Intended for an information security application, particularly in networked information systems, the present invention includes two methods and systems for verifying a current performance of a command by a controller. A first cyclic redundancy check (CRC) for the command is prestored in memory. A second CRC for the command is calculated after instructions of the command have been performed by the controller. The first CRC is compared with the second CRC. Preferably, the controller is reset if the first CRC does not match the second CRC. Also, an address of a first instruction of the command is compared with an address of a second instruction of the command to determine if there may be a discontinuity between the first and the second instructions. It is determined if the first instruction is a valid instruction from/to which an instruction sequence of the command can be redirected.

Abstract: A method, apparatus and article of manufacture for prioritizing customer error reports for a software application. A sub-bucketing algorithm is performed in a computer to sort stack traces associated with the customer error reports by a plurality of lines or entries in the stack traces, in order to create a hierarchy for categorization of the customer error reports.

Abstract: A method for providing an indication from a network interface controller to a microcontroller is disclosed wherein upon occurrence of a particular condition within the network interface controller, an indication is provided from a reset pin of the network interface controller to the microcontroller unit. Upon receipt of the indication by the microcontroller unit, communications between the network interface controller and the microcontroller unit are inhibited.

Abstract: A trace data formatter 30 assembles trace data frames 50. These trace data frames 50 include bytes which may either serve to carry a trace data source identifier ID or trace data. A system being traced has multiple trace data sources 12, 14, 16, 18 and when the trace data source which is generating the current trace data stream changes then a trace data source identifier ID is inserted within the trace data stream.

Abstract: When a plurality of simultaneous, preselected target processor events are detected, a multiple-event sync marker is generated that identifies the preselected events and relates the occurrence of these events to timing trace stream. The sync marker for the plurality of preselected events differs from a single event sync marker by including at least one additional packet. The additional packet includes logic signals stored at locations related to each identified event.

Abstract: A method and system gather information to facilitate the remote support of devices installed on a computer. For example, an exemplary method comprises first installing an information harvester and a formatter onto the computer. These are then used to identify and test the devices and to collect information about the devices and the testing. Then at least some of the collected information is formatted for display to the user and presentation to a support specialist. The formatted information is then displayed as part of a user display also having provision whereby a user may enter additional comments about device problems into the user display. If a user so chooses, the user comments may be collected, then the combined formatted collected information and the collected user comments are sent to a support specialist by means of a network transport mechanism such as e-mail, TCP, or the like.

Abstract: A measurement and data acquisition system including a real-time monitoring circuit for implementing control loop applications. The system control loop may include the real-time monitoring circuit, a data acquisition device, a processing unit, and a plurality of subsystems. The subsystems may be comprised in the data acquisition device or may be external to the data acquisition device. The real-time monitoring circuit may receive a plurality of timing signals from the plurality of subsystems and may select a control loop timing signal out of the plurality of timing signals. The real-time monitoring circuit may determine whether the operations of the control loop are performed within a particular period of time by monitoring the control loop timing signal and communicating with the processing unit. In response to an error notification, the processing unit may take appropriate action, such as shutting down the system and/or reporting an error or warning.

Abstract: Embodiments of the present invention relate to a method. The method includes synchronizing a first device and a second device. If the first device and the second device both initiate the synchronizing at substantially the same time, then the first device and/or the second device may compensate for synchronization errors. In other words, when two devices begin communication, one or both the devices may perform a procedure which causes the two devices to successfully synchronize. Accordingly, when the two devices are synchronized they will be able to communicate. However, if both devices initiate synchronization at substantially the same time, absent additional measures, the two devices may not be synchronized. Accordingly, in embodiments of the present invention, these synchronization errors are compensated for, if a first and second device both initiates a synchronization procedure at substantially the same time.

Abstract: During a first data compression test mode which disables an error correction function, first test data are written to a first regular memory block. Second test data are written to not only a second regular memory block, but a parity memory block. By changing the number of bits distributed to the first and second test data (compression rate of data), a data compression test for a parity memory block can be performed without need to increase the number of test terminals. As a result, the test time can be decreased and the test cost can be decreased.

Abstract: The present invention relates to a pre-processing apparatus using nonuniform quantization of a channel reliability value and a low density parity check (LDPC) decoding system. The pre-processing apparatus can present degradation in performance and be embodied simply by performing decoding pre-process by estimating a discrete channel reliability value (Lc*) through nonuniform quantization of a channel reliability value based on a relations between a bit error rate (BER) estimated through a simulation performed in advance and a standard deviation (?) of channel noise within a predetermined range of noise estimation error and p, and bit-shifting a receiving signal as much as a discrete channel reliability value. The pre-processing apparatus includes: a channel reliability measuring unit, a nonuniform quantizing unit, a sign bit adding unit, a bit shifting unit.

Abstract: A system may adjust the times at which data is sampled by separate sampling mechanisms. Here, it may be desirable to ensure that one sampler samples data at substantially the same time as the other sampler. For example, output data from a high speed sampler that samples received data may be compared with an output of an analog to digital converter that samples the received data at a lower data rate. This difference or relative error may be accumulated over a period of time for given values of delay applied to the clock for the analog to digital converter. In this way, a delay value that minimizes the relative error may be selected as a desired delay value.

Abstract: Memory testing at system startup, such as boot POST, of an information handling system is accelerated by adjusting memory testing routines to use instructions that take advantage of optimizations made to information handling system and CPU architectures. For instance, memory test iterations in one Mbyte portions using 128-bit SIMD registers, 64-bit MMX registers, ADD and SUB instructions, the MOVNTDQ instruction, and relying on an initial setting of the gate A20 and protected mode result in a substantially accelerated memory test.

Abstract: A test circuit is sued to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.

Abstract: The pBIST solution to memory testing is a balanced hardware-software oriented solution. pBIST hardware provides access to all memories and other such logic (e.g. register files) in pipelined logic allowing back-to-back accesses. The approach then gives the user access to this logic through CPU-like logic in which the programmer can code any algorithm to target any memory testing technique required. Because hardware inside the chip is used at-speed, the full device speed capabilities are available. CPU-like hardware can be programmed and algorithms can be developed and executed after tape-out and while testing on devices in chip form is in process.

Abstract: The storage system includes a PLD (Programmable Logic Device), which controls data transfer between another device and a media drive; and a processor. The PLD includes a memory for storing information input from an information source located externally to the PLD; a circuit element group including a plurality of circuit elements; and a logical circuit configured on the circuit element group in accordance with the information in the memory. The processor detects whether a soft error has occurred in the memory, detects whether or not an error has occurred in the logical circuit, and implements control in accordance with the results of the two detection operations.

Abstract: A system to test integrated circuits on a wafer may include a transceiver formed on the wafer. The system may also include an antenna system couplable to the transceiver. The transceiver may be formed in one of a scribe line on the wafer, a chip on the wafer or on an otherwise unusable portion of the wafer. The antenna system maybe formed in at least one of the same scribe line as the transceiver or in at least one other scribe line formed in the wafer. Alternatively, the antenna system may include an antenna external to the wafer.

Abstract: A device for selecting an operating mode of an integrated circuit, including a non-volatile memory programmable after manufacturing exhibiting prior to any programming an initial content, means for storing a first signature representative of the initial content of the memory, means for calculating a second signature representative of a current content of the memory, and means for evaluating a difference between the first and second signatures and for deactivating an operating mode selection signal when the difference is greater than a predetermined threshold.

Abstract: The invention relates to a method for testing electrical modules. A test pattern of input signals is applied to each module to be tested as test specimen, and the actual responses of the test specimen to the test pattern is compared with the desired responses. The comparison result is evaluated for the purpose of displaying test assessments. According to one embodiment of the invention, to supply the desired responses, a reference module produced with the same design and technology as the test specimen and tested as entirely satisfactory is utilized. The same test pattern as for the test specimen is applied to the reference module. The invention furthermore relates to circuit arrangements for carrying out this method, in particular for testing data memories.

Abstract: A method and apparatus for generating an error correction code used in communicating over a channel, includes generating a set of candidate circulant blocks corresponding to a parity check matrix and a Hamming code wherein the Hamming code is initially unable to detect a predetermined error pattern without ambiguity due to one or more redundancies and eliminating columns of the parity check matrix and related redundancies in the detection of a predetermined error pattern as used by the resulting Hamming code.

Abstract: A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2 n bits in length.

Abstract: Requests issuing on a host computer are intercepted and stalled prior to sending to target computer systems. The requests are analyzed to determine whether they are suspicious. Requests determined to be suspicious are added as request entries to a request database. Each time a request entry is added to the request database, a determination is made whether malicious code activity is detected on the host computer system. Upon a determination that malicious code activity is detected, a notification of the malicious code detection is generated and protective actions are implemented, such as terminating the request. Requests not determined to be suspicious or to indicate malicious code activity are released for sending to the target computer systems.

Abstract: Methods and systems provide a tree view showing unannotated text nodes in a corresponding data formatted document. When the user begins to annotate the document with a desired data format structure, such as a markup language like XML, a tree view pane is displayed to the user to provide the user with an outline of the data structure presently applied to the document or to provide the user with an outline of the data structure applied to the document as the user annotates the document with data structure. In the tree view, an indicator is displayed in the location of any unannotated text nodes relative to their sibling data elements. If the user focuses on a given unannotated text node indicator in the tree view, the corresponding text node in the corresponding document is highlighted to the user to show the user the location of the text node that has not been annotated with data structure.

Abstract: The structured document converting method converts a tagged structured document in which tags are hierarchically ordered, into a document of unrestricted order, in such a manner that the original structured document can be restored. When converting a tagged structured document in which tags are hierarchically ordered into a document of unrestricted order, positional information relating to the original structured document is appended as attribute information to each tag. Furthermore, an index and hierarchical layer depth are used as references in the positional information. Moreover, a namespace is assigned.

Abstract: Method and system for dynamically capturing elements from a target Web page and displaying the captured elements in another Web page. A user first opens a Web Capture Web Part dialog box in a browser application program. The user navigates to the target server hosting the target Web page and sends an HTTP request to the target server to retrieve the target Web page. The target server returns the target Web page in an HTML string, which it is displayed in the Web Part Web Capture dialog box. The user then selects the elements that he or she wants to capture. The captured elements are then displayed in a Web part on the user's Web page and the returned HTML string is stored in a cache memory. Each subsequent time the captured elements are displayed, the elements are automatically updated from the target Web page.

Abstract: Literal character strings and are described directly without using a JSP extension tag in a portion of source statements that displays a component displaying the content repeatedly on a web screen. A mechanism is prepared to construct a component tree containing components generated from the literal character strings through the execution of the source statements. HTML is outputted by execution of components of the component tree, and the content is displayed on the web screen of a browser repeatedly.

Abstract: The present invention is an interface system for interactively building rules and constraints. The interface system comprises of an output display configured to show a user a partial complete rule with a current rule fragment, such rule fragment comprising a blank space. The user can fill in the blank space by either choosing from a list or by typing in text in the blank space. After the blank space is filled, a completed rule is generated. The interface system then assigns this rule to one or more person in a resource scheduling system. The present invention can be used for agent scheduling in a call center environment.

Abstract: Documents before and after editing are compared. Changes are applied to the original document, thus preserving the existing formatting.

Abstract: An automated document delivery service acquires content from content providers publishing on different schedules and using different URLs to define the path to their web sites. A rule based process of URL generation enables the use of a limited number of resource locator templates and a table of rules to access the web sites and download content of a large number of content providers.

Abstract: An apparatus, program product, and method manage content from a content-controlled database (e.g., web pages or other files maintained in a web site) using a content management record linked to each content-controlled content item in the database. Each content management record is utilized in conjunction with a multi-stage content management process, where at least one stage is a review stage during which approval of an associated content item for a content management record is obtained. As a result of receiving appropriate approval, such an associated content item may be promoted and made available to users of the content-controlled database, with the content management record updated to reflect such a status of the associated content item. Content management information for a content item may be maintained in a content management record that is separate from the content item.

Abstract: Number conversion between different units of measurement in a document is enabled. A string of text entered into an application program is analyzed to determine whether it includes a number having an associated unit name. Found numbers with associated unit names are semantically labeled with schema information identifying the unit name as a source unit of measurement. When the number is selected or an indication received that the number is labeled with schema information, a list of actions may be provided identifying conversion options for the number. In response to selection of one of the conversion options, the selected number is converted to the destination unit of measure identified by the selected action. The converted number may then be inserted into the string of text to replace the selected number along with a unit name corresponding to the destination unit of measure.

Abstract: A method of composing information by electronically advancing a sequence of information elements at controlled speed in an even step-wise fashion into a fixed transfer location while visibly displaying each of them there during a dwell time to permit the operator to decide whether to select it for manually directed copying into an output sequence. The speed of advance of the sequence of information elements and hence the dwell time for display of each information element is manually adjusted from time to time.

Abstract: A page is generated in a computer-based format that includes zones in which controls are inserted. The controls can present information or data that the controls obtain from one or more sources. Features such as the location, quantity, and properties of the zones and the controls can be set as desired when creating the page. Furthermore, the page can be created using a graphical layout. The page can be accessed in a computer-based environment, and properties of the controls, such as the size, position, or classification of presented information, can be manipulated while the page is being accessed.

Abstract: A page is accessed in a computer-based environment. A user interface gallery that includes at least one computer-based module from a remote source is opened on or in the vicinity of the page. The computer-based module can be inserted on the page from the gallery. The gallery can be dynamically populated with one or more computer-based modules from various sources remote to the page. A pointer that represents a computer-based module can be populated to the gallery as an alternative. The computer-based module can then be inserted on the page from the remote source when the pointer is selected and placed on the page. The computer-based module can also be stored in a database for future use after it has been inserted on the page.

Abstract: Embodiments of the present invention provide the ability to navigate, view, and manipulate a collection of digital images utilizing a GUI that has the familiar context of a calendar. Graphical objects representative of digital images are displayed within a particular day displayed in a calendar-based GUI. A user may group digital images into groups, modify the date with which a digital image is associated and perform various other manipulations using embodiments of a calendar-based GUI.