Abstract: An object of the present invention is to provide a Group III nitride semiconductor light-emitting device with high emission efficiency.

Abstract: A method for controlling the color contrast of a multi-wavelength light-emitting diode (LED) made according to the present invention is disclosed. The present invention includes at least the step of increasing the junction temperature of a multi-quantum-well LED, such that holes are distributed in a deeper quantum-well layer of the LED to increase luminous intensity of the deeper quantum-well layer, thereby controlling the relative intensity ratios of the multiple wavelengths emitted by the LED. The step of increasing junction temperature of the multi-quantum-well LED is achieved either by controlling resistance through modulating thickness of a p-type electrode layer of the LED or by modifying the mesa area size to control its relative heat radiation surface area.

Abstract: In a nitride semiconductor light-emitting device (11), an emission region (17) has a quantum well structure (19), and lies between an n-type gallium nitride semiconductor region (13) and a p-type gallium nitride semiconductor region (15). The quantum well structure (19) includes a plurality of first well layers (21) composed of InxGa1-xN, one or a plurality of second well layers (23) composed of InyGa1-yN, and barrier layers (25). The first and second well layers (21) and (23) are arranged in alternation with the barrier layers (25). The second well layers (23) lie between the first well layers (21) and the p-type gallium nitride semiconductor region (15). The indium component y of the second well layers (23) is smaller than indium component x of the first well layers (21), and the thickness DW2 of the second well layers (23) is greater than the thickness DW1 of the first well layers (21).

Abstract: A method of creating two-dimensional quantum computational cluster states is demonstrated that is considerably more efficient than previously proposed approaches. The method uses local unitaries and type-I fusion operations. The increased efficiency of the method compared to previously proposed constructions is obtained by identifying and exploiting local equivalence properties inherent in cluster states.

Abstract: A field-effect transistor includes a semiconductor layer (14), a source electrode (15) and a drain electrode (16) electrically connected to the semiconductor layer (14), and a gate electrode (12) for applying an electric field to the semiconductor layer (14) between the source electrode (15) and the drain electrode (16). The semiconductor layer (14) contains an organic semiconductor material and a plurality of thin wires made of an inorganic semiconductor.

Abstract: Molecular resonant tunneling diode (RTD) devices that include a molecular linker or bridge between two carbon nanotube (CNT) leads. Such devices include organic material self-assembled between two leads to yield RTD device behavior without the use of metallization of the organic material. Such devices alleviate the aforementioned problems associated with similar devices. Semiconducting carbon nanotubes (CNTs) may be used, and electrical functionality of the device is provided, not by intrinsic bistable properties of the bridge molecule, but by the crossing of resonant levels with the band edges of the leads.

Abstract: The present invention relates to the use of perylene diimide derivatives as air-stable n-type organic semiconductors.

Abstract: According to a first aspect, the present invention provides a method for forming a semiconductor film comprising a first step of providing a solution comprising a first organic semiconductor and a second organic semiconductor on a surface of a substrate. The solution is then dried to form the semiconductor film so that it comprises discrete domains of the first organic semiconductor in a matrix of the second organic semiconductor which electrically connects adjacent domains of the first organic semiconductor. The first and second semiconductors are of the same conductivity type. The mobility of charge carriers in the domains of the first organic semiconductor is higher than the mobility of charge carriers in the matrix of the second organic semiconductor.

Abstract: An object of the present invention is to provide a material which does not substantially have a hole injection barrier from an electrode. A composite material containing an organic compound and an inorganic compound, in which measured current-voltage characteristics of a thin-film layer formed from the composite material which is sandwiched between a pair of electrodes each having a work function of 3.5 eV to 5.5 eV follow Formula (I) below, is manufactured.

Abstract: An array substrate for a liquid crystal display device includes: a data line on a substrate; a source electrode contacting the data line, a drain electrode spaced apart from the source electrode and a pixel electrode connected to the drain electrode, wherein the source electrode, the drain electrode and the pixel electrode each including a transparent conductive material; an organic semiconductor layer contacting the source and drain electrodes; a gate insulating layer on the organic semiconductor layer; a gate electrode on the gate insulating layer; a first passivation layer on the gate electrode, the first passivation layer having a gate contact hole exposing the gate electrode; and a gate line on the first passivation layer, the gate line connected to the gate electrode through the gate contact hole.

Abstract: An organic thin-film transistor and a method for manufacturing the same are described. The method forms a gate layer on a substrate, an insulator layer on the substrate, forming a semiconductor layer on the insulator layer, and a strip for defining a channel length on the semiconductor layer. An electrode layer is screen printed on the semiconductor layer, and a passivation layer is coated on the electrode layer. The organic thin-film transistor manufactured by the method of the invention has a substrate, a gate layer formed on the substrate, an insulator layer formed on the substrate, a semiconductor layer formed on the insulator layer, a strip for defining a channel length formed on the semiconductor layer, an electrode layer screen-printed on the semiconductor layer, and a passivation layer coated on the electrode layer. Thereby, an organic thin-film transistor with a top-contact/bottom-gate structure is obtained.

Abstract: Disclosed is a thin film transistor array panel including a substrate, a data line formed on the substrate, a gate line that intersects the data line and includes a gate electrode, a source electrode connected to the data line, and a drain electrode facing the source electrode. An organic semiconductor contacts the source electrode and the drain electrode via an insulating layer having an opening that defines the location of the organic semiconductor. The insulating layer includes an acrylic photosensitive resin having a fluorine-containing compound. A method of manufacturing the above-described thin film transistor array panel is disclosed.

Abstract: A thin-film transistor array includes an electrically insulating substrate, a plurality of thin-film transistors arranged in a matrix on the substrate, and each including a channel, a source, and a drain each comprised of an oxide-semiconductor film, a pixel electrode integrally formed with the drain, a source signal line through which a source signal is transmitted to a group of thin-film transistors, a gate signal line through which a gate signal is transmitted to a group of thin-film transistors, a source terminal formed at an end of the source signal line, and a gate terminal formed at an end of the gate signal line. The source terminal and the gate terminal are formed in the same layer as a layer in which the channel is formed. The source terminal and the gate terminal have the same electric conductivity as that of the pixel electrode.

Abstract: A degradation detection method and circuit system for responding to degradation. The circuit system is located within a semiconductor device and comprises a process sensitive circuit, a measurement circuit, and a calculation circuit. The method comprises subjecting the semiconductor device to a first operating condition. A first value at a first time for a parameter of the process sensitive circuit is measured by the measurement circuit. The semiconductor device is operated to perform an intended function. A second value at a second time for the parameter of the circuit is measured by the measurement circuit. The second time is different from the first time. A first differential value between the first value and the second value is determined by the calculation circuit.

Abstract: A display apparatus comprises a display array and an enable circuit. The enable circuit comprises a set of diodes and a set of transistors. The diode element comprises a first contact and a second contact. The set of transistors comprises a first contact, a second contact, and a third contact. The first contact of the set of transistors is connected to the display array. The second contact of the set of transistors receives a test signal to test the display array. The third contact of the set of transistors is connected to the first contact of the diode element. The second contact of the diode element receives an enable signal to activate the enable circuit.

Abstract: A semiconductor chip having a current source coupled between a first potential and an electrical node, a detection circuit having an input coupled to the electrical node, and a first active component coupled in series with the current source and further coupled between the electrical node and a second potential, wherein the first active component is coupled to the electrical node via a first conductive interconnect.

Abstract: An ESD protection structure includes a structure to be protected disposed in a semiconductor body. A region of a first conductivity type is disposed within the semiconductor body and a channel is disposed in the semiconductor body and extends through the region of the first conductivity type. A semiconductor of a second conductivity type is disposed within the channel adjacent the region of the first conductivity type such that the region of the first conductivity type and the semiconductor of the second conductivity type form a diode. At least one of the region of the first conductivity type and the semiconductor of the second conductivity type is electrically coupled to the structure to be protected.

Abstract: A lower substrate for a liquid crystal display device and the method of making the same are disclosed. The method includes steps of: (a) providing a substrate; (b) forming a patterned transparent layer having plural recess on the substrate; (c) forming a first barrier layer on the surface of the recess; (d) coating a first metal layer on the first barrier layer and making the surfaces of the first metal layer and the transparent layer in substantially the same plane; and (e) forming a first insulated layer and a semi-conductive layer in sequence. The method further can optionally comprise the steps of: (f) forming a patterned second metal layer, wherein part of the semi-conductive layer is exposed, thus forming the source electrode and the drain electrode; and (g) forming a transparent electrode layer on part of the transparent layer and part of the second metal layer.

Abstract: An active matrix type display device, wherein a pixel circuit is formed using a plurality of thin film transistors in which thin semiconductor films forming channel regions of the thin film transistors are made in different crystal states.

Abstract: In a CMOS circuit formed on a substrate 100, a subordinate gate wiring line (a first wiring line) 102a and main gate wiring line (a second wiring line) 113a are provided in an n-channel TFT. The LDD regions 107a and 107b overlap the first wiring line 102a and not overlap the second wiring line 113a. Thus, applying a gate voltage to the first wiring line forms the GOLD structure, while not applying forms the LLD structure. In this way, the GOLD structure and the LLD structure can be used appropriately in accordance with the respective specifications required for the circuits.

Abstract: In a memory device and a method of forming a memory device, the device comprises a substrate, a first electrode extending in a vertical direction relative to the substrate, and a second electrode extending in a vertical direction relative to the substrate, the second electrode being spaced apart from the first electrode by a vertical gap. A third electrode is provided that extends in a vertical direction in the electrode gap, the third electrode being spaced apart from the first electrode by a first gap and the third electrode being spaced apart from the second electrode by a second gap, the third electrode being elastically deformable such that the third electrode deflects to be electrically coupled with the first electrode through the first gap in a first bent position and to be electrically coupled with the second electrode through the second gap in a second bent position, and to be isolated from the first electrode and the second electrode in a rest position.

Abstract: Organic light emitting display (OLED) devices and methods for fabricating the same are disclosed. An exemplary OLED device comprises a substrate with a thin film transistor (TFT) formed over a first portion thereof. A color filter layer is formed over a second portion of the substrate. A planarization layer overlies the color filter layer and the TFT. A pair of openings is formed through the planarization layer and portions of the TFT, respectively exposing a source/drain region of the TFT. A pair of conductive layers conformably covers the openings and portions of the planarization layer adjacent thereto, electrically connecting one of the source/drain regions of the TFT, wherein one of the conductive layers extends toward the color filter layer and the conductive layers are electrically isolated from each other. An anode is formed over the planarization, partially covering the conductive extending toward the color filter layer.

Abstract: A thin film transistor substrate includes a first conductive layer formed on a substrate, an anti-diffusion layer deposited on the first conductive layer, a semiconductor layer formed on the anti-diffusion layer, a gate insulating layer deposited on the semiconductor layer, a second conductive layer formed on the gate insulating layer, an interlayer insulating layer deposited on the second conductive layer, and a third conductive layer formed on the interlayer insulating layer, in a first contact hole penetrating through the interlayer insulating layer and the gate insulating layer to reach the semiconductor layer, and in a second contact hole penetrating through the interlayer insulating layer, the gate insulating layer and the anti-diffusion layer to reach the first conductive layer. The third conductive layer includes a pixel electrode formed in island shape on the interlayer insulating layer.

Abstract: A pixel employable by a display device, including a plurality of transistors, including a first transistor having a gate electrode, and a capacitor including a first terminal connected to the gate electrode of the first transistor and a second terminal that is an intrinsic semiconductor.

Abstract: A thin film transistor (TFT) having a lightly doped drain (LDD) structure includes a lightly doped drain (LDD) region formation pattern, an active layer formed in an uneven structure on the LDD region formation pattern, and having a source region and a drain region having an LDD region. A gate electrode may be formed on a gate insulating layer, and source and drain electrodes are coupled to the source and drain regions.

Abstract: A thin film transistor array substrate includes a polysilicon layer having a predetermined pattern shape formed over a substrate, a first gate insulating film provided over the substrate and on the surface of the polysilicon layer and having a same polished surface as the surface of the polysilicon layer and a second gate insulating film formed to cover the polysilicon layer and the first gate insulating film.

Abstract: An improved field effect transistor formed in the Group III nitride material system includes a two part structure in which a chemical vapor deposited passivation layer of silicon nitride encapsulates a previously sputtered-deposited layer of silicon nitride. The sputtered layer provides some of the benefits of passivation and the chemical vapor deposited layer provides an excellent environmental barrier.

Abstract: A surface mountable device having a circuit device and a base section. The circuit device includes top and bottom layers having a top contact and a bottom contact, respectively. The base section includes a substrate having a top base surface and a bottom base surface. The top base surface includes a top electrode bonded to the bottom contact, and the bottom base surface includes first and second bottom electrodes that are electrically isolated from one another. The top electrode is connected to the first bottom electrode, and the second bottom electrode is connected to the top contact by a vertical conductor. An insulating layer is bonded to a surface of the circuit device and covers a portion of a vertical surface of the bottom layer. The vertical conductor includes a layer of metal bonded to the insulating layer.

Abstract: A light-emitting device and the method for making the same are disclosed. The device includes a substrate, a light-emitting structure and a light scattering layer. The light-emitting structure includes an active layer sandwiched between a p-type GaN layer and an n-type GaN layer, the active layer emitting light of a predetermined wavelength when electrons and holes from the n-type GaN layer and the p-type GaN layer, respectively, combine therein. The light scattering layer includes a GaN crystalline layer characterized by an N-face surface. The N-face surface includes features that scatter light of the predetermined wavelength. The light-emitting structure is between the N-face surface and the substrate.

Abstract: A method or manufacturing an array substrate at a low cost. Silicon patterns are formed. A first impurity is implanted at a high concentration. Gate metal patterns are formed. A second impurity is implanted. The first impurity is implanted at a low concentration. A pixel electrode is formed. The first impurity is simultaneously implanted into partial portions of the pixel pattern part, the storage pattern part, and the driving pattern part.

Abstract: In accordance with the invention a light source for an image projection system comprises one or more LEDs packaged for high temperature operation. Advantageously, the LED die are disposed on a package comprising a ceramic coated metal base including one or more underlying thermal connection pads, and underlying electrical connection pads, each LED die thermally coupled through the metal base to a thermal connection pad and electrically coupled to electrical connection pads. The LED can be mounted directly on the metal of the base or on a thin coating of electrical insulator on the metal. Arrays of LED die thus packaged are advantageously fabricated by the low temperature co-fired ceramic-on-metal technique (LTTC-M) and can be referred to as LTTC-M packaged arrays. The LEDs are advantageously mounted in an array of cavities having tapered sides to reflect light from the LEDs. The high temperature LED light sources can substitute for HID lamps in a variety of front and rear projection systems and displays.

Abstract: Electronic and opto-electronic devices having epitaxially-deposited III/V compounds on vicinal group IV substrates and method for making same. The devices include an AlAs nucleating layer on a Ge substrate. The group IV substrate contains a p-n junction whose change of characteristics during epitaxial growth of As-containing layers is minimized by the AlAs nucleating layer. The AlAs nucleating layer provides improved morphology of the devices and a means to control the position of a p-n junction near the surface of the group IV substrate through diffusion of As and/or P and near the bottom of the III/V structure through minimized diffusion of the group IV element.

Abstract: A pixel includes a photodiode and a transfer transistor. The transfer transistor is formed between the photodiode and a floating node and selectively operative to transfer a signal from the photodiode to the floating node. The transfer transistor has a bird's beak structure formed at the interface of its transfer gate and said floating node. Also included is a reset transistor for resetting the floating node to a voltage reference and an amplification transistor controlled by the floating node.

Abstract: A radiation-emitting thin-film semiconductor chip with an epitaxial multilayer structure (12), which contains an active, radiation-generating layer (14) and has a first main face (16) and a second main face (18)—remote from the first main face—for coupling out the radiation generated in the active, radiation-generating layer. Furthermore, the first main face (16) of the multilayer structure (12) is coupled to a reflective layer or interface, and the region (22) of the multilayer structure that adjoins the second main face (18) of the multilayer structure is patterned one- or two-dimensionally with convex elevations (26).

Abstract: A light emitting device package capable of emitting uniform white light and a method for manufacturing the same are disclosed. The light emitting device package includes a package body, an electrode formed on at least one surface of the package body, a light emitting device mounted on the package body, and a phosphor layer enclosing the light emitting device while having a uniform thickness around the light emitting device.

Abstract: The present invention provides novel methods of forming component carriers, component modules, and the carriers and modules formed therefrom which utilize thick film technology. In some embodiments, these methods are used to form lighting device chip carriers and modules. In further embodiments, these lighting device chip carriers and modules are used in LED applications.

Abstract: A radiation-emitting component (10) having a layer stack (1) which is based on a semiconductor material and which has an active layer sequence (4) for generating electromagnetic radiation, and a filter element (2) which is arranged after the active layer sequence (4) in the irradiation direction (A) and by means of which a first radiation component is transmitted, and a second radiation component is reflected into the layer stack (1), wherein the second radiation component is subjected to a deflection process or an absorption and emission process, and the deflected or emitted radiation impinges on the filter element (2).

Abstract: Light sources are disclosed utilizing LED dies that have a light emitting surface. A patterned low refractive index layer that can support total internal reflection within the LED die is provided in optical contact with a first portion of the emitting surface. In optical contact with a second portion of the emitting surface is an input surface of an optical element. The refractive index of the low index layer is below both that of the optical element and the LED die. The optical element can have a variety of shapes and sizes.

Abstract: A method is provided for forming a rare earth (RE) element-doped silicon (Si) oxide film with nanocrystalline (nc) Si particles. The method comprises: providing a first target of Si, embedded with a first rare earth element; providing a second target of Si; co-sputtering the first and second targets; forming a Si-rich Si oxide (SRSO) film on a substrate, doped with the first rare earth element; and, annealing the rare earth element-doped SRSO film. The first target is doped with a rare earth element such as erbium (Er), ytterbium (Yb), cerium (Ce), praseodymium (Pr), or terbium (Tb). The sputtering power is in the range of about 75 to 300 watts (W). Different sputtering powers are applied to the two targets. Also, deposition can be controlled by varying the effective areas of the two targets. For example, one of the targets can be partially covered.

Abstract: A surface mount light emitting package includes a chip carrier having top and bottom principal surfaces. At least one light emitting chip is attached to the top principal surface of the chip carrier. A lead frame attached to the top principal surface of the chip carrier. When surface mounted to an associated support, the bottom principal surface of the chip carrier is in thermal contact with the associated support without the lead frame intervening therebetween.

Abstract: A light emitting diode package for preventing an electric short circuit among semiconductor layers and with excellent bonding strength. The light emitting diode package includes a package substrate, a light emitting diode chip bonded to an upper surface of the package substrate, and a bonding material for bonding the light emitting diode chip to the package substrate. The package substrate has a recess formed in a bonding surface thereof to accommodate the bonding material.

Abstract: A nitride semiconductor light emitting device includes a conductive substrate, a first metal layer, a second conductivity-type semiconductor layer, an emission layer, and a first conductivity-type semiconductor layer in this order. The nitride semiconductor light emitting device additionally has an insulating layer covering at least side surfaces of the second conductivity-type semiconductor layer, the emission layer and the first conductivity-type semiconductor layer. A method of manufacturing the same is provided. The nitride semiconductor light emitting device may further include a second metal layer. Thus, a reliable nitride semiconductor light emitting device and a method of manufacturing the same are provided in which short-circuit at the PN junction portion and current leak is reduced as compared with the conventional examples.

Abstract: Techniques for fabricating contacts on inverted configuration surfaces of GaN layers of semiconductor devices are provided. An n-doped GaN layer may be formed with a surface exposed by removing a substrate on which the n-doped GaN layer was formed. The crystal structure of such a surface may have a significantly different configuration than the surface of an as-deposited p-doped GaN layer.

Abstract: A method for selectively growing a nitride semiconductor, in which a mask is formed, with an opening formed therein, on a nitride semiconductor layer. A nitride semiconductor crystal is selectively grown on a portion of the nitride semiconductor layer exposed through the opening in the mask, the nitride semiconductor crystal shaped as a hexagonal pyramid and having crystal planes inclined with respect to a top surface of the nitride semiconductor. Here, the nitride semiconductor crystal has at least one intermediate stress-relieving area having crystal planes inclined at a greater angle than those of upper and lower areas of the nitride semiconductor crystal, the intermediate stress-relieving area relieving stress which occurs from continuity in the inclined crystal planes.

Abstract: Embodiments of methods, apparatuses, devices, or systems for forming a photonic device are described.

Abstract: A vertical GaN-based LED comprises an n-electrode; an n-type GaN layer formed under the n-electrode, the n-type GaN layer having an irregular-surface structure which includes a first irregular-surface structure having irregularities formed at even intervals and a second irregular-surface structure having irregularities formed at uneven intervals, the second irregular-surface structure being formed on the first irregular-surface structure; an active layer formed under the n-type GaN layer; a p-type GaN layer formed under the active layer; a p-electrode formed under the p-type GaN layer; and a structure support layer formed under the p-electrode.

Abstract: A semiconductor device includes a photodiode formed using a silicon substrate, a wide-bandgap semiconductor layer formed on the silicon substrate and having a bandgap larger than that of silicon, and a switching element formed using the wide-bandgap semiconductor layer. The switching element is electrically connected to the photodiode so as to be on/off-controlled by a control signal from the photodiode.

Abstract: By a non-selective epitaxial growth method, an SiGe film is grown on the whole surface of a silicon oxide film so as to cover an inner wall of a base opening. Here, such film forming conditions are selected that, inside the base opening, a bottom portion is formed of single crystal, other portions such as a sidewall portion are formed of polycrystalline, and a film thickness of the sidewall portion is less than or equal to 1.5 times the film thickness of the bottom portion. In this non-selective epitaxial growth, monosilane, hydrogen, diborane, and germane are used as source gases. Then, flow rates of monosilane and hydrogen are set to 20 sccm and 20 slm respectively. Also, a growth temperature is set to 650° C., a flow rate of diborane is set to 75 sccm, and a flow rate of germane is set to 35 sccm.

Abstract: A semiconductor memory device such as a dynamic random access memory (DRAM) has substantially non-orthogonal word and bit lines. For a given memory cell size, such as six square lithographic features (6F2), the non-orthogonal layout allows for larger-pitch word and bit lines when compared to the orthogonal layout of the word and bit lines.

Abstract: An improved complementary metal oxide semiconductor (CMOS) image sensor which may decrease the occurrence of dark current is provided. The CMOS image sensor includes a plurality of isolation regions formed in a substrate and a first impurity-doped region formed between the isolation region and separated from a side surface of the isolation region by a predetermined interval.