Abstract: A magnetic random access memory includes a semiconductor substrate having a projection projecting from a substrate surface, first and second gate electrodes and a first source diffusion layer formed on first and second side surfaces and an upper surface of the projection, first and second drain diffusion layers formed in the substrate surface at roots on the first and second side surfaces of the first projection, first and second word lines formed above the semiconductor substrate, a bit line formed above the first and second word lines, a first magnetoresistive effect element formed between the bit line and the first word line, a second magnetoresistive effect element formed between the bit line and the second word line, a first contact which connects the first magnetoresistive effect element and the first drain diffusion layer, and a second contact which connects the second magnetoresistive effect element and the second drain diffusion layer.

Abstract: A chip scale package is disclosed that includes a semiconductor die further comprising an array of power buses electrically coupled to a high power integrated circuit, and a plurality of Under Bump Metallization (UBM) multi-layer power buses disposed parallel to one another and spanning substantially across the entire length of the semiconductor die. The plurality of multi-layer UBM power buses, electrically coupled to the array of power buses, further includes a thick metal layer configured in a geometric shape that have interconnection balls completely posited thereupon.

Abstract: In a memory device and a method of forming the same, in one embodiment, the memory device comprises a first word line structure on a substrate, the first word line structure extending in a first direction. A bit line is provided over the first word line structure and spaced apart from the first word line by a first gap, the bit line extending in a second direction transverse to the first direction. A second word line structure is provided over the bit line and spaced apart from the bit line by a second gap, the second word line structure extending in the first direction.

Abstract: A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the bottom electrode are electrically connected via the first phase-change material. Since the phase-change material can have a diameter less than the resolution limit of the photolithography process, an operating current for a state conversion of the phase-change material pattern may be reduced so as to decrease a power dissipation of the phase-change memory device.

Abstract: A semiconductor device includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a recess channel that is formed on the inner surface of a recess region, which is formed on the semiconductor substrate between the source and drain regions, and in an epitaxial semiconductor film in which dopants are doped. The semiconductor device further includes a gate insulating film formed on the recess channel, and a gate electrode that fills the recess region and is formed on the gate insulating film.

Abstract: Image sensors include a pixel region and a logic region. Pixel isolation regions in the pixel region include pixel isolation region walls that are less sloped than logic isolation region walls in the logic region. An impurity layer also may be provided adjacent at least some of the pixel isolation region walls, wherein at least some of the logic isolation region walls are free of the impurity layer. The impurity layer and/or the less sloped logic isolation region walls may also be provided for NMOS devices in the logic region but not for PMOS devices in the logic region. Doped sacrificial layers may be used to fabricate the impurity layer.

Abstract: Embodiments relate to a CMOS image sensor and a fabricating method thereof. In embodiments, a linear nitride layer formed on a semiconductor substrate may protect a gate oxide layer during a process of removing a silicide barrier layer, and may improve the performance of an CMOS image sensor.

Abstract: A photoelectric conversion element comprises a photoelectric conversion section that includes: a pair of electrodes; and a photoelectric conversion layer disposed between the pair of electrodes, wherein the photoelectric conversion section further comprises between one of the pair of electrodes and the photoelectric conversion layer a first charge-blocking layer that restrains injection of charges from the one of the electrodes into the photoelectric conversion layer when a voltage is applied to the pair of electrodes, and the first charge-blocking layer comprises a plurality of layers.

Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor and a method of driving the CMOS image sensor that can reduce the number of devices required by each of a plurality of pixels and can stably drive the pixels, in which each of the pixels includes a photodiode that converts light energy into an electrical signal, a transfer transistor that transmits photocarriers stored in the photodiode to a floating diffusing region, a drive transistor that has a gate connected to the floating diffusion region and drives a voltage signal according to a voltage of the floating diffusion region, the voltage signal being output to an external device, and a capacitive device that is connected between a control voltage source and the floating diffusion region and, when a sensing operation of a corresponding pixel is terminated, deselects the pixel by altering the voltage of the floating diffusion region according to a control voltage provided by the control voltage source.

Abstract: A CMOS image sensor includes isolation regions and a photo diode region formed in a substrate, gate electrodes formed on the substrate, impurity injection regions formed in the substrate respectively positioned between the gate electrodes and the isolation regions, silicide regions formed on upper surfaces of the gate electrodes and the impurity injection regions, a first insulating layer formed on a surface of the photodiode region and sides of the gate electrodes, a second insulating layer formed on the first insulating layer, a third insulating layer formed on the second insulating layer, an interlayer insulating layer formed to cover the third insulating layer, and via plugs vertically passing through the interlayer insulating layer and connected to the silicide regions.

Abstract: An image sensor includes a semiconductor substrate, a photo receiving area in the semiconductor substrate, a gate electrode installed in a lateral side of the photo receiving area on the semiconductor substrate, and a patterned dielectric layer covering the gate electrode, the photo receiving area, and exposing a partial gate electrode. A spacer surrounds the gate electrode on the dielectric layer.

Abstract: Example embodiments may provide a CMOS image sensor and example methods of forming the same. Example embodiment CMOS image sensors may include a transfer gate insulating pattern between a transfer gate and an active region. A photodiode region and/or a floating doped region may be in the active region at either side of the transfer gate. The transfer gate insulating pattern may include a first part adjacent to the photodiode region and/or a second part adjacent to the floating doped region. The first part may be thicker than the second part.

Abstract: A semiconductor device includes a ferroelectric capacitor formed above the lower interlevel insulating film covering a MOS transistor formed on a semiconductor substrate, including lamination of a lower electrode, an oxide ferroelectric film, a first upper electrode made of conductive oxide having a stoichiometric composition AOx1 and an actual composition AOx2, a second upper electrode made of conductive oxide having a stoichiometric composition BOy1 and an actual composition BOy2, where y2/y1>x2/x1, and a third upper electrode having a composition containing metal of the platinum group; and a multilayer wiring structure formed above the lower ferroelectric capacitor, and including interlevel insulating films and wirings. Abnormal growth and oxygen vacancies can be prevented which may occur when the upper electrode of the ferroelectric capacitor is made of a conductive oxide film having a low oxidation degree and a conductive oxide film having a high oxidation degree.

Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: The present invention discloses a low-noise single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the electrically-conductive gate of the transistor and the electrically-conductive gate of the capacitor structure are interconnected to form a single floating gate of a memory cell; an ion-doped buried layer is formed between the dielectric layer of the capacitor structure and the semiconductor substrate to reduce the external interference on the capacitor structure and control the initial threshold voltage; a reverse bias may be used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of the low-noise single-gate non-volatile memory having an isolation well, positive and negative voltages may be applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer, and thereby, the absolute voltage, the area of th

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: A semiconductor memory device includes: a transistor formed in a substrate; a capacitor formed above one of source/drain regions of the transistor; a bit line formed above the substrate and extending in the gate length direction of the transistor; a first conductive plug connecting one of the source/drain regions and the capacitor; a second conductive plug connected to the other source/drain region that is not connected to the first conductive plug; and a third conductive plug formed on the second conductive plug and connected to the bit line. The central axis of the third conductive plug is displaced from the central axis of the second conductive plug in the gate width direction of the transistor.

Abstract: A method of forming box-shaped cylindrical storage nodes includes forming an interlayer insulating layer on a semiconductor substrate. Buried contact plugs are formed to penetrate the interlayer insulating layer. A molding layer and a photoresist layer are then sequentially formed on the substrate. Using a first phase shift mask having line-and-space patterns, the photoresist layer is exposed, forming first exposure regions. Using a second phase shift mask having line-and-space patterns, the photoresist layer is exposed again, forming second exposure regions intersecting the first exposure regions. The photoresist layer is then developed, forming a photoresist pattern having rectangular-shaped openings formed at intersections of the first and the second exposure regions. The molding layer is etched using the photoresist pattern as an etch mask, forming storage node holes exposing the buried contact plugs. Storage nodes are formed inside the storage node holes.

Abstract: A semiconductor structure that may be a discrete capacitor, a Silicon On Insulator (SOI) Integrated Circuit (IC) including circuits with discrete such capacitors and/or decoupled by such discrete capacitors and an on-chip decoupling capacitor (decap). One capacitor plate may be a well (N-well or P-well) in a silicon bulk layer or a thickened portion of a surface silicon layer. The other capacitor plate may be doped polysilicon and separated from the first capacitor plate by capacitor dielectric, e.g., CVD or thermal oxide. Contacts to each of the capacitor plates directly connect and extend from the respective plates, such that direct contact is available from both plates.

Abstract: A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.

Abstract: The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.

Abstract: Embodiments relate to a mask in which a mask pattern used for forming a contact hole may be designed such that any one of a horizontal-axis length and a vertical-axis length may be greater than the other in a photolithography process for forming the contact hole. In embodiments, a method for fabricating a mask having a plurality of patterns for forming a contact hole may be provided, in which the pattern may be designed differently depending on a distance between contact holes to be formed.

Abstract: A one time programmable memory including a first memory cell is provided. The first memory cell is disposed on a substrate having a trench disposed therein. The first memory cell includes a floating gate, a select gate, a first doped region, a second doped region and a third doped region. The floating gate is disposed on the sidewall of the trench. The select gate is disposed on the substrate outside the trench. The first doped region is disposed in the substrate at the bottom of the trench. The second and third doped regions are disposed in the substrate on both sides of the trench, and the second doped region is disposed between the floating gate and the select gate.

Abstract: An array of memory cells with non-volatile memory transistors having a compact arrangement of diagonally symmetric floating gates. The floating gates have portions extending in both X and Y directions, allowing them to be charged through a common tunnel oxide 8stripe that runs under a portion of each, for example a portion running in the X-direction while the two Y-direction portions serve to establish a channel. Shared source/drain regions are established between and in proximity to the Y-direction portions to define two non-volatile memory transistors in each memory cell. Memory cells are replicated in the word line direction and then mirrored with respect to the word line to form the next row or column. This geometry is contactless because the word line and source/drain regions are all linear throughout the array so that electrical contact can be established outside of the array of cells. Each transistor can be addressed and thus programmed and erased or pairs of transistors in a line can be erased, i,.e.

Abstract: A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.

Abstract: One embodiment of a method of fabricating a flash memory device includes forming a trench mask pattern, which includes a gate insulation pattern and a charge storage pattern stacked in sequence, on a semiconductor substrate; etching the semiconductor substrate using the trench mask pattern as an etch mask to form trenches defining active regions; and sequentially forming lower and upper device isolation patterns in the trench. After sequentially forming an intergate insulation film and a control gate film on the upper device isolation pattern, the control gate film, the intergate insulation pattern and the gloating gate pattern are formed, thereby providing gate lines crossing over the active regions.

Abstract: The semiconductor device which is hard to generate malfunction and whose reliability of an element is high, and its manufacturing method are offered. Each of a plurality of convex patterns is formed on the front surface of a semiconductor substrate so that it may have a floating gate and a control gate. The insulating layer has covered the side surface and the upper surface of a plurality of convex patterns, and the bottom between convex patterns. A contact interlayer insulating layer covers the cavity part located via an insulating layer between a plurality of convex patterns and on a plurality of convex patterns, and has a through hole. An insulating layer closes a through hole and occludes the cavity part.

Abstract: A method of fabricating a semiconductor device having a non-volatile memory cell includes forming an insulation layer as an uppermost/outermost portion of the memory cell to enhance the charge retention capability of the memory cell. The insulation layer is formed after the gate structure and integrate dielectric of the non-volatile memory cell, and a gate of a logic transistor are formed. The insulation layer thus enhances the function of the intergate dielectric. Subsequently, a conductive layer is formed on the substrate including over the gate of the logic transistor. A silicide layer is then formed on the gate of the logic transistor and on the substrate adjacent opposite sides of the gate. The insulation layer thus also serves prevent the formation of a silicide layer on the non-volatile memory cell.

Abstract: This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench (SGT) structure below and insulated from the trenched gate. The SGT structure is formed substantially as a round hole having a lateral expansion extended beyond the trench gate and covered by a dielectric linen layer filled with a trenched gate material. The round hole is formed by an isotropic etch at the bottom of the trenched gate and is insulated from the trenched gate by an oxide insulation layer. The round hole has a lateral expansion beyond the trench walls and the lateral expansion serves as a vertical alignment landmark for controlling the depth of the trenched gate.

Abstract: A trenched semiconductor power device that includes a trenched gate disposed in an extended continuous trench surrounding a plurality of transistor cells in an active cell area and extending as trench-gate fingers to intersect with a trenched gate under the gate metal runner at a termination area. At least one of the trench-gate fingers intersects with the trenched gate under the gate metal runner near the termination area having trench intersection regions vulnerable to have a polysilicon void and seam developed therein.

Abstract: A process for fabricating a trench power semiconductor device is disclosed. A first dielectric layer between the pad oxide layer and the mask oxide layer is formed so as to form a gate with a height higher than the surface of the pad oxide layer after the first dielectric layer is removed. In addition, a sidewall structure is formed at laterals of the gate protruded from the surface of the trench structure. Hence the source structure and the first conductive layer formed at the surface of the gate can be isolated through the sidewall structure. When the trench power semiconductor device is processed at high frequency, the net resistance of the gate can be reduced by the first conductive layer, and thus the electrical properties thereof can be elevated.

Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

Abstract: A semiconductor device includes an upper gate trench crossing an active region of a semiconductor substrate, a lower gate trench overlapping the upper gate trench at both ends, disposed at a lower level than the upper gate trench, and having a smaller width than the upper gate trench and wherein the lower gate trench is spaced apart from sidewalls of the upper gate trench. The semiconductor device further includes a gate pattern partially covering the bottom of the upper gate trench between the sidewall of the upper gate trench and the lower gate trench, filling the lower gate trench, and covering sidewalls of the active region adjacent to the bottom and sidewalls of the lower gate trench.

Abstract: This semiconductor device comprises a drift layer of a first conductivity type formed on a drain layer of a first conductivity type, and a drain electrode electrically connected to the drain layer. A semiconductor base layer of a second conductivity type is formed in a surface of the drift layer, and a source region of a first conductivity type is further formed in the semiconductor base layer. A source electrode is electrically connected to the source region and a semiconductor base layer. Plural gate electrodes are formed through a gate insulation film so that a semiconductor base layer may be sandwiched by the gate electrodes. The width of the semiconductor base layer sandwiched by the gate electrodes is 0.3 micrometers or less.

Abstract: A power semiconductor device that includes a plurality of source trenches that extend to a depth below the gate electrodes and a termination region that includes a termination trench that is as deep as the source trenches.

Abstract: A semiconductor device and a method of manufacturing the same are provided, capable of minimizing a size of the semiconductor device and inhibiting punch through. According to an embodiment, at least one conductive bar is formed in a substrate between source and drain regions. Thereby, punch through can be inhibited to the utmost to increase breakdown voltage, and thus the electrical properties of the device can be improved. Further, because the punch through is inhibited, the size of the device can be minimized without degrading the electrical properties of the device.

Abstract: A system for displaying images. The system comprises a thin film transistor (TFT) device comprising a substrate having a pixel region. An active layer is disposed on the substrate of the pixel region, comprising a channel region, a pair of source/drain regions separated by the channel region. The channel region comprises dopants with a first conductivity type and a second conductivity type opposite to the first conductivity type. A gate structure is disposed on the active layer, comprising a stack of a gate dielectric layer and a gate layer. A method for fabricating a system for displaying images including the TFT device is also disclosed.

Abstract: A semiconductor device having an SOI structure including a semiconductor substrate, a buried insulating layer and an SOI layer including, first and second element formation regions provided in said SOI layer, a partial isolation region including a partial insulating film provided in an upper layer portion of said SOI layer and a semiconductor region to be a part of said SOI layer which is provided under said partial insulating film and serving to isolate said first and second element formation regions from each other, and first and second MOS transistors formed in said first and second element formation regions, respectively, wherein at least one of a structure of a body region, a structure of a gate electrode and presence/absence of body potential fixation in said first and second MOS transistors is varied to make transistor characteristics of said first and second MOS transistors different from each other.

Abstract: A fin field-effect transistor has a substrate and a fin structure above the substrate, as well as a drain region and a source region outside the fin structure above the substrate. The fin structure serves as a channel between the source region and the drain region. The source and drain regions are formed once a gate has been produced.

Abstract: The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating material within each of the plurality of trenches, the layer of insulating material having a thickness that is less than the depth of the trenches, and performing an anneal process on the substrate in a hydrogen environment to cause the silicon substrate material to merge above the layer of insulating material within the plurality of trenches to thereby define a pseudo SOI substrate.

Abstract: Methods of forming thin-film transistor display devices including forming a gate line and a gate electrode on a face of a substrate and forming a semiconductor layer that is insulated from the gate line. A data line and a source/drain electrode are formed on the semiconductor layer. The data line and the source/drain electrode are formed as composites of at least two different metal conductive layers. A transparent pixel electrode is formed that is electrically coupled to the drain electrode.

Abstract: A semiconductor structure and the associated method for fabricating the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a back gate region on the semiconductor substrate, (c) a back gate dielectric region on the back gate region, (d) a semiconductor region on the back gate dielectric region comprising a channel region disposed between first and second source/drain (S/D) regions, (e) a main gate dielectric region on the semiconductor region, (f) a main gate region on the main gate dielectric region, (g) a first contact pad adjacent to the first S/D region and electrically insulated from the back gate region, and (h) a first buried dielectric region that physically and electrically isolates the first contact pad and the back gate region, and wherein the first buried dielectric region has a first thickness in the first direction at least 1.5 times a second thickness of the back gate region.

Abstract: A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth process. The in-situ doped epitaxial pattern has a conformal impurity concentration throughout. Accordingly, source/drain regions with a conformal impurity concentration are connected throughout a channel width of a channel region including both sidewalls of a protruded channel pattern. As a result, it is possible to maximize a driving current of the filed effect transistor, and an on-off characteristic can be highly stabilized.

Abstract: Surge current, which flows-in from an exterior due to ESD or the like, is prevented from directly flowing-into a supporting substrate. A semiconductor device has: an element-isolating insulating film sectioning an SOI layer into an active region and a field region; a resistance element formed at the field region; one or more layers of an interlayer insulating films formed on an SOI substrate; a ground terminal for a substrate contact formed on the interlayer insulating film; a substrate contact passing through the element-isolating insulating film and a BOX layer, and electrically connected to the supporting substrate; a first wire electrically connecting the substrate contact and the resistance element; and a second wire electrically connecting the resistance element and the ground terminal for a substrate contact.

Abstract: A backlighted membrane switch includes a circuit board having a number of switch contacts, a plate spaced away from the circuit board and having a number of conductor contacts aligned with the switch contacts of the printed circuit for being selectively depressed to engage with the switch contacts of the printed circuit by key pads. A spacing device may space the conductor contacts of the plate from the switch contacts of the printed circuit of the circuit board. An electroluminescent device is integrated onto the plate for being selectively energized to generate a backlight and for suitably reducing the weight and the thickness of the membrane switch, and the manufacturing processes and the cost of the membrane switch.

Abstract: A semiconductor apparatus having an outer ESD protective circuit corresponding to each external connection terminal, the outer ESD protective circuit being formed in a peripheral region around the external connection terminals. The outer ESD protective circuit discharges electrostatic voltage from the external connection terminal and avoids the damaging of an internal circuit of the semiconductor apparatus. Accordingly, the ESD withstanding voltage of the semiconductor apparatus is improved.

Abstract: Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the <100> direction. Additionally, longitudinal tensile stress is applied to the channels.

Abstract: A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1.

Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 ?.