Abstract: A package substrate including a circuit board, a reinforcing plate and at least one conductive channel is provided. A first surface of the reinforcing plate is disposed on the circuit board for resisting the warpage of the circuit board. The reinforcing plate has an opening corresponding to a first contact of the circuit board exposed thereon. In addition, one end of the conductive channel is located in the opening and electrically connected to the first contact, and the other end of the conductive channel is located on a second surface of the reinforcing plate to form a bonding pad.

Abstract: The invention relates to a method in which components (101, 102) are provided, movement elements (104) are in each case applied to surfaces of a number of the components (101), and the components (101, 102) are stacked, so that one or a plurality of the movement elements (104) are situated between adjacent components (101, 102) and the components (101, 102) are held in their position by connecting elements (103).

Abstract: A microelectronic element package has one or more individual carrier units overlying a region or regions of the front or rear surface of the microelectronic element, leaving other regions of the microelectronic element surface uncovered. The carrier units can be made economically using only a small area of a dielectric film or other circuit panel material.

Abstract: An electronic device includes: at least one electronic chip comprising a first coefficient of thermal expansion (CTE); and a carrier including a top side connected to the bottom side of the chip by solder bumps. The carrier further includes a second CTE that approximately matches the first CTE, and a plurality of through vias from the bottom side of the carrier to the top side of the carrier layer. Each through via comprising a collar exposed at the top surface of the carrier, a pad exposed at the bottom surface of the carrier, and a post disposed between the collar and the pad. The post extends thorough a volume of space.

Abstract: A multi-chip structure at least including a first chip, a second chip and a first thermal-conductive layer is provided. The first chip has a first surface and a plurality of first pads disposed on the first surface. The second chip has a second surface facing the first surface and a plurality of second pads disposed on the second surface. The first thermal-conductive layer is disposed between the first chip and the second chip and includes a thermal-conductive area, a plurality of first electrical connection members and a plurality of first dielectric areas. The first electrical connection members disposed in the first thermal-conductive layer are used to electrically connect the first surface and the second surface. The first dielectric areas surround and insulate the first electrical connection members from the thermal-conductive area.

Abstract: A semiconductor package has a base, a chip attached to the base a flexible connection plate mounted on and electrically connecting the chip and the base, and an encapsulant encapsulating the chip and the flexible connection plate on the base. The flexible connection plate includes a film and a layer of leads integrated with the film. Inner ends of the leads located at a central portion of the flexible connection plate are connected to contact pads of the chip, and outer ends of the leads located at an outer peripheral portion of the flexible connection plate are connected to leads of the base.

Abstract: A semiconductor device according to embodiments may include an interposer, a plurality of devices stacked on the interposer, a cooling device provided in at least one of the devices and including a passage for a cooling material, and a connection electrode provided between the devices, in which the connection electrode connects a signal electrode in an upper device to a signal electrode in a lower device.

Abstract: An electronic device or devices and method for producing a device is disclosed. One embodiment provides an integrated component, a first package body and a contact device. The contact device penetrates the package body.

Abstract: A method is disclosed for packaging semiconductor chips on a flexible substrate employing thin film transfer. The semiconductor chips are placed on a temporary adhesive substrate, then covered by a permanent flexible substrate with a casting layer for planarizingly embedding the chips on the permanent substrate before removing the temporary substrate. With the surface of the chips coplanar with the surface of the complete structure without any gaps, interconnect metal lines can be easily placed on the uninterrupted surface, connecting the chips and other components.

Abstract: The present invention provides a package structure with lead-frame on stacked chips, comprising: a lead-frame, composed of a plurality of outer leads arranged in rows facing each other and a plurality of inner leads arranged in rows facing each other formed by a plurality of wires, wherein the plurality of inner leads are divided into first inner leads and second inner leads, and the length of the first inner leads is greater than that of the second inner leads; and a plurality of semiconductor chip devices. The active surface of each chip faces upward and chips are misaligned to form offset stacked structure, wherein the semiconductor chip device stacked uppermost is fixedly connected under said first inner leads, and the plurality of semiconductor chip devices are electrically connected to the first inner leads and the second inner leads on the same side edge.

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment in accordance with the invention, a form standard associated with one or more CSPs provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the contacts of the lower CSP will be compressed before flex circuitry is attached to a combination of the CSP and a form standard to create lower profile contacts between CSP and the flex circuitry.

Abstract: A production equipment includes a substrate 2 placed inside and having a plurality of semiconductor elements 3 mounted thereon, and a resin molding mold 20 having a cavity 21. The mold 20 has resin injection ports 29a and air release ports 30a. Each of the resin injection ports 29a is formed in a top surface portion of the cavity in the mold in association with the corresponding semiconductor element 3. Each of the air release ports 30a is formed around each of the resin injection ports 29a.

Abstract: There is provided herein exemplary embodiments of a semiconductor device constructed in accordance with the present invention. The device comprises: a semiconductor chip having a lateral power transistor device formed therein. The chip has an upper surface and source, drain and gate contact terminals on the upper surface thereof. Each of the source, drain and gate contact terminals have a conductive ball or pillar bump thereon. A metal lead frame spans the upper surface of the chip, the metal lead frame being in electrical contact with the conductive balls or pillar bumps. A capsule encases the chip and at least a portion of the metal lead frame such that opposite ends of the metal lead frame protrudes from opposite sides of the capsule.

Abstract: A high-density electrical package utilizing an array of high performance demountable electrical contacts such as UEC, T-Spring, F-Spring and their equivalent contained in a carrier in the form of an interposer between one or more components and a substrate. The carrier is made of a thermally conductive metal or contains thermally conductive metal to provide heat-spreading or dissipation functions in addition to the function of the retention and alignment of the electrical contacts. The above interposer is used for chip attach for a single chip or a stack of chips in the package. The interposer provides electrical connections through individual electrical contact to another chip or to the substrate of the package. It provides also the heat spreading or dissipation function to the chips connected thermally to a particular interposer. The interposer can further be connected thermally to an external heat spreader when necessary.

Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor die and an electrically conductive attachment region having a first attachment surface and a second attachment surface. The first attachment surface is arranged for electrical communication with the semiconductor die. An interlayer material is formed on the second attachment surface of the electrically conductive attachment region. The interlayer material is a thermally conductive, dielectric material. A housing at least in part encloses the semiconductor die and the interlayer material.

Abstract: A semiconductor device mountable to a substrate includes a semiconductor die and an electrically conductive attachment region having a first attachment surface and a second attachment surface. The first attachment surface is arranged for electrical communication with the semiconductor die. A housing at least in part encloses the semiconductor die and the interlayer material. The housing has a recess disposed through the second attachment surface of the electrically conductive attachment region. A dielectric, thermally conductive interlayer material is located in the recess and secured to the housing. A metallic plate is located in the recess and secured to the interlayer material.

Abstract: This invention relates to a package unit including a semiconductor package that houses a semiconductor chip, and a heat sink attached thereto. A peripheral wall section that surrounds a thermal junction member is provided on a stiffener. More preferably, a tip end section of the peripheral wall section is allowed to fit into a slit provided on the heat sink. The peripheral wall section may be provided on a heat spreader instead. It is possible to prevent the thermal junction member from falling outside without incurring addition of new components or new occupancy of the area on a system substrate.

Abstract: A hermetically sealed package for electronic circuit components includes a generally hollow, titanium body, having a reduced thickness bottom wall/floor, whose interior surface is laminated with a relatively low mass, insert, upon which electronic circuit components are mounted. The insert has a high thermal conductivity and a low coefficient of thermal expansion, approximate to that of the housing body.

Abstract: A method for cooling a semiconductor including passive cooling including transferring heat via passive cooling components; active cooling including transferring heat via active cooling components; and controlling the active cooling based on temperature of the semiconductor. A cooling system for a semiconductor including: a passive component in thermal contact with the semiconductor; an active cooling component in thermal contact with the semiconductor; and a controller controlling the active cooling component.

Abstract: A package structure and a heat sink module thereof are provided. The package structure includes a substrate, a chip and a heat sink module. The chip is disposed on the substrate. The heat sink module includes a supporting ring and a heat sink plate. The supporting ring is disposed on the substrate and surrounds the chip. Four recesses are formed on an upper surface of the supporting ring. The heat sink plate is disposed on the chip and includes four protruding parts lodged in the recesses.

Abstract: A wirebond-less packaged semiconductor device includes a plurality of I/O contacts, at least one semiconductor die, the semiconductor die having a bottom major surface and a top major surface, the top major surface having at least two electrically isolated electrodes, and a conductive clip system disposed over the top major surface, the clip system comprising at least two electrically isolated sections coupling the electrodes to respective I/O contacts.

Abstract: The conductive connection structure of the present invention comprises a circuit board, a plurality of conductive pads, a solder mask layer, an electroless plating copper layer, and an electroless plating adhesive layer. The manufacturing method comprises the following steps: providing the circuit board having a plurality of conductive pads thereon; forming the solder mask layer, the electroless plating copper layer, and the electroless plating adhesive layer respectively on the surface of the circuit board, and forming a solder bump on the electroless plating adhesive layer. By the assistance of the conductive connection structure and the manufacturing method thereof, cavity otherwise formed on the conductive pads can be prevented, and the solder bumps therefore are firmly fixed on the conductive pads. Moreover, the stress in the surface between the solder bump and the conductive pad can be reduced as the semiconductor chip and the circuit board are combined.

Abstract: A chip package with an anti-creeping underfill is provided. The chip package includes a carrier, a chip and an underfill. The chip is disposed on the carrier and includes a chip body and a blocking portion. The chip body has at least one lateral surface and the blocking portion is formed on the lateral surface. The blocking portion has a top surface and a bottom surface. The top surface and the bottom surface form an acute angle. The underfill is formed between the carrier and the chip and blocked by the blocking portion to prevent creeping.

Abstract: An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.

Abstract: Provided is a multi-chip package in which a plurality of semiconductor chips having different sizes are stacked. A multi-chip package may include a substrate, and a plurality of semiconductor chips stacked on the substrate, each of the plurality of semiconductor chips having a different size. Each of the plurality of semiconductor chips including a pad group and a reference region associated with the pad group, each pad group having a plurality of pads, and the plurality of pads in each pad group located at same coordinates with respect to the associated reference region, and each of the plurality of semiconductor chips having their reference regions vertically aligned.

Abstract: The semiconductor device which can prevent destruction of a low dielectric constant film and a bump's destruction which consists of lead free solder both is obtained. A semiconductor package which has a semiconductor chip including a low dielectric constant film and a bump which consists of lead free solder, a wiring substrate by which flip chip junction of the semiconductor package was done via the bump, and under-filling resin, with which a gap between the semiconductor package and the wiring substrate is filled up, are provided. As for under-filling resin, the glass transition temperature is equal to or more than 125° C., the coefficient of thermal expansion in 125° C. is less than 40 ppm/° C., and the elastic modulus in 25° C. is less than 9 GPa.

Abstract: A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.

Abstract: A circuit board and a semiconductor package having the same are provided. The circuit board comprises a base substrate having interconnections, and solder ball lands disposed on one surface of the base substrate. The solder ball lands respectively have land holes having different sizes. The land hole disposed at the center portion of the base substrate and the land hole disposed at the edge portion of the base substrate may have different sizes. For example, the sizes of the land holes may increase from the center portion of the base substrate to the edge portion thereof, and alternatively, the sizes of the land holes may decrease from the center portion of the base substrate to the edge portion thereof.

Abstract: A semiconductor device provided with a semiconductor chip wherein an electrode pad is formed on a circuit formation surface, includes a first passivation film, which serves as an adhering layer; a second passivation film formed on the first passivation film, for protecting the semiconductor chip from external physical damage; a metal film formed so as to cover at least a first electrode-pad opening section of the first passivation film; and an external connection terminal to connect the electrode pad to an external equipment. A second electrode-pad opening section of the second passivation film is formed so as to expose the first electrode-pad opening section entirely. The second passivation film is formed so as not to be in direct contact with the electrode pad.

Abstract: Apparatuses and methods for forming displays are claimed. One embodiment of the invention relates to depositing a plurality of blocks onto a substrate and is coupled to a flexible layer having interconnect deposited thereon. Another embodiment of the invention relates to forming a display along a length of a flexible layer wherein a slurry containing a plurality of elements with circuit elements thereon washes over the flexible layer and slides into recessed regions or holes found in the flexible layer. Interconnect is then deposited thereon. In another embodiment, interconnect is placed on the flexible layer followed by a slurry containing a plurality of elements.

Abstract: The present invention provides a semiconductor apparatus having the improved thermal fatigue life against temperature change by lowering the maximum temperature on a jointing member existing between a semiconductor element and an electrode terminal and reducing the range of the temperature change.

Abstract: A semiconductor device includes a semiconductor substrate, and an interlayer wiring structure further including a lower wiring layer formed on the semiconductor substrate, a first interlayer an interlayer wiring layer including an interlayer insulating film formed on the lower wiring layer and including a first upper surface and a second upper surface, the first upper surface being higher than the second upper surface relative to a surface of the semiconductor substrate, a contact plug formed in the interlayer insulating film and including a first bottom surface contacting to the lower wiring layer, a third upper surface flush with the second upper surface and a fourth upper surface flush with the first upper surface, an upper wiring layer formed on the first and third upper surfaces and including a first side surface and a second side surface opposite to the first side surface, and a second interlayer insulating film formed on the second and fourth upper surfaces.

Abstract: Provided, is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO2. Alternatively, the via region of the interconnect structure may be strengthened with a mechanically rigid dielectric comprising SiO2, SiCOH, or doped silicate glass.

Abstract: A method, in which the semiconductor components forming part of an electronic circuit, or at least some of them, are embedded in a base, such as a circuit board, during the manufacture of the base, when part of the base structure is, as it were, manufactured around the semiconductor components. Through-holes for the semiconductor components are made in the base, in such a way that the holes extend between the first and second surface of the base. After the making of the holes, a polymer film is spread over the second surface of the base structure, in such a way that the polymer film also covers the through-holes made for the semiconductor components from the side of the second surface of the base structure. Before the hardening, or after the partial hardening of the polymer film, the semiconductor components are placed in the holes made in the base, from the direction of the first surface of the base.

Abstract: This disclosure provides a technique that prevents debonding at an interface between a functional device and a resin on reflow soldering in a functional device-mounted module requiring a hollow structure. Also disclosed is a functional device having a functional portion mounted on a substrate formed with predetermined wiring patterns, wherein the functional portion of the functional device is arranged in a receiving space, and the substrate is provided with a hole which communicates with the receiving space and a solder-introducing portion made of a metallic material compatible with solder. During solder reflowing, the functional device-mounted module is placed on a mounting substrate such that the solder-introducing portion of the functional device-mounted module contacts a solder paste, and solder is melted with heat. Water inside the receiving space is thus discharged, and solder is introduced into the hole due to surface tension, and the interior of the receiving space is sealed.

Abstract: A semiconductor device includes a first interlayer insulating film formed above a semiconductor substrate, a first source line formed on the first interlayer insulating film, a second interlayer insulating film formed on the first source line, a plurality of bit lines formed on the second interlayer insulating film so as to extend in a direction, the bit lines being arranged at same width and same width, a third interlayer insulating film formed above the bit lines, a second source line formed on the third interlayer insulating film, and a source shunt line formed between the second and third interlayer insulating films, the source shunt line electrically connecting the first and second source lines to each other, the source shunt line being located between the bit lines so as to extend in the same direction as the bit lines, the source shunt line including a width same as the bit lines.

Abstract: A semiconductor multi-package module having stacked second and first packages, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding, and in which the first package is a flip chip ball grid array package in a die-up configuration. Also, a method for making a semiconductor multi-package module, by providing a first package including a first package substrate and having a die-up flip chip configuration, affixing a second package including a second package substrate an upper surface of the first package, and forming z-interconnects between the first and second package substrates.

Abstract: A flip-chip semiconductor package and method of manufacture thereof, the flip-chip semiconductor being highly reliable due to suppression of cracking. The flip-chip semiconductor package is formed by flip-chip bonding of a semiconductor chip-connecting electrode surface of a circuit board 1 and an electrode surface of a semiconductor chip 2, dispensing of an encapsulation resin 4 between the circuit board 1 and the semiconductor chip 2, and formation of fillet 4b by providing the encapsulation resin 4 on peripheral side portions of the semiconductor chip, the fillet 4b having inclined surfaces extending from upper edges 2a of the peripheral side portions of the semiconductor chip 2 outward toward the circuit board, wherein the angle of inclination formed between the inclined surfaces and the peripheral side portions of the semiconductor chip 2 is 50 degrees or less in the vicinity of the upper edges of the peripheral side portions 2a of the semiconductor chip.

Abstract: A universal interconnect device for mounting and interconnecting a semiconductor integrated circuit die in preparation for mounting to another substrate such as a printed circuit board. The device consists of a laminate substrate having a first surface upon which the integrated circuit die may be mounted. Underlying and surrounding the die mount area is a plurality of substantially concentric electrically-conductive paths. Each of the plurality of paths is electrically isolated from each other and at least one of the plurality of electrically-conductive paths is located near an outer periphery of the laminate substrate. A plurality of vias traverse the laminate substrate a plurality of bonding features is mounted on a second surface of the substrate. Each of the bonding features is electrically isolated both from one another and from the plurality of paths but is electrically connectable to one or more of the paths through the plurality of vias.

Abstract: A method for producing a component and device including a component is disclosed. A basic substrate having paper as substrate material is provided, at least one integrated circuit is applied to the basic substrate, the at least one integrated circuit applied on the basic substrate is enveloped with an encapsulant, and at least parts of the basic substrate are removed from the at least one enveloped integrated circuit.

Abstract: Elongated solder masses are formed by contacting the molten solder with the walls of holes in a dielectric layer overlying the front face of a chip element such as a wafer. The elongated solder masses have a relatively large aspect ratio, or ratio of height to maximum diameter, and thus provide a high reliability connection with a relatively small diameter compatible with closely spaced contacts on the chip.

Abstract: A process for synthesizing a metal telluride is provided that includes the dissolution of a metal precursor in a solvent containing a ligand to form a metal-ligand complex soluble in the solvent. The metal-ligand complex is then reacted with a telluride-containing reagent to form metal telluride domains having a mean linear dimension of from 2 to 40 nanometers. NaHTe represents a well-suited telluride reagent. A composition is provided that includes a plurality of metal telluride crystalline domains (PbTe)1-x-y(SnTe)x(Bi2Te3)y ??(I) having a mean linear dimension of from 2 to 40 nanometers inclusive where x is between 0 and 1 inclusive and y is between 0 and 1 inclusive with the proviso that x+y is less than or equal to 1. Each of the metal telluride crystalline domains has a surface passivated with a saccharide moiety or a polydentate carboxylate.

Abstract: The invention relates to a corrugated criss-crossing packing structure for installations that transfer material and/or heat between a gas phase and a liquid phase, comprising a first surface (10), called the primary surface, having a number of parallel channels (11). According to the invention, this structure has a second surface (20), called the secondary surface, comprised of a number of secondary packing elements (21, 31), each secondary packing element being placed inside a channel (11) of said primary surface (10) and being formed separately from the first surface. The invention is for use in cryogenic distillation.

Abstract: An object of the present invention is to provide a technique making it possible to easily manufacture a multi-channel optical module in which optical elements are air-sealed. In the optical module, a package 111 with optical elements mounted thereon is sealed with a transparent plate 109. Above a sealing window of the package, a lens plate 105 having holes 104 or grooves 201 and engagement pins 101 are engaged and optically aligned with each other.

Abstract: The invention concerns a process for forming at least one coating layer on a toric surface of an optical article which comprises: providing an optical article 1 having a toric surface comprising a first principal meridian with a lower radius of curvature r and a second principal meridian with a higher radius of curvature R (r<R) and a periphery 2; depositing on the toric surface at least two drops 2a, 2b of the liquid curable composition, each within one of two opposite sectors S1, S2 centered on the first principal meridian of lower radius of curvature r and having an apex angle up to 40°; applying pressure on said pre-measured amount of liquid curable composition to cause said liquid curable composition to spread over the toric surface of the optical article; curing the liquid curable composition; and recovering an optical article coated with at least one coating layer.

Abstract: This invention is directed to improved lens molds for the production of ophthalmic lenses, in particular colored contact lenses. The invention involves protective coatings for extended use and repair of reusable glass or quartz molds as well as for improved mold release and print-on-mold properties. The invention is also directed to a method of making the improved lens molds and their use in the manufacture of ophthalmic lenses, in particular colored contact lenses.

Abstract: In a method for forming concrete structures a form having at least one elongate body has an L-shaped strip attached along the lower edge of the elongate body. The L-shaped strip has an inside corner radius. Concrete is then poured into the form and against the inside corner radius of the L-shaped strip. After the concrete has set, the form and L-shaped strip are removed from the concrete, which is partially cured, to provide a concrete body having a curved edge that corresponds to the L-shaped strip. Thereafter, the curved edge is finished with a hand tool to provide a smooth drip edge. Once the finishing is completed, the concrete is allowed to fully cure.

Abstract: Thermoforming a plastics material part, in particular a plate. According to the invention, the thermoforming unit comprises at least two molds (2, 3) of respective shapes that enable the shape of the material (1) being worked to be caused to vary progressively up to a final mold giving the desired shape. A thermoforming method using such a thermoforming unit.