Abstract: A display device includes a substrate having a transistor disposed thereon and including a source/drain electrode connected to the transistor, an intermediate layer disposed on the transistor, the source/drain electrode penetrating the intermediate layer, a light emitting structure disposed on the intermediate layer, the light emitting structure connected to an extension portion of the source/drain electrode by a first electrode, the extension portion extending across an upper surface of the intermediate layer, a first opening in the upper surface of the intermediate layer where the source/drain electrode penetrates the intermediate layer, and a contact area where the first electrode contacts the source/drain electrode, wherein the contact area has an area greater than that of the first opening, and the contact area does not overlap the first opening.

Abstract: Methods for cooling semiconductor devices having a light-emitting surface and associated devices are disclosed and described. Such a device may include a light-emitting surface and a diamond layer disposed on at least a portion of the light-emitting surface. The diamond layer may be exposed to air in order to accelerate movement of heat away from the light-emitting surface and into the air.

Abstract: A white LED module includes a circuit board, a blue LED chip disposed on the circuit board, a green light source of an LED chip or phosphor disposed on the circuit board, and a red light source of an LED chip or phosphor disposed on the circuit board. At least one of the green and red light sources is a phosphor, which is excited by the blue LED chip to radiate. The blue LED chip emits light in a triangular region defined by color coordinates (0.0123, 0.5346), (0.0676, 0.4633) and (0.17319, 0.0048), the green light source emits light in a triangular region defined by color coordinates (0.025, 0.5203), (0.4479, 0.541) and (0.0722, 0.7894), and the red light source emits light in a triangular region defined by color coordinates (0.556, 0.4408), (0.6253, 0.3741) and (0.7346, 0.2654).

Abstract: A nitride semiconductor light emitting element having a laminate S made of a semiconductor crystal layer, wherein the laminate S includes an n-type layer 2, a light emitting layer 3 and a p-type layer 4. The p-type layer 4 has a p-type contact layer 42 to be in contact with the p-side electrode P2. The p-type contact layer 42 comprises a first contact layer 42a and a second contact layer 42b. The first contact layer 42a is in contact with the p-side electrode P2 on one surface and in contact with the second contact layer 42b on the other surface. The first contact layer 42a is made of Alx1Iny1Gaz1N (0<x1?1, 0?y1?1, 0?z1?1), and the second contact layer 42b is made of Alx2Iny2Gaz2N (0?x2?1, 0?y2?1, 0?z2?1). 0?x2<x1, 0?y1?y2, and the first contact layer 42a has a thickness of 0.5 nm-2 nm.

Abstract: A GaN-based semiconductor light-emitting element capable of suppressing the occurrence of piezoelectric spontaneous polarization in the thickness direction of an active layer and reducing the driving voltage of a light-emitting diode is provided. The GaN-based semiconductor light-emitting element has a structure with a first GaN-based compound semiconductor layer 21 having the top face parallel to the a-plane and having a first conductivity type, an active layer 22 having the top face parallel to the a-plane, a second GaN-based compound semiconductor layer 23 having the top face parallel to the a-plane and having a second conductivity type, and a contact layer 24 composed of a GaN-based compound semiconductor and having the top face parallel to the a-plane, stacked in that order. The GaN-based semiconductor light-emitting element further includes a first electrode 25 disposed on the first GaN-based compound semiconductor layer 21 and a second electrode 26 disposed on the contact layer 24.

Abstract: An electrical and/or optical component and a process for manufacturing the component achieve especially good quality in the component and especially reliably avoid crystal dislocations in material layers of the component. In the process for producing a component, at least one trench is etched into a substrate, the trench is overgrown laterally by at least one semiconductor layer in such a way that the trench is completely covered by the semiconductor layer while forming a gas-filled, especially air-filled, cavity, and the component is integrated in the semiconductor layer or in a further semiconductor layer applied to the semiconductor layer, with an active region of the component being placed above the cavity.

Abstract: A semiconductor is provided with: a silicon substrate 2a of a first conductivity type, including a first surface S1a and a second surface S2a; a silicon layer 4a of a second conductivity type, arranged on the first surface S1a of the silicon substrate 2a, including a third surface S3a opposite a junction surface with the silicon substrate 2a; a first electrode 12a arranged on the second surface S2a; a second electrode 14a arranged on the third surface S3a; and an argon added area 6a formed in a semiconductor area formed of the silicon substrate 2a and the silicon layer 4a. The argon added area 6a includes an area indicating an argon concentration of a minimum of 1×1018 cm?3 and a maximum of 2×1020 cm?3.

Abstract: A light emitting diode (“LED”) device that emits omni-directional light is disclosed. Such omni-directional LED device may include a LED chip capable of emitting light in all directions. In one example of one implementation, the LED chip is then assembled and sealed inside a casing, such as a glass casing or tube that is capable of emitting light in 360 degree beam pattern. Further, the anode and cathode, or P or N-type contacts, may be configured on the LED chip such that light is allowed to emit from the top and/or the bottom surface of the LED chip in the LED device and is further able to reflect outward and fill the casing or tube of the LED device with light capable of emitting omni-directionally.

Abstract: A light emitting device and method of making the device uses an encapsulant to create a hollow region within a chamber of the device. The encapsulant is configured to contact at least a portion of a light source of the device and a portion of a lens of the device. The hollow region within the chamber provides space for the encapsulant to expand and contract.

Abstract: Overmolded lenses and certain fabrication techniques are described for LED structures. In one embodiment, thin YAG phosphor plates are formed and affixed over blue LEDs mounted on a submount wafer. A clear lens is then molded over each LED structure during a single molding process. The LEDs are then separated from the wafer. The molded lens may include red phosphor to generate a warmer white light. In another embodiment, the phosphor plates are first temporarily mounted on a backplate, and a lens containing a red phosphor is molded over the phosphor plates. The plates with overmolded lenses are removed from the backplate and affixed to the top of an energizing LED. A clear lens is then molded over each LED structure. The shape of the molded phosphor-loaded lenses may be designed to improve the color vs. angle uniformity. Multiple dies may be encapsulated by a single lens. In another embodiment, a prefabricated collimating lens is glued to the flat top of an overmolded lens.

Abstract: Disclosed is a light emitting diode (LED) package employing a lead terminal with a reflecting surface. The package includes first and second lead terminals that are spaced apart from each other. The first lead terminal has a lower portion with an LED chip mounting area, and at least one reflecting surface formed by being bent from the lower portion. Meanwhile, a package body supports the first and second lead terminals and forms a cavity through which the LED chip mounting area and the reflecting surface of the first lead terminal and a part of the second lead terminal are exposed. The first and second lead terminals extend outside of the package body. Accordingly, light emitted from an LED chip can be reflected on the reflecting surface with high reflectivity, so that the optical efficiency of the package can be improved.

Abstract: A semiconductor device may include, but is not limited to, a substrate, a compound semiconductor epitaxial layer, and a first reflecting layer. The substrate may have a main face. The substrate may have at least one cavity that is adjacent to the main face. The compound semiconductor epitaxial layer may have first and second faces adjacent to each other. The first face may contact with the main face. The second face may face toward the at least one cavity. The compound semiconductor epitaxial layer may include, but is not limited to, at least one light emitting layer that emits light. The first reflecting layer may be in the at least one cavity. The first reflecting layer may contact with the second face. The first reflecting layer may be higher in light-reflectivity than the substrate.

Abstract: Provided are a light emitting apparatus and a light unit. The light emitting apparatus comprises a first substrate, a second substrate, and a light emitting device. The first substrate has a plurality of lead frames, and the second substrate has an opening part on the first substrate. The light emitting device is mounted on a portion of the first substrate that is below the opening part. The light unit comprises at least one light emitting apparatus and an optical member on a light emitting path of the light emitting apparatus.

Abstract: A semiconductor light-emitting element assembly includes: a semiconductor light-emitting element having first and second leads, a semiconductor light-emitting element chip die-bonded to the first lead and wire-bonded to the second lead, a metal body for heat dissipation fixed to the first and second leads via an insulating adhesive layer, and a reflector fixed to the first and second leads and reflecting light from the chip; a wiring board having an opening for receiving the reflector; a heat dissipator disposed on the metal body for heat dissipation; and a fastening part for fastening the heat dissipator and the wiring board, wherein the first and second leads are fixed to the wiring board so that the reflector is received in the opening, and an interval holding part for holding an interval between the heat dissipator and the wiring board.

Abstract: An optical semiconductor device includes an insulating substrate provided with a first electrode and a second electrode each extending from the obverse surface onto the reverse surface of the substrate. The first electrode includes a die-bonding pad extending on the obverse surface of the substrate and a first terminal extending on the reverse surface of the substrate. The second electrode includes a wire-bonding pad extending on the obverse surface of the substrate and a second terminal extending on the reverse surface of the substrate. An LED chip is bonded to the die-bonding pad of the first electrode. The LED chip is also connected to the wire-bonding pad of the second electrode by a wire. The wire and the LED chip are enclosed by a resin package. The wire-bonding pad has a thickness of 10 ?m-30 ?m, and the second terminal has a thickness of 5 ?m-9 ?m.

Abstract: A method of manufacturing a vertical GaN-based LED comprises forming a light emission structure in which an n-type GaN-based semiconductor layer, an active layer, and a p-type GaN-based semiconductor layer are sequentially laminated on a substrate; etching the light emission structure such that the light emission structure is divided into units of LED; forming a p-electrode on each of the divided light emission structures; filling a non-conductive material between the divided light emission structures; forming a metal seed layer on the resulting structure; forming a first plated layer on the metal seed layer excluding a region between the light emission structures; forming a second plated layer on the metal seed layer between the first plated layers; separating the substrate from the light emission structures; removing the non-conductive material between the light emission structures exposed by separating the substrate; forming an n-electrode on the n-type GaN-based semiconductor layer; and removing portions

Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.

Abstract: An integrated circuit is made of a semiconductor material and comprises an input and/or output terminal connected to an output transistor forming a parasitic element capable of triggering itself under the effect of an electrostatic discharge applied to the terminal. The integrated circuit comprises a protection device formed so as to be biased at the same time as the parasitic element under the effect of an electrostatic discharge, and more than the parasitic element to evacuate a discharge current as a priority.

Abstract: An image sensor according to embodiments may include a first substrate having photodiode cells, a second substrate having a logic circuit, and connection electrodes that may electrically connect the photodiode cells with the logic circuit. In embodiments, more area may be available on the first substrate for photodiode cells and light loss may be reduced.

Abstract: In a MOS-type semiconductor device in which, on a Si substrate (201), a SiGe layer (202) having a valence band edge energy value smaller than a valence band edge energy value of the first semiconductor layer and a mobility larger than a mobility of the first semiconductor layer, a Si cap layer (203), and an insulating layer (204) are sequentially laminated, the problem of the shift of the absolute value of the threshold voltage toward a smaller value caused by negative fixed charges formed in or near the interface between the Si cap layer (203) and the insulting film (204) by diffusion of Ge is overcome by neutralizing the negative fixed charges by positive charges induced in and near the interface between the Si cap layer and the insulating film along with addition of nitrogen atoms to the semiconductor device surface by NO gas annealing and thereby shifting the threshold voltage toward a larger value.

Abstract: A one or two-dimensional capacitive micro-machined ultrasonic transducer (CMUT) array with supporting frame is provided. The CMUT array has at least three array elements deposited on a conductive substrate. The invention also has at least one CMUT cell in the array element, a conductive top layer deposited to a top side of the element, and a conductive via disposed within the elements. The via is isolated from the conductive top layer and conducts with the substrate. There are at least two isolation trenches in the conductive substrate, and the trenches are disposed between adjacent vias to conductively isolating the vias. A substrate region between the trenches forms a mechanical support frame. At least one conductive electrode is deposited to a bottom surface of the conductive substrate, where the electrode conducts with the via. The support frame eliminates the need for a carrier wafer in the process steps.

Abstract: An imaging device includes a first electrode for generating an electric field storing signal charges, a charge multiplication section for multiplying the stored signal charges, a second electrode for generating the electric field in the charge multiplication section, a voltage conversion portion for converting the signal charges into a voltage, a third electrode for transferring the signal charges to the voltage conversion portion, provided between the first electrode and the voltage conversion portion, wherein the second electrode is provided on a side opposite to the third electrode and the voltage conversion portion with respect to the first electrode.

Abstract: Phase change memory elements, devices and systems using the same and methods of forming the same are disclosed. A memory element includes first and second electrodes, and a phase change material layer between the first and second electrodes. The phase change material layer has a first portion with a width less than a width of a second portion of the phase change material layer. The first electrode, second electrode and phase change material layer may be oriented at least partially along a same horizontal plane.

Abstract: According to a junction FET of the present invention, the depth of a channel region is made shallow by selectively performing ion implantation and diffusion. Since the channel region forms a pn junction together with a p type semiconductor layer with relatively low impurity concentration, the improvement in the high frequency characteristic and the reduction in the amount of the leakage current because of the reduction in a junction capacitance can be achieved. Moreover, the depth of a gate region is also made shallow by ion implantation, and thus the reduction in noise because of the reduction in the internal resistance can be achieved.

Abstract: In various embodiments, circuits and semiconductor devices and structures and methods to manufacture these structures and devices are disclosed. In one embodiment, a bidirectional polarity, voltage transient protection device is disclosed. The voltage transient protection device may include a bipolar PNP transistor having a turn-on voltage of VBE1, a bipolar NPN transistor having a turn-on voltage of VBE2, and a field effect transistor (FET) having a threshold voltage of VTH, wherein a turn-on voltage VTO of the voltage transient protection device is approximately equal to the sum of VBE1, VBE2, and VTH, that is, VTO?VBE1+VBE2+VTH. Other embodiments are described and claimed.

Abstract: A method for forming a metal oxide semiconductor field-effect transistor (MOSFET) includes forming a III-V compound semiconductor on a substrate with the III-V compound semiconductor being doped with a first dopant type. The method further includes doping a first and second region of the III-V compound semiconductor with a second dopant type to form a drain and a source of the MOSFET. The method further includes forming a gate dielectric on the III-V compound semiconductor through atomic layer deposition. The method further includes applying a metal onto the dielectric to form a gate of the MOSFET. A MOSFET is also disclosed herein.

Abstract: A semiconductor device may include a gate pattern formed on a semiconductor substrate. At least one impurity region may be formed in the semiconductor substrate such that at least a portion of the at least one impurity region is disposed under the gate pattern. An epitaxial growth layer may be formed on the at least one impurity region. The epitaxial growth layer may include a first epitaxial growth portion spaced apart from the gate pattern and a second epitaxial growth portion extending toward the gate pattern from the first epitaxial growth portion.

Abstract: A lead frame structure for supporting a semiconductor die is disclosed that includes at least two electrical leads each having a plurality of finger shaped structures unilaterally extending outward from the at least two electrical leads. The electrical leads are arranged so that the plurality of finger shaped structures forms inter-digital patterns where the semiconductor dies are bonded to the lead frame structure.

Abstract: A semiconductor device including a substrate-driven field-effect transistor with a lateral channel and a parallel-coupled Schottky diode, and a method of forming the same. In one embodiment, the substrate-driven field-effect transistor of the semiconductor device includes a conductive substrate having a first contact covering a substantial portion of a bottom surface thereof, and a lateral channel above the conductive substrate. The substrate-driven field-effect transistor also includes a second contact above the lateral channel and an interconnect that connects the lateral channel to the conductive substrate operable to provide a low resistance coupling between the first contact and the lateral channel. The semiconductor device also includes a Schottky diode parallel-coupled to the substrate-driven field-effect transistor. A first and second terminal of the Schottky diode are couplable to the first and second contacts, respectively, of the substrate drive field-effect transistor.

Abstract: A CMOS image sensor and a fabricating method thereof are provided. The method includes forming a nitride layer over a boundary region between a device isolation region and a pixel region, forming a silicide barrier layer in the pixel region and performing a silicide process. A boundary portion of the silicide barrier layer formed in the pixel region can be prevented from being wet-etched while the silicide barrier layer is removed by the wet etching process.

Abstract: Embodiments relate to an image sensor and a method for manufacturing an image sensor. According to embodiments, ions of low concentration may be implanted into a photodiode region of a semiconductor substrate to form a photodiode. At least one gate insulating layer pattern may be formed on the semiconductor substrate, and a gate electrode may be formed on each of the at least one gate insulating layer pattern to receive charges from the photodiode. Spacers may be formed at sidewalls of the gate electrode, respectively. A selective epitaxial growth layer may be formed on the photodiode, and ions of low concentration may be obliquely implanted into one side and the other side of the gate electrode to form a low concentration source and a low concentration drain extending below the spacer. Subsequently, a high concentration source and a high concentration drain may be formed on both sides of the gate electrode, respectively.

Abstract: Embodiments relate to a horizontal type bipolar junction transistor element (BJT) and a CMOS image sensor having the same to form a photodiode. In embodiments, the bipolar junction transistor as well as collector current may flow uniformly in a horizontal direction, which may increase the entire amount of current. In embodiments, large current gain may be obtained.

Abstract: A CMOS image sensor and a fabricating method thereof improves sensitivity to blue light by forming a depletion layer by means of a PN junction in a gate of a drive transistor. The depletion layer formed on the upper portion of the gate improves the sensitivity of the CMOS image sensor to blue light.

Abstract: A CMOS image sensor includes at least one of: A P-type semiconductor substrate. A P-type photodiode formed in the P-type semiconductor substrate and having a higher impurity concentration than the semiconductor substrate. An N-type photodiode disposed over the P-type photodiode at a depth less than approximately 0.15 ?m from the surface of the semiconductor substrate. A depletion layer provided by junction of the P-type photodiode and the N-type photodiode.

Abstract: Apparatus and methods of forming the apparatus include a dielectric layer containing barium strontium titanium oxide layer, an erbium-doped barium strontium titanium oxide layer, or a combination thereof. Embodiments of methods of fabricating such dielectric layers provide dielectric layers for use in a variety of devices. Embodiments include forming barium strontium titanium oxide film using atomic layer deposition. Embodiments include forming erbium-doped barium strontium titanium oxide film using atomic layer deposition.

Abstract: Provided are FeRAM device constructions and fabrication methods that provide for the direct connection of metal patterns to ferroelectric capacitors. The FeRAM device constructions utilize a combination of one or more barrier layers incorporated in conductive plugs, barrier layers incorporated in primary conductive patterns or conductive patterns formed using one or more noble metals to suppress parametric drift associated with conventional FeRAM constructions.

Abstract: Provided are a dielectric film, a method of manufacturing the same, and a semiconductor capacitor having the dielectric film. The semiconductor capacitor includes a lower electrode, a ferroelectric layer disposed on the lower electrode, a paraelectric layer disposed on the ferroelectric layer, and an upper electrode disposed on the paraelectric layer.

Abstract: In a conventional semiconductor device, an excessive etching occurs in a section where an opening for contact plug is formed, causing a damage to a diffusion layer located under the opening. A semiconductor device 1 includes a region D1 for forming an electric circuit, and a seal ring 30 (guard ring) that surrounds the region D1 for forming the electric circuit. A DRAM 40 is formed in the region D1 for forming the electric circuit. Interlayer insulating films 22, 24, 26 and 28 are formed on a semiconductor substrate 10. The seal ring 30 is formed in the interlayer insulating films 22, 24, 26 and 28, and at least a portion there of is located spaced apart from the semiconductor substrate 10.

Abstract: A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between the semiconductor substrate and the metal filling. The semiconductor substrate has a doped region in the contact hole.

Abstract: A semiconductor device including a semiconductor substrate and a recessed transistor provided on the semiconductor substrate, wherein the recessed transistor includes a recess formed in a surface of the semiconductor substrate, an insulating film provided on a surface in the recess, a gate electrode at least partly buried in the recess, and a first diffusion layer and a second diffusion layer formed in a surface of the semiconductor substrate with the gate electrode located between the first diffusion layer and the second diffusion layer, and wherein the insulating film includes a thicker film portion between the first diffusion layer and the gate electrode, the thicker film portion being thicker than a portion of the insulating film located between the gate electrode and a channel region of the recessed transistor.

Abstract: A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.

Abstract: A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched into the first, second pad layers, and the semiconductor substrate. The second pad layer and a portion of the STI structure between the two trenches are etched to form a ridge. A liner is formed on interior surface of the trenches. A first polysilicon layer is formed on the liner. A capacitor dielectric layer is formed on the first polysilicon layer. The two adjacent trenches are filled with a second polysilicon layer. The second polysilicon layer is then etched until the capacitor dielectric layer is exposed. The fabrication process is easy to integrate to SoC chip.

Abstract: A method is provided for producing a fin structure on a semiconductor substrate using a thin SiGe layer to produce a void between a silicon substrate and a silicon fin portion. A fin structure produced by such a method is also provided.

Abstract: A semiconductor memory device has a first interlayer insulating film formed on a semiconductor substrate and having a capacitor opening portion provided in the film, and a capacitance element formed over the bottom and sides of the capacitor opening portion and composed of a lower electrode, a capacitance insulating film, and an upper electrode. A bit-line contact plug is formed through the first interlayer insulating film. At least parts of respective upper edges of the lower electrode, the capacitance insulating film, and he upper electrode at a side facing the bit-line contact plug are located below the surface of the first interlayer insulating film, the lower electrode, the capacitance insulating film, and the upper electrode being located over the sides of the capacitor opening portion. The upper electrode is formed over only the bottom and sides of the capacitor opening portion.

Abstract: A capacitor structure comprises a substrate having a contact plug, a conductive cylinder positioned on the substrate and an electroplating structure covering the conductive cylinder, wherein a bottom electrode of the capacitor structure comprises the conductive cylinder and the electroplating structure. The conductive cylinder can be a hollow conductive cylinder, and the electroplating structure comprises a first conductive layer covering the inner sidewall and bottom surface of the hollow conductive cylinder and a second conductive layer covering the first conductive layer and the outer sidewall of the hollow conductive cylinder. The conductive cylinder and the electroplating structure can be made of different conductive material, and the free end of the conductive cylinder is preferably round. The conductive cylinder can be made of titanium nitride or tantalum nitride, while the electroplating structure can be made of ruthenium or platinum.

Abstract: Provided is a parallel-varactor capacitor. The capacitor comprises a first varactor and a second varactor. The first varactor has a first capacitance which varies depending on voltages applied to a first anode and a first cathode. The second varactor has a second capacitance which varies depending on voltages applied to a second anode and a second cathode. The first anode is connected to the second cathode and the first cathode is connected to the second anode.

Abstract: A nonvolatile semiconductor memory device includes: a source-line-side diode an anode region that is connected to a source line; a bit-line-side diode a cathode region that is connected to a bit line; and memory cell string connected between a cathode region of the source-line-side diode and an anode region of the bit-line-side diode. The memory cell string includes a series connection of a plurality of memory cell transistors. The source-line-side diode is formed in a contact for connecting the source line and the memory cell string in a first direction perpendicular to a semiconductor substrate. The bit-line-side diode is formed in a contact for connecting the bit line and the memory cell string in the first direction.

Abstract: There are provided a nonvolatile semiconductor memory of a structure in which electric signals from peripheral circuits are reliably transferred to control gates via word lines even if contact holes cannot be opened accurately above the word lines, and a method of fabricating the nonvolatile semiconductor memory. Plural word lines and plural bit lines are disposed on a semiconductor substrate, and there are memory cells at intersecting portions of the word lines and the bit lines. At contact portions of the word lines and metal wires of an upper layer, polysilicon regions, which include the contact portions, are formed beneath a polysilicon forming the word lines, as an etching stop layer at a time of forming contacts.

Abstract: A semiconductor memory device may have a DRAM cell mode and a non-volatile memory cell mode without a capacitor, including multiple transistors arranged in an array and having floating bodies, word lines connected to gate electrodes of the transistors, bit lines at a first side of the gate electrodes connected to drains of the transistors, source lines at a second side of the gate electrodes, different from the first side, and connected to sources of the transistors on the semiconductor substrate, and charge storage regions between the gate electrodes and the floating bodies.

Abstract: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.