Patents Issued in April 29, 2008
  • Patent number: 7364925
    Abstract: A method of forming a protective barrier in an organic light emitting device is disclosed, wherein the organic light emitting device is formed on a substrate and includes a plurality of layers of materials, the plurality of layers of materials including an organic light emitting layer. The method includes forming an inorganic layer and a semi-crystalline parylene-based polymer layer over an underlying layer, wherein the semi-crystalline parylene-based polymer layer is formed via transport polymerization of a reactive intermediate species. Organic light emitting devices having barriers are also disclosed.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: April 29, 2008
    Assignee: International Display Systems, Inc.
    Inventors: Chung J. Lee, Chieh Chen, Atul Kumar
  • Patent number: 7364926
    Abstract: A method for manufacturing GaN LED devices is disclosed herein. First, a LED epitaxial layer is formed on a provisional substrate. Part of the LED epitaxial layer is removed to form a plurality of LED epitaxial areas. Then, a first transparent conductive layer, a metal reflective layer, and a first metal bonding layer are sequentially formed on the plurality of LED epitaxial areas and then part of the first transparent conductive layer, the metal reflective layer, and the first metal bonding layer are removed. Next, a permanent substrate is provided. At least a metal layer and a second metal bonding layer are formed on the permanent substrate. Then, part of at least the metal layer and the second metal bonding layer are removed. Next, the provisional substrate is bonded to the permanent substrate by aligned wafer bonding method. Then, the provisional substrate is removed to expose a surface of the LED epitaxial layer and then an n-type electrode is formed on the surface.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: April 29, 2008
    Assignee: Uni Light Technology Inc.
    Inventors: Li-Shei Yeh, Bor-Jen Wu, Chien-An Chen, Hsiao-Ping Chiu
  • Patent number: 7364928
    Abstract: In a circuit to drive driven elements such, as electro-optical elements, an electro-optical device has an element layer, a wire-forming layer, and an electronic component layer in order to suppress variation in characteristics of active elements. The element layer has a plurality of organic EL elements, each of which is arranged in a different position in a plane. The electronic component layer has pixel-driving IC chips. The respective pixel-driving IC chips include a plurality of pixel circuits, each of which drives each organic EL element corresponding to the pixel circuit. The wire-forming layer is positioned between the element layer and the electronic component layer. The wire-forming layer has wires to connect the respective pixel circuits included in the pixel-driving IC chips with the organic EL elements corresponding to the pixel circuits.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: April 29, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Yoichi Imamura
  • Patent number: 7364929
    Abstract: An object of the present invention is to provide a nitride semiconductor based light-emitting device, which is low in operating voltage reduction and is high in performance, and a manufacturing method thereof. A first metal film is formed on a P-type conductive nitride semiconductor formed on a substrate, and then, a film (WOx) made of tungsten oxide is formed in superimposition, followed by annealing.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: April 29, 2008
    Assignee: Opnext Japan, Inc.
    Inventors: Akihisa Terano, Shigehisa Tanaka
  • Patent number: 7364930
    Abstract: What is proposed here is a method of structuring surfaces of glass-type materials and variants of this method, comprising the following steps of operation: providing a semiconductor substrate, structuring, with the formation of recesses, of at least one surface of the semiconductor substrate, providing a substrate of glass-type material, joining the semiconductor substrate to the glass-type substrate, with a structured surface of the semiconductor substrate being joined to a surface of the glass-type surface in an at least partly overlapping relationship, and heating the substrates so bonded by annealing in a way so as to induce an inflow of the glass-type material into the recesses of the structured surface of the semiconductor substrate. The variants of the method are particularly well suitable for the manufacture of micro-optical lenses and micro-mechanical components such as micro-relays or micro-valves.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: April 29, 2008
    Assignee: Fraunhofer-Gesellschaft zur Forderung der angewandten Forschung e.V.
    Inventors: Hans-Joachim Quenzer, Peter Merz, Arne Veit Schulz
  • Patent number: 7364931
    Abstract: Capacitance sensor electrodes are arranged in a form of matrix on a semiconductor substrate and coated with a cover film. These capacitance sensor electrodes are connected to a drive circuit. ESD electrodes are arranged in the vicinities of corner portions of the capacitance sensor electrodes. Each ESD electrode is composed of a film containing, for example, aluminum excellent in conductivity and a TiN film formed thereon. The ESD electrodes are grounded through the semiconductor substrate. On each ESD electrode, a plurality of fine ESD holes reaching the ESD electrode from a surface of the cover film are formed.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: April 29, 2008
    Assignee: Fujitsu Limited
    Inventor: Masaki Ito
  • Patent number: 7364932
    Abstract: In the present invention, an etching hole 21 is formed in a polysilicon film 14 as a cavity-wall member. Through the etching hole 21, hydrofluoric acid is injected, so as to dissolve a silicon oxide film 13, thereby forming a cavity 22. In the cavity 22, a detecting unit 12 of a sensor is in an exposed condition. Next, by sputtering, an Al film 16 is deposited in the etching hole 21 and on an upper face of a substrate. Thereafter, a portion of the Al film 16 positioned on the polysilicon film 14 is removed by etching back, thereby leaving only a metal closure 16a of Al which closes the etching hole. The sputtering step is performed under a pressure of 5 Pa or less, so that the pressure in the cavity can be held to be low.
    Type: Grant
    Filed: December 25, 2003
    Date of Patent: April 29, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kimiya Ikushima, Hiroyoshi Komobuchi, Asako Baba, Mikiya Uchida
  • Patent number: 7364933
    Abstract: A method for forming an image sensor is provided. The method includes providing a semiconductor substrate having a pixel region and a peripheral circuit region, forming a photoelectric transformation section at the semiconductor substrate of the pixel region, forming a plurality of interlayer dielectrics over the semiconductor substrate with interconnections interposed therebetween, forming a passivation layer, partially patterning the passivation layer at the peripheral circuit region to form a via hole exposing the interconnection and removing the passivation layer and the underlying interlayer dielectric at the pixel region. The method further includes forming a conductive layer to fill the via hole and etching the conductive layer to remove the conductive layer at the pixel region and form a via plug and a conductive pad at the peripheral circuit region. The via plug fills the via hole and the conductive pad protrudes outwardly from the via hole.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: April 29, 2008
    Assignee: Samsung Electronics, Co., Ltd.
    Inventor: Ki-Hong Kim
  • Patent number: 7364934
    Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method for manufacturing a plurality of microelectronic imaging units includes placing a plurality of singulated imaging dies on a support member. The individual imaging dies include a first height, an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member and forming a base on the support member between adjacent imaging dies. The base has a second height less than or approximately equal to the first height of the dies. The method further includes attaching a plurality of covers to the base so that the covers are positioned over corresponding image sensors.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: April 29, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Bret K. Street, Frank L. Hall, James M. Derderian
  • Patent number: 7364935
    Abstract: A method of fabricating a phase-change memory cell is described. The cross-sectional area of a contact with a phase-change memory element within the cell is controlled by a first dimension of a bottom electrode and a second dimension controlled by an etch process. The contact area is a product of the first dimension and the second dimension. The method allows the formation of very small phase-change memory cells.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: April 29, 2008
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 7364936
    Abstract: A CMOS image sensor and a method for fabricating the same improve photosensitivity by imparting a color filter layer with the function of a microlens layer. The CMOS image sensor includes a semiconductor substrate; a plurality of photo-sensing elements formed in the semiconductor substrate; and a color filter layer comprised of a plurality of color filters for filtering light according to wavelength, wherein the plurality of color filters correspond to the plurality of photo-sensing elements and each color filter has a predetermined curvature for focusing light and for transmitting the focused light according to a corresponding wavelength.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: April 29, 2008
    Assignee: Dongbu Electronics Co., Ltd
    Inventor: Chang Young Hong
  • Patent number: 7364937
    Abstract: A vertical elevated pore structure for a phase change memory may include a pore with a lower electrode beneath the pore contacting the phase change material in the pore. The lower electrode may be made up of a higher resistivity lower electrode and a lower resistivity lower electrode underneath the higher resistivity lower electrode. As a result, more uniform heating of the phase change material may be achieved in some embodiments and better contact may be made in some cases.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: April 29, 2008
    Assignee: Ovonyx, Inc.
    Inventor: Tyler Lowrey
  • Patent number: 7364938
    Abstract: This invention relates to a process for making a semiconductor device comprising the following steps: a doped region with a first type of conductivity is made on a first principal face of a semiconductor substrate and at least one window is made, a first metallisation area is deposited on the doped region, a dielectric layer is deposited on at least the window and the first metallisation area, at least a first opening is etched in the dielectric layer at the window to accommodate a doped region with a second type of conductivity while arranging an undoped portion of the semiconductor substrate laterally between the doped regions, the substrate is doped to create the doped region with the second type of conductivity, a second metallisation area is deposited. Application particularly for solar cells in thin layer.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: April 29, 2008
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Pierre-Jean Ribeyron, Marc Pirot
  • Patent number: 7364939
    Abstract: In order to provide an active matrix display device in which a thick insulating film is preferably formed around an organic semiconductive film of a thin film luminescent device without damaging the thin film luminescent device, the active matrix display device is provided with a bank layer (bank) along a data line (sig) and a scanning line (gate) to suppress formation of parasitic capacitance in the data line (sig), in which the bank layer (bank) surrounds a region that forms the organic semiconductive film of the thin film luminescent device by an ink-jet process. The bank layer (bank) includes a lower insulating layer formed of a thick organic material and an upper insulating layer of an organic material which is deposited on the lower insulating layer and has a smaller thickness so as to avoid contact of the organic semiconductive film with the upper insulating layer.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: April 29, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Ichio Yudasaka
  • Patent number: 7364940
    Abstract: An organic thin film transistor including a fluorine-based polymer thin film and method of fabricating the same. The organic thin film transistor may include a gate electrode, a gate insulating layer, an organic semiconductor layer, source electrode, and a drain electrode formed on a substrate wherein a fluorine-based polymer thin film may be formed (or deposited) at the interface between the gate insulating layer and the organic semiconductor layer. The organic thin film transistor may have higher charge carrier mobility and/or higher on/off current ratio (Ion/Ioff). In addition, a polymer organic semiconductor may be used to form the insulating layer and the organic semiconductor layer by wet processes, so the organic thin film transistor may be fabricated by simplified procedure(s) at reduced costs.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: April 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo Young Kim, Eun Kyung Lee, Bang Lin Lee, Bon Won Koo, Hyun Jung Park, Sang Yoon Lee
  • Patent number: 7364941
    Abstract: A circuit device manufacturing method is provided, wherein the adhesion of an overcoat resin, formed on a conductive wiring layer, to a sealing resin layer is improved by irradiating plasma onto the overcoat resin. A first conductive film 23A and a second conductive film 23B, which are laminated with an interlayer insulating layer 22 interposed in between, are formed. By selectively removing the first conductive film, a first conductive wiring layer 12A is formed and the first conductive wiring layer is covered with an overcoat resin 18. Overcoat resin 18 is irradiated with plasma to roughen its top surface. A sealing resin layer 17 is formed so as to cover the top surface of the roughened overcoat resin 18 and circuit elements 13.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: April 29, 2008
    Assignees: Sanyo Electric Co., Ltd., Kanto SANYO Semiconductors Co., Ltd.
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Noriaki Sakamoto
  • Patent number: 7364942
    Abstract: This invention discloses a process for forming durable anti-stiction surfaces on micromachined structures while they are still in wafer form (i.e., before they are separated into discrete devices for assembly into packages). This process involves the vapor deposition of a material to create a low stiction surface. It also discloses chemicals which are effective in imparting an anti-stiction property to the chip. These include polyphenylsiloxanes, silanol terminated phenylsiloxanes and similar materials.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: April 29, 2008
    Assignee: Analog Devices, Inc.
    Inventor: John R. Martin
  • Patent number: 7364943
    Abstract: A method and an arrangement to bond a die to a substrate of a die-substrate combination to form a microelectronic package. The method comprises: providing the die-substrate combination including a die, a substrate, pre-connection bumps and an underfill material, the pre-connection bumps and underfill material being disposed between the die and the substrate; forming joints from the pre-connection bumps at a joint formation site to obtain an intermediate package; curing the underfill material of the intermediate package at an underfill curing site to obtain the microelectronic package; using a conveying device to transfer the intermediate package from the joint formation site to the underfill curing site; and applying heat energy to the intermediate package during at least part of a transfer thereof from the joint formation site to the underfill curing site to control a temperature of the intermediate package.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: April 29, 2008
    Assignee: Intel Corporation
    Inventors: James P. Mellody, Sabina J. Houle
  • Patent number: 7364944
    Abstract: A thermally enhanced semiconductor package and a fabrication method thereof are provided. A plurality of conductive bumps are formed on bond pads on an active surface of a chip. A heat sink is attached to an inactive surface of the chip and has a surface area larger than that of the chip. An encapsulation body encapsulates the heat sink, chip and conductive bumps, while exposing a bottom or surfaces, not for attaching the chip, of the heat sink and ends of the conductive bumps outside. A plurality of conductive traces are formed on the encapsulation body and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with a plurality of openings for exposing predetermined portions of the conductive traces. A solder ball is implanted on each exposed portion of the conductive traces.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: April 29, 2008
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Ping Huang, Cheng-Hsu Hsiao
  • Patent number: 7364945
    Abstract: An encapsulant cavity integrated circuit package system including forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: April 29, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Il Kwon Shim, Byung Joon Han, Kambhampati Ramakrishna, Seng Guan Chow
  • Patent number: 7364946
    Abstract: A method is provided for making a semiconductor multi-package module, by providing a lower molded ball grid array package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: April 29, 2008
    Assignee: Chippac, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 7364947
    Abstract: In an electronic component comprising a semiconductor chip packaged in a molded part from which the lead terminals of the semiconductor chip project, a main cutting notch is formed on the obverse surface of each lead terminal before molding the molded part while leaving unnotched portions adjoining both ends of the main notch. Then, each lead terminal is cut at the main notch after molding the molded part, thereby making fewer and smaller cutting burrs occurring at the cut faces.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: April 29, 2008
    Assignee: Rohm Co., Ltd.
    Inventor: Masahiko Kobayakawa
  • Patent number: 7364948
    Abstract: A semiconductor package and a fabrication method thereof are proposed. A lead frame is provided between a chip and a substrate in a window ball grid array semiconductor package, wherein an active surface of the chip is electrically connected to the lead frame via bonding wires formed in an opening of the substrate and is electrically connected to the substrate via the lead frame. The provision of lead frame can improve the heat dissipating efficiency and electrical performances. The bonding wires located in the opening of the substrate eliminate the prior-art drawback of requiring different molds in response to different opening structures of a substrate.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: April 29, 2008
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Jeng-Yuan Lai, Chun-Lung Chen
  • Patent number: 7364949
    Abstract: A semiconductor package that includes two circuit boards and at least one semiconductor device which is disposed between the two circuit boards and connected to external connectors disposed on at least one of the circuit boards.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: April 29, 2008
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 7364950
    Abstract: A semiconductor device is provided including a semiconductor element having a plurality of electrodes, a plurality of bonding portions of a lead frame, a plate-like current path material which electrically connects at least one of the plurality of electrodes and one of the plurality of bonding portions, a housing which packages the semiconductor element having the plurality of electrodes, the plurality of bonding portions of the lead frame, and the current path material, wherein the plate-like current path material is arranged to be directly bonded to one of the plurality of electrodes and one of the plurality of bonding portions, and the middle portion of the current path material is formed apart from the surface of the semiconductor element. A method of manufacturing the same is also provided.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: April 29, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Norihide Funato, Masataka Nanba, Hiroshi Sawano
  • Patent number: 7364951
    Abstract: A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: April 29, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Goda, Riichiro Shirota, Kazuhiro Shimizu, Hiroaki Hazama, Hirohisa Iizuka, Seiichi Aritome, Wakako Moriyama
  • Patent number: 7364952
    Abstract: The present disclosure is directed to methods and systems for processing a thin film samples. In an exemplary method, semiconductor thin films are loaded onto two different loading fixtures, laser beam pulses generated by a laser source system are split into first laser beam pulses and second laser beam pulses, the thin film loaded on one loading fixture is irradiated with the first laser beam pulses to induce crystallization while the thin film loaded on the other loading fixture is irradiated with the second laser beam pulses. In a preferred embodiment, at least a portion of the thin film that is loaded on the first loading fixture is irradiated while at least a portion of the thin film that is loaded on the second loading fixture is also being irradiated. In an exemplary embodiment, the laser source system includes first and second laser sources and an integrator that combines the laser beam pulses generated by the first and second laser sources to form combined laser beam pulses.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: April 29, 2008
    Assignee: The Trustees of Columbia University in the City of New York
    Inventor: James Im
  • Patent number: 7364953
    Abstract: A method for treating exposed metal in a semiconductor wafer (301) in wafer processing is disclosed herein. In accordance with the method, a wafer is provided which is equipped with a metal layer (307) and a substrate (303), wherein a portion of the metal layer is exposed at the edge of the wafer. The exposed portion of the metal layer is then covered with a dielectric material (317).
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: April 29, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Thuy Dao
  • Patent number: 7364954
    Abstract: The present invention provides a manufacturing method of a semiconductor device at low cost and with high reliability.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: April 29, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazutaka Kuwashima, Tamae Takano, Shunpei Yamazaki
  • Patent number: 7364955
    Abstract: Methods of manufacturing semiconductor devices having at least one single crystal silicon layer are provided. Pursuant to these methods, a first seed layer that includes silicon is formed. A first non-single crystalline silicon layer is then formed on the first seed layer. The first non-single crystalline silicon layer is irradiated with a laser to transform the first non-single crystalline silicon layer into a first single crystalline silicon layer. Corresponding semiconductor devices are also disclosed.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: April 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Yu-Gyun Shin
  • Patent number: 7364956
    Abstract: A method for manufacturing semiconductor devices includes a step of etching a sample including an interlayer insulating layer containing Al2O3 and a polysilicon or SiO2 layer in contact with the interlayer insulating layer using a plasma etching system. The interlayer insulating layer is etched with a gas mixture containing BCl3, Ar, and CH4 or He. The gas mixture further contains Cl2. The interlayer insulating layer is etched in such a manner that a time-modulated high-frequency bias voltage is applied to the sample. The interlayer insulating layer is etched in such a manner that the sample is maintained at a temperature of 100° C. to 200° C. The interlayer insulating layer and the polysilicon or SiO2 layer are separately etched in different chambers.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: April 29, 2008
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Go Saito, Toshiaki Nishida, Takahiro Shimomura, Takao Arase
  • Patent number: 7364957
    Abstract: A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: April 29, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kong-Beng Thei, Chung Long Cheng, Harry Chuang
  • Patent number: 7364958
    Abstract: A method in which semiconductor-to-semiconductor direct wafer bonding is employed to provide a hybrid substrate having semiconductor layers of different crystallographic orientations that are separated by a conductive interface is provided. Also provided are the hybrid substrate produced by the method as well as using the direct bonding method to provide an integrated semiconductor structure in which various CMOS devices are built upon a surface orientation that enhances device performance.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: April 29, 2008
    Assignee: International Business Machines Corporation
    Inventors: Meikei Ieong, Alexander Reznicek, Min Yang
  • Patent number: 7364959
    Abstract: A method for manufacturing a MOS transistor integrated into a chip of semi-conductive material comprising a first and a second active region which extend from the inside of the chip to a surface of the chip. The method comprises the steps of: a) forming a layer of insulating material on the surface of the chip and depositing a layer of conductive material on said insulating layer, b) defining an insulated gate electrode of the transistor, from said superimposed insulating and conductive layers, c) defining, from said superimposed insulating and conductive layers, an additional structure arranged on a first surface portion of the first active region, and d) placing between the insulated gate electrode and the additional structure a dielectric spacer placed on a second surface portion of the first active region.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: April 29, 2008
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alessandro Moscatelli, Giuseppe Croce
  • Patent number: 7364960
    Abstract: Methods for fabricating CMOS image sensor devices are provided, wherein active pixel sensors are constructed with non-planar transistors having vertical gate electrodes and channels, which minimize the effects of image lag and dark current.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: April 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jeong Ho Lyu
  • Patent number: 7364961
    Abstract: A new method to form a SRAM memory cell in an integrated circuit device is achieved. The method comprises providing a bi-stable flip-flop cell having a data storage node and a data bar storage node. A first capacitor is formed coupled to the data bar storage node, and a second capacitor is formed coupled to the data storage node. The first and second capacitors comprise a first conductor layer overlying a second conductor layer with a dielectric layer therebetween. One of the first and second conductor layers is coupled to ground. A new SRAM device is disclosed.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: April 29, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 7364962
    Abstract: A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: April 29, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Srinath Krishnan
  • Patent number: 7364963
    Abstract: A method for fabricating a semiconductor device is provided. The method includes: implanting impurities onto a substrate by performing an ion implantation process; recessing portions of the substrate to form a plurality of trenches; performing a first thermal process to form junction regions between the trenches in the substrate by diffusing the impurities and simultaneously to form a gate oxide layer on the substrate and on the junction regions; forming a polysilicon layer on the gate oxide layer; sequentially etching the polysilicon layer and the gate oxide layer to form a gate structure, and to form first spacers on lateral walls of the junction regions; forming second spacers on lateral walls of the first spacers and the gate structure; and forming a metal silicide layer on top portions of the junction regions and the gate structure.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: April 29, 2008
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Yong-Sik Jeong
  • Patent number: 7364964
    Abstract: A highly reliable semiconductor device having a ferroelectric capacitor structure by sufficiently preventing the H2 attack without damaging the function of an interlayer insulating film covering interconnections and the like to obtain a high capacitor performance. The position of a semiconductor substrate mounted on and secured to a substrate support plate in an HDP-CVD system is adjusted in the vertical direction, whereby a second HDP-CVD oxide film is deposited so that voids are formed between aluminum interconnections at lower positions than the height of the aluminum interconnections.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: April 29, 2008
    Assignee: Fujitsu Limited
    Inventor: Kazutoshi Izumi
  • Patent number: 7364965
    Abstract: A semiconductor device having a DRAM has a capacitor in which a dielectric film and an upper electrode are laminated on a lower electrode comprising a polysilicone, in which a natural oxide film oxidized by oxygen in the atmosphere grows to at least 1.5 nm on the surface of a lower electrode of the capacitor. Further, in forming the dielectric film, the dioxide film further grows in the case of using an oxidative raw material. This brings forth a reduction in capacitance, and an increase of a leakage current is caused. Therefore, after a dielectric film having a reduction property has been formed, the reduction property is promoted by a heat treatment to thereby reduce a dioxide film and realize making the dioxide film on the lower electrode surface thinner.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: April 29, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Osamu Tonomura, Hiroshi Miki, Yuichi Matsui, Tomoko Sekiguchi, Kikuo Watanabe
  • Patent number: 7364966
    Abstract: A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then formed in the one or more openings in the dielectric layer, and is then planarized to form one or more individual contact plugs. Next, the buried bit line layer is etched to recess the buried bit line layer, and a capacitor plate is formed to contact the contact plug.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: April 29, 2008
    Assignee: Micron Technology, Inc.
    Inventors: James E. Green, Terrence B. McDaniel
  • Patent number: 7364967
    Abstract: Methods of forming a storage capacitor include forming an interlayer insulation layer having an opening therethrough on a semiconductor substrate, forming a contact plug in the opening, forming a molding oxide layer on the interlayer insulation layer and the contact plug, selectively removing portions of the molding oxide layer to form a recess above the contact plug, forming a titanium layer on a bottom surface and side surfaces of the recess, forming a titanium nitride layer on the titanium layer, and forming a titanium oxide nitride layer on the titanium nitride layer. A storage capacitor includes a semiconductor substrate, an interlayer insulation layer having a contact plug therein on the substrate, and a storage electrode on the contact plug including a titanium silicide layer, a titanium nitride layer on the titanium silicide layer, and a titanium oxide nitride layer on the titanium nitride layer.
    Type: Grant
    Filed: November 3, 2005
    Date of Patent: April 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Rak-Hwan Kim, Young-Joo Cho, Sung-Tae Kim, In-Sun Park, Hyeon-Deok Lee, Hyun-Suk Lee, Jung-Hee Chung, Hyun-Young Kim, Hyun-Seok Lim
  • Patent number: 7364968
    Abstract: The capacitor in a semiconductor device includes a substrate, a lower electrode formed over the substrate, a diffusion barrier formed over the lower electrode, a plurality of agglomerates formed over the diffusion barrier, a dielectric layer formed over the surface of the agglomerates to form an uneven surface, and an upper electrode formed over the dielectric layer.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: April 29, 2008
    Assignee: Dongbu Hitek Co. Ltd.
    Inventor: Jae Suk Lee
  • Patent number: 7364969
    Abstract: A semiconductor fabrication process includes forming polysilicon nanocrystals on a tunnel oxide overlying a first region of a substrate. A second dielectric is deposited overlying the first region and a second region. Without providing any protective layer overlying the second dielectric in the first region, an additional thermal oxidation step is performed without oxidizing the nanocrystals. A gate electrode film is then deposited over the second dielectric and patterned to form first and second gate electrodes. The second dielectric may be an annealed, CVD oxide. The additional thermal oxidation may include forming by dry oxidation a third dielectric overlying a third region of the semiconductor substrate. The dry oxidation produces a interfacial silicon oxide underlying the second dielectric in the second region. An upper surface of a fourth region of the substrate may then be exposed and a fourth dielectric formed on the upper surface in the fourth region.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: April 29, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Erwin J. Prinz, Ramachandran Muralidhar
  • Patent number: 7364970
    Abstract: A multi-bit non volatile memory cell includes a first floating gate sidewall spacer structure and a second floating gate sidewall spacer structure physically separated from the first floating gate sidewall spacer structure. Each floating gate sidewall spacer structure stores charge for logically storing a bit. The floating gate sidewall spacer structures are formed adjacent to a patterned structure by sidewall spacer formation processes from a layer of floating gate material (e.g. polysilicon). A control gate is formed over the floating gate sidewall spacer structures by forming a layer of control gate material and then patterning the layer of control gate material.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: April 29, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Marius K. Orlowski, Sinan Goktepeli
  • Patent number: 7364971
    Abstract: A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is adjacent to the first part. The trench gate electrode penetrates the body region and reaches the drift region so that the trench gate electrode faces the body region and the drift region through an insulation layer. The trench gate electrode extends in a direction crossing with the extending direction of the first and second parts. The first part includes a portion near the trench gate electrode, which has an impurity concentration equal to or lower than that of the body region.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: April 29, 2008
    Assignee: DENSO CORPORATION
    Inventors: Hitoshi Yamaguchi, Mikimasa Suzuki, Yoshiyuki Hattori
  • Patent number: 7364972
    Abstract: A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first circuit including a first and a second field-effect transistor, the first drain region of the first transistor accompanying a first load capacitance, the second drain region of the second transistor accompanying a second load capacitance smaller than the first load capacitance, and the first gate insulation film of the first transistor having an average relative dielectric constant higher than that of the second gate insulation film of the second transistor, thereby realizing a high operation speed.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: April 29, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mizuki Ono, Akira Nishiyama
  • Patent number: 7364973
    Abstract: A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drain regions is formed by implanting impurities of a second conductivity type, opposite the first conductivity type, into the semiconductor substrate adjacent only to one side of the first gate electrode and adjacent to both sides of the second gate electrode. To prevent misalignment of a bit line contact hole with a contact region, additional impurities are implanted only into a bit line contact region of the mask ROM device region. When a semiconductor device formed on the same substrate as the mask ROM device includes a double diffused region, additional implantation for both may be realized simultaneously.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: April 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Khe Yoo, Weon-ho Park, Byoung-ho Kim
  • Patent number: 7364974
    Abstract: A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulating material, an active layer of crystalline semiconductor material, an upper gate insulating layer of crystalline rare earth insulating material, and an upper gate layer of crystalline rare earth conductive material. The upper gate layer and the upper gate electrically insulating layer are etched and a contact is deposited on the upper gate layer to define an upper gate structure. An impurity is implanted into the lower gate layer to define a lower gate area aligned with the upper gate structure. A source and drain are formed in the active layer and contacts are deposited on the source and drain, respectively.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: April 29, 2008
    Assignee: Translucent Inc.
    Inventor: Petar B. Atanackovic
  • Patent number: 7364975
    Abstract: Methods of fabricating semiconductor devices are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece including a plurality of active area regions defined therein, and forming at least one trench in the workpiece between at least two of the plurality of active area regions. A first insulating material is deposited over the plurality of active area regions and the at least one trench, partially filling the at least one trench with the first insulating material and forming peaks of the first insulating material over the plurality of active area regions. A masking material is formed over the first insulating material in the at least one trench, leaving the peaks of the first insulating material over the plurality of active area regions completely exposed. At least the peaks of the first insulating material are removed from over the plurality of active area regions.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: April 29, 2008
    Assignee: Infineon Technologies AG
    Inventors: Marcus Culmsee, Frank Weber, Josef Maynollo