Abstract: A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline surface and an amorphous region where deposited on an amorphous surface. A four-component wet etch mixture is tuned to selectively etch the amorphous region while retaining the epitaxial region, wherein the four-component wet etch mixture comprises an oxidizing agent, an etchant, a buffer and a diluent.

Abstract: Disclosed are a heterojunction bipolar transistor and a method of fabricating the same. A first dielectric layer easily etched is deposited on the overall surface of a substrate before an isolation region is defined. The first dielectric layer and a sub-collector layer are selectively etched, and then a second dielectric layer etched at a low etch rate is deposited on the overall surface of the substrate. Via holes are formed in the first and second dielectric layers, and then the first dielectric layer is removed using a difference between etch characteristics of the first and second dielectric layers. Accordingly, a reduction in power gain, generated at the interface of a compound semiconductor and a dielectric insulating layer (the second dielectric layer), can be eliminated.

Abstract: There is provided a method of fabricating semiconductor devices that allows ion implantation to be performed at high temperature with ions accelerated with high energy to help to introduce dopant in a semiconductor substrate, in particular a SiC semiconductor substrate, at a selected region to sufficient depth. To achieve this the method includes the steps of: providing the semiconductor substrate at a surface thereof with a mask layer including a polyimide resin film, or a SiO2 film and a thin metal film; and introducing dopant ions.

Abstract: A capacitor and a method for fabricating the same are provided. The capacitor includes: a substrate; an inter-layer insulation layer formed over the substrate and including a contact hole; a storage node formed over the inter-layer insulation layer and filled into the contact hole; a tantalum oxide layer of single crystal formed over the storage node; and a plate formed over the tantalum oxide layer.

Abstract: Closure at the opening of a trench with an epitaxial film is restrained, and thereby, filling morphology in the trenches is improved. A method for manufacturing a semiconductor substrate includes a step for growing an epitaxial layer 11 on the surface of a silicon substrate 13, a step of forming a trench 14 in this epitaxial layer, and a step of filling the inside of the trench 14 with the epitaxial film 12, wherein mixed gas made by mixing halogenoid gas into silicon source gas is circulated as material gas in filling the inside of the trench with the epitaxial film, and when the standard flow rate of the halogenoid gas is defined as Xslm and the film formation speed of the epitaxial film formed by the circulation of the silicon source gas is defined as Y?m/min, in the case when the aspect ratio of the trench is less than 10, an expression Y<0.2X+0.10 is satisfied, and in the case that the aspect ratio of the trench is between 10 and less than 20, an expression Y<0.2X+0.

Abstract: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.

Abstract: The process comprises a step of growing epitaxially mixed crystals of a compound semiconductor represented by the composition formula Inx(Ga1-yAly)1-xP on a GaAs substrate 12 to form an epi-wafer having an n-type cladding layer 14 (0.45<x<0.

Abstract: A process is disclosed for creating semiconductor devices such as RFID assemblies wherein an array of dies mounted to a substrate is spaced apart at a first pitch, and the substrate is removed after the positions of the dies in the array is fixed by a solidifiable substance. The solidifiable substance is then removed without changing the relative positions of the dies in the array. All or a selected portion of the array of dies is then electrically attached to a plurality of straps or interposers arranged in a corresponding array. The spacing, or pitch, between the dies in the die array may be changed before or after the substrate is removed to match the pitch of the straps or interposers in the corresponding array. An RFID device created using the process inventive is also disclosed.

Abstract: The object of the invention is to provide a method for manufacturing an SOI layer which is devoid of damages, has a reduced variation in thickness, and is uniform in thickness.

Abstract: A method for creating electrical pathways for semiconductor device structures using laser machining processes is provided. The method of the present invention includes providing a semiconductor substrate and forming one or more depressions in the semiconductor substrate using laser machining processes. Optionally, a film may be deposited over the semiconductor substrate and the depressions may be formed therein. Subsequently, the semiconductor substrate and/or film are etched to smooth out the depressions and the depressions are then filled with an electrically conductive material. The electrically conductive material is then planarized down to the surface of the semiconductor substrate or film thereby isolating the electrically conductive material in the depressions.

Abstract: A laser beam processing method comprising the step of processing-feeding a wafer having devices which are formed in a large number of areas sectioned by streets arranged in a lattice pattern on the front surface while a laser beam capable of passing through the wafer is applied to the wafer to form deteriorated layers along the streets in the inside of the wafer, wherein the laser beam is applied at a predetermined angle toward a direction intersecting at right angles to the processing-feed direction relative to a direction perpendicular to the laser beam applied surface of the wafer.

Abstract: In a method of forming a semiconductor device, a copper diffusion-prevention layer is formed underneath a substrate. Impurity regions are formed on the surface of the substrate. A copper wiring is electrically connected to the impurity regions. The copper diffusion-prevention layer is formed before forming the lightly doped source/drain regions to prevent copper atoms from diffusing into the substrate.

Abstract: A method of manufacturing a heterojunction device includes forming a first layer of p-type aluminum gallium nitride; forming a second layer of undoped gallium nitride on the first layer; and forming a third layer of aluminum gallium nitride on the second layer, to provide an electron gas between the second and third layers. A heterojunction between the first and second layers injects positive charge into the second layer to compensate and/or neutralize negative charge within the electron gas.

Abstract: A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy on the silicon substrate; adjusting the lattice constant of the silicon alloy layer by selecting the alloy material content to adjust and to select a type of strain for the silicon alloy layer; depositing a single-crystal, epitaxial oxide film, by atomic layer deposition, taken from the group of oxide films consisting of perovskite manganite materials, single crystal rare-earth oxides and perovskite oxides, not containing manganese; and rare earth binary and ternary oxides, on the silicon alloy layer; and completing a desired device.

Abstract: First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown, a connection structure of a material having an amorphous state is formed on a portion of the insulation layer located between the first and second preliminary epitaxial layers. The material having an amorphous state is then changed into material having a single-crystalline state. Thus, portions of the first and second epitaxial layers are connected to each other through the connection structure so that the epitaxial layers and the connection structure constitute a single-crystalline structure layer that is free of voids for use as a channel layer or the like of a semiconductor device.

Abstract: Methods are disclosed for fabricating a compound nitride semiconductor structure. An amorphous buffer layer that includes nitrogen and a group-III element is formed over a substrate disposed within a substrate processing chamber at a first temperature. The temperature within the chamber is increased to a second temperature at which the amorphous buffer layer coalesces into crystallites over the substrate. The substrate is exposed to a corrosive agent to destroy at least some of the crystallites. A crystalline nitride layer is formed over the substrate at a third temperature using the crystallites remaining after exposure to the corrosive agent as seed crystals. The third temperature is greater than the first temperature. The crystalline nitride layer also includes nitrogen and a group-III element.

Abstract: A method of forming a polycrystalline silicon thin film with improved electrical characteristics and a method of manufacturing a thin film transistor using the method of forming the polycrystalline silicon thin film.

Abstract: A semiconductor material with photoconductive properties and a method of the semiconductor, wherein a base material is grown and then annealed post-growth at a temperature of 475° C. or less. It has been found that be annealing at temperatures of 475° C., or less the carrier lifetime of the material and the resistivity can be optimized so as to obtain semiconductor with useful photoconductive properties.

Abstract: A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.

Abstract: A method for manufacturing a semiconductor device capable of reducing a short channel effect, whereby the semiconductor device includes a pair of impurity regions for a source and a drain formed on a semiconductor substrate, a gate having a gate electrode used to control a drain current, side walls formed on both sides of the gate electrode, and a pair of electrode members formed on both sides of the semiconductor substrate and in contact with the side walls. First impurity regions are formed by thermal diffusion of impurities from each of the electrode members, and second impurity regions each having thickness smaller than the first impurity region and extending below the gate electrode are formed by thermal diffusion of impurities from the side walls.

Abstract: A method of fabricating a pattern on a substrate, comprises the steps of: depositing; such as by ink-jet printing, multiple drops of a first liquid material as a first deposit (15) on the substrate: depositing, such as by ink-jet printing, multiple drops of a second liquid material (17) as a second deposit on the substrate, and in contact with the first material (15) while the first material is liquid, the first and second liquid materials being mutually immiscible; and producing on the substrate a solid deposit from at least one of said liquid materials. In a preferred embodiment, the method comprises ink-jet printing multiple drops of liquid material immiscible with said second liquid material as a third deposit (16) on the substrate, the third deposit (16) being spaced from the first (15) by a predetermined gap and the second deposit (17) applied in said gap overlapping the first and third deposits (15, 16).

Abstract: In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the etching, a circuit component is formed in the first circuitry area and a circuit component is formed in the second circuitry area. Dielectric material is formed over the first and second circuitry areas. The dielectric material comprises a conductive contact extending outwardly from the circuit component in the first circuitry area. The dielectric material has a first outermost surface. A portion of the dielectric material and a portion of the conductive contact are removed to form a second outermost surface of the dielectric material which has greater degree of planarity than did the first outermost surface. Other aspects are contemplated.

Abstract: Methods for forming a bump on a semiconductor substrate, the substrate having a contact pad thereon, is provided. In one embodiment, the method comprises depositing a passivation layer over the substrate and the contact pad. The passivation layer is patterned and etched to form a plurality of openings in the passivation layer exposing portions of the contact pad. An under bump metallurgy (UBM) layer is deposited over the etched passivation layer and in the plurality of openings thereof to contact the contact pad. A photoresist layer is formed on the UBM layer and then patterned and etched to form at least one opening substantially overlying the contact pad. An electrically conductive material is deposited into the opening formed in the photoresist layer and overlying the UBM layer and aligned with the contact pad. A portion of the remaining photoresist layer is removed. The UBM layer is etched using the electrically conductive material as a mask.

Abstract: A semiconductor component includes a substrate having a plurality of compliant contact bumps formed over a surface thereof. A semiconductor chip has a plurality of contact regions formed over a surface thereof. The compliant contact bumps of the substrate are electrically connected with the contact regions of the semiconductor chip and wherein the semiconductor chip is mechanically attached to the substrate. As an example, this connection and attachment can be achieved by soldering the contact bumps to the contact regions.

Abstract: Disclosed is a method for fabricating a semiconductor device capable of preventing an inter-layer insulation layer from being damaged during a wet cleaning process due to a density difference created by reliance on a thickness of a SOG layer subjected to a curing process and of overcoming defects caused by an improper contact opening in a certain region and a punch taken place by micro voids of an APL layer. Particularly, the method includes the steps of: forming a plurality of conductive structure on a substrate; forming a spin-on-glass layer; curing the spin-on-glass layer; forming an advanced-planarization-layer on the spin-on-glass layer; and forming a plurality of contact holes by selectively etching the advanced-planarization-layer and the spin-on-glass layer, thereby exposing portions of the substrate.

Abstract: A method of making a diffusion barrier for a interconnect structure. The method comprises: providing a conductive line in a bottom dielectric trench; depositing a sacrificial liner on the cap layer; depositing an interlayer dielectric; forming a trench and a via in the top interlayer dielectric; and removing a portion of the cap layer and the sacrificial layer proximate to the bottom surface of the via. The removed portions of the cap layer and sacrificial layer deposit predominantly along the lower sidewalls of the via. The conductive line is in contact with a cap layer, and the sacrificial layer is in contact with the cap layer. The invention is also directed to the interconnect structures resulting from the inventive process.

Abstract: A method of manufacturing a semiconductor device. The device includes a plurality of layers on a semiconductor substrate. The method includes the steps of dividing a pattern of at least one layer into a plurality of sub-patterns, and joining the divided sub-patterns to perform patterning. A layer that includes wiring substantially affects operation of the semiconductor device depending on a positional relationship to any other wiring. The patterning is performed by one-shot exposure using a single mask.

Abstract: A method and structure for using porous diamond interlayer dielectrics (ILDs) in conjunction with carbon nanotube interconnects is herein described. A diamond ILD is deposited on an underlaying layer. The diamond layer is optionally and selectively removed of non-sp3 bond to create a porous diamond film. Trenches and vias are etched in the porous diamond ILD. Carbon nanotubes are deposited on the diamond ILD filling the trenches using a liquid crystal host-carbon nanotube solution. Using methods of nematic liquid crystal alignment, the carbon nanotubes are aligned under the influence of the liquid crystals. At least some of the liquid crystal solution is removed leaving an aligned carbon nanotubes.

Abstract: The invention is aimed to prevent that fall of characteristic of a solar battery and producing yield caused by particles of powder condition generating from working part at laser beam process in the method producing the solar battery by laser beam process. The constitution of the invention is characterized by comprising: a first step forming the lower electrode and the semiconductor layer on the insulating substrate by laminating; a second step forming a protective film on surface of the semiconductor; a third step forming an opening portion at the semiconductor layer, or the semiconductor layer and the lower electrode by laser beam process after the second step; and a fourth step removing the protective film.

Abstract: This invention relates to process sequence by high-speed atomic layer chemical vapor processing that includes deposition for diffusion barriers in the etched features on substrate followed by gap fill and subsequent in-situ removal of the blanket films on the top by plasma enhanced vapor phase processes. The apparatus and process sequences employed in these processing scheme allows the practitioner to complete all vapor phase process sequences of diffusion barrier deposition, gap fill and planarization of copper and diffusion barrier planarization. In case of copper metallization scheme, vapor phase gap fill can be employed to replace electrochemical deposition of copper and removal of copper and the diffusion barrier by vapor phase reactions can replace chemical-mechanical-polishing. Furthermore, such a processing scheme can be employed to deposit gate level dielectric layer, shallow trench isolation and also to form first metal contact plugs with a suitable barrier at the front end of line processing.

Abstract: A semiconductor package and substrate having multi-level plated vias provide a high density blind via solution at low incremental cost. Via are half-plated atop a circuit pattern and then a second via half is added to complete the via after isolation of elements of the circuit pattern. Successive resist pattern applications and etching are used to form a via tier atop a circuit pattern that is connected by a thin plane of metal. After the tier is deposited, the thin metal plane is etched to isolate the circuit pattern elements. Dielectric is then deposited and the top half of the via is deposited over the tier. The tier may have a larger or smaller diameter with respect to the other half of the via, so that the via halves may be properly registered. Tin plating may also be used to control the etching process to provide etching control.

Abstract: Embodiments include an interconnect or trace of electrically conductive material with a contact surface, and a dielectric layer overlying the contact surface with a via formed on the dielectric layer and to the contact surface. The via sidewalls and perimeter are layered with a manganese oxide (MnO2) layer which is layered over with a conductive polymer material. An interconnect material is formed in the via and in a trench above the perimeter of the via such that the interconnect material is on the conductive polymer material and contacts the contact surface. An additional dielectric layer may be formed over the interconnect material and an additional via may be formed therethrough so that an additional structure having a MnO2 layer, conductive polymer material, and interconnect material can be formed in the additional via and to the interconnect material.

Abstract: A method of forming a predetermined pattern by disposing a functional liquid on a substrate, the method includes the steps of forming banks on the substrate, and disposing the functional liquid on a region divided by the banks, wherein a width of the region is partially formed so as to be large.

Abstract: A process and structure for a metal interconnect includes providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.

Abstract: Methods of fabricating semiconductor devices having a carbon-containing metal silicide layer and semiconductor devices fabricated by the methods are provided. A representative method includes the steps of preparing a semiconductor substrate and forming a gate electrode and source/drain regions on the semiconductor substrate, such that the gate electrode has a first metal silicide layer on an upper part thereof which contains carbon and the source/drain regions have second metal silicide layers on their substantially carbon-free upper parts.

Abstract: A method of forming a copper interconnect on a substrate comprises providing a substrate that includes a dielectric layer and a trench etched into the dielectric layer, depositing a barrier layer within the trench, using a palladium immobilization process to form a metal catalyst layer on the barrier layer, activating the metal catalyst layer, and using a vapor deposition process to deposit a copper seed layer onto the metal catalyst layer. The vapor deposition process may include PVD, CVD, or ALD. An electroplating process or an electroless plating process may then be used to deposit a bulk copper layer onto the copper seed layer to fill the trench. A planarization process may follow to form the final interconnect structure.

Abstract: An etching method of subjecting a base material to an etching process using an etching agent containing hydrogen fluoride and ozone is disclosed. The base material has a first region constituted from silicon as a main material and a second region constituted from SiO2 as a main material. The etching method includes the steps of: preparing the base material; and supplying the etching agent onto the base material to form a step between the first and second regions using a feature that an etching rate of silicon by the etching agent is higher than an etching rate of SiO2 by the etching agent, so that the height of the surface of the first region is lower than the height of the surface of the second region.

Abstract: A system, composition, and a method for planarizing or polishing a composite substrate are provided. The planarizing or polishing system comprises (i) a polishing composition comprising (a) about 0.5 wt. % or more of fluoride ions, (b) about 1 wt. % or more of an amine, (c) about 0.1 wt. % or more of a base, and (d) water, and (ii) an abrasive. The present invention also provides a method of planarizing or polishing a composite substrate comprising contacting the substrate with a system comprising (i) a polishing composition comprising (a) about 0.5 wt. % or more of fluoride ions, (b) about 1 wt. % or more of an amine, (c) about 0.1 wt. % or more of a base, and (d) water, and (ii) an abrasive.

Abstract: We have reduced the critical dimension bias for reticle fabrication. Pattern transfer to the radiation-blocking layer of the reticle substrate essentially depends upon use of a hard mask to which the pattern is transferred from a photoresist. The photoresist pull back which occurs during pattern transfer to the hard mask is minimalized. In addition, a hard mask material having anti-reflective properties which are matched to the reflective characteristics of the radiation-blocking layer enables a reduction in critical dimension size and an improvement in the pattern feature integrity in the hard mask itself. An anti-reflective hard mask layer left on the radiation-blocking layer provides functionality when the reticle is used in a semiconductor device manufacturing process.

Abstract: A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolyS1-xGex, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi1-xGex, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.

Abstract: A method of etching a sacrificial oxide layer covering an etch-stop silicon nitride underlayer, involves exposing the sacrificial oxide to anhydrous HF at a temperature of less than about 100° C. and/or at vacuum level lower than 40 Torr; and subsequently performing an in-situ vacuum evaporation of etch by-products at a temperature of more than about 100° C. and at vacuum level lower than the 40 Torr without exposure to ambient air.

Abstract: A method for finishing a metal line for a semiconductor device is disclosed, in which polymer generated when forming the metal line including aluminum and its alloy is effectively removed and the metal line is prevented from being eroded. A chlorine radical and a chlorine compound remaining on a surface of the metal line are removed using H2O plasma and the polymer is removed using H2O gas and HF gas not plasma. Therefore, it is possible to improve reliability and yield of the semiconductor device.

Abstract: A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques. In one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size F that are spaced apart by the feature size F, for instance. The second photomask has an opening which is sized to create a desired inter-select gate gap, such as 3 F or 5 F. A third photomask is used to provide protective portions in a second photoresist layer over the select gate structures. The final structure has memory elements of width F spaced apart by a distance F, and select gates of width 3 F spaced apart by 3 F or 5 F. In another approach, the patterns of three photomasks are transferred to respective photoresist layers to create an analogous final structure.

Abstract: A system that generates an intense hot gas stream is described to etch a polymer on a substrate used in the manufacture of semiconductor and MEMS devices with no surface damage. The etching process is particularly useful to remove a polymer from relatively high aspect Height-to-Width and Width-to-Height ratio holes that can include trenches, having relatively large aspect ratios for removal of polymers used in connection with the manufacturing of microstructures.

Abstract: A method for etching an upper metal film of a capacitor, enables a safe etching of the upper metal film of a capacitor by exploiting an over-etch step. The method for etching the upper metal film of the capacitor includes the steps of forming a lower metal film, a lower nitride film, an upper metal film, and an upper nitride film on a substrate having a predetermined device formed thereon, and then forming a pattern thereover; etching the upper nitride film with CHF3, Ar and Cl2 using the pattern; over etching the upper metal film more than 50% with CHF3, Ar and N2 using the pattern; etching the upper metal film with CHF3, Ar and N2 using the pattern; and etching the lower nitride film with CHF3 and Ar using the pattern.

Abstract: Methods are provided for fabricating a semiconductor device that include the steps of: sequentially forming a metal interconnection and a protecting layer on a semiconductor substrate; forming a contact hole on the protecting layer; isolating the contact hole by forming a molding layer and an etching stop layer stacked thereon; forming a sacrificial layer on the etching stop layer so as to fill the contact hole; forming a photoresist layer with an opening so as to expose the sacrificial layer and such that the opening of the photoresist layer aligns with the contact hole; forming a trench in the molding layer to penetrate the sacrificial layer and the etching stop layer; and performing a wet etching on the semiconductor substrate having the trench to remove the photoresist layer and the sacrificial layer, wherein the wet etching step is performed using an organic compound and fluoride ion-based buffered solution.

Abstract: A digital lithographic process first deposits a mask layer comprised of print patterned mask features. The print patterned mask features define gaps into which a target material may be deposited, preferably through a digital lithographic process. The target material is cured or hardened, if necessary, into target features. The mask layer is then selectively removed. The remaining target features may then be used as exposure or etch masks, physical structures such as fluid containment elements, etc. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.

Abstract: There is provided an underlayer coating causing no intermixing with photoresist layer and having a high dry etching rate compared with photoresist, which is used in lithography process of manufacture of semiconductor device. Concretely, it is an underlayer coating forming composition for forming a porous underlayer coating for use in manufacture of semiconductor device, comprising a blowing agent, an organic material and a solvent, or a polymer having a blowing group and a solvent. The underlayer coating formed from the composition has porous structure which has pores therein, and makes possible to attain a high dry etching rate.

Abstract: A chemical solution coating method includes: a first step of disposing a semiconductor substrate on a substrate supporting unit with a first face to be coated with a chemical solution facing upward; a second step of moving a chemical solution spraying member for spraying the chemical solution to an initial position which is positioned in the vicinity of the first face of the semiconductor substrate and where the chemical solution is to be applied; and a third step of moving the chemical solution spraying member from the initial position in accordance with a predetermined travel pattern and, simultaneously, spraying the chemical solution from the chemical solution spraying member toward the first face of the semiconductor substrate.

Abstract: Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole.