Image sensor and method for forming the same
A method for forming an image sensor is provided. The method includes providing a semiconductor substrate having a pixel region and a peripheral circuit region, forming a photoelectric transformation section at the semiconductor substrate of the pixel region, forming a plurality of interlayer dielectrics over the semiconductor substrate with interconnections interposed therebetween, forming a passivation layer, partially patterning the passivation layer at the peripheral circuit region to form a via hole exposing the interconnection and removing the passivation layer and the underlying interlayer dielectric at the pixel region. The method further includes forming a conductive layer to fill the via hole and etching the conductive layer to remove the conductive layer at the pixel region and form a via plug and a conductive pad at the peripheral circuit region. The via plug fills the via hole and the conductive pad protrudes outwardly from the via hole.
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This application claims priority of Korean Patent Application No. 2005-09541, filed on Feb. 2, 2005 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention is directed to image sensors and to methods for forming the same.
2. Description of Related Art
Image sensors are semiconductor devices for converting an optical image into an electrical signal. Generally, image sensors are classified into charge coupled devices (CCDs) or complementary metal-oxide-silicon (CMOS) image sensors. CCD image sensors have certain benefits over CMOS image sensors such as having higher photosensitivity and better noise characteristics in comparison to CMOS image sensors. However, CMOS image sensors also hold several key benefits over CCD image sensors in that for example, CMOS image sensors may be prepared by simple processes, are suitable for high integration, and exhibit low power consumption. CCD image sensors on the other hand exhibit high power consumption and are generally not suitable for high integration processes.
With the increasing demand for highly integrated semiconductor devices, studies are being conducted for improving the characteristics of CMOS image sensors. A pixel of a conventional CMOS image sensor includes photodiodes for receiving light and CMOS elements for controlling image signals from the photodiodes. In the photodiodes of the conventional CMOS image sensor, electron-hole pairs are generated based upon the wavelength and intensity of red, green, and blue lights impinging through a color filter. In addition, output signals vary with the amount of the electrons generated.
A conventional image sensor such as the above-described CMOS image sensor typically has a pixel region where a photoelectric transformation section is formed and also a peripheral circuit region for detecting signals from the pixel region. The peripheral circuit region is disposed to surround the pixel region. Moreover, an image sensor also includes multi-layer interconnections, interlayer dielectrics, and etch-stop layers. It is also noted that the greater the number of etch-stop layers that an image sensor has, the lower the transmittance of incident light will be for the image sensor. For the above reason, the intensity of light reaching the photodiode is lower than that of light impinging upon the highest layer. Thus, to enhance the photosensitivity of an image sensor, there is a need for a process which removes unnecessary interlayer dielectrics and etch-stop layers and which is also a relatively simple and cost effective process.
SUMMARY OF THE INVENTIONIn an exemplary embodiment of the present invention, a method for forming an image sensor is provided. The method includes providing a semiconductor substrate having a pixel region and a peripheral circuit region, forming a photoelectric transformation section at the semiconductor substrate of the pixel region, forming a plurality of interlayer dielectrics over the semiconductor substrate with interconnections interposed therebetween, forming a passivation layer, partially patterning the passivation layer at the peripheral circuit region to form a via hole exposing the interconnection and removing the passivation layer and the underlying interlayer dielectric at the pixel region. The method further includes forming a conductive layer to fill the via hole and etching the conductive layer to remove the conductive layer at the pixel region and form a via plug and a conductive pad at the peripheral circuit region. The via plug fills the via hole and the conductive pad protrudes outwardly from the via hole.
In another exemplary embodiment, a method for forming an image sensor is provided. The method includes preparing a semiconductor substrate having a pixel region and a peripheral circuit region, forming device isolation layers on the semiconductor substrate to define active regions, forming a photoelectric transformation section at the active region of the pixel region, forming a shield layer on an entire surface of the semiconductor substrate and forming a plurality of intermediate interconnection layers on the shield layer. Each of the intermediate interconnection layers includes a first etch-stop layer, a first interlayer dielectric on the first etch-stop layer, and a first interconnection overlapping the device isolation layer at the active region and penetrating the first interlayer dielectric and the first etch-stop layer. The method further includes forming at least one top interconnection layer on the intermediate interconnection layer, the top interconnection layer including a second etch-stop layer, a second interlayer dielectric on the second etch-stop layer, and a second interconnection disposed only at the peripheral circuit region and penetrating the second interlayer dielectric and the second etch-stop layer, forming a passivation layer on the top interconnection layer, partially patterning the passivation layer at the peripheral circuit region to form a via hole exposing the second interconnection while removing the passivation layer and the top interconnection layer at the pixel region to expose the intermediate interconnection layer, forming a conductive layer to fill the via hole, and etching the conductive layer to remove the conductive layer at the pixel region and form a via plug and a conductive pad at the peripheral circuit region. The via plug fills the via hole and the conductive layer protrudes outwardly from the via hole.
In another exemplary embodiment, an image sensor is provided. The image sensor includes a semiconductor substrate having a pixel region and a peripheral circuit region, a device isolation layer disposed at the semiconductor substrate to define an active region, a photoelectric transformation section disposed in the semiconductor substrate at the pixel region, a shield layer disposed on the semiconductor substrate and a plurality of intermediate interconnection layers disposed on the shield layer. Each of the intermediate interconnection layers includes a first etch-stop layer, a first interlayer dielectric on the first etch-stop layer, and a first interconnection overlapping the device isolation layer at the active region and penetrating the first interlayer dielectric and the first etch-stop layer. The image sensor further includes at least one top interconnection layer disposed on the intermediate interconnection layer, the top interconnection layer including a second etch-stop layer, a second interlayer dielectric on the second etch-stop layer, and a second interconnection disposed only at the peripheral circuit region and penetrating the second interlayer dielectric and the second etch-stop layer, a passivation layer disposed on the top interconnection layer, a via plug connected to the second interconnection through the passivation layer and a conductive pad at the peripheral circuit region, a resin layer connected to the shield layer through the interlayer dielectric and the first etch-stop layer of the intermediate dielectric at the pixel region, a planarization layer disposed to cover the conductive pad, the top interconnection layer, the resin layer, and the intermediate interconnection layer, and a color filter layer and a microlens disposed on the planarization layer at the pixel region.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. The invention may be applied to, for example, methods of forming CMOS or CCD image sensors. In the drawings, the height of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like numbers refer to like elements throughout.
As illustrated in the exemplary embodiment of
As illustrated in
As illustrated in
As illustrated in
As previously described above in relation to the description of a conventional image sensor, loss caused by light interference arises at boundaries between the etch-stop layers 9a and 9b, the interlayer dielectrics 11a and 11b, and the passivation layers 21. Further, the intensity of light impinging on the photoelectric transformation section 5 is lowered due to intrinsic absorption coefficients of the layers. Thus, to enhance the photosensitivity of an image sensor, the top interconnection layer 17 on the pixel region where the photoelectric transformation section 5 is disposed should be removed. Referring to
As illustrated in
As illustrated in
In the image sensor of
In sum, the process of the exemplary embodiments of the invention, by removing unnecessary layers at the pixel region when the via hole is formed at the peripheral circuit region in forming an image sensor, provides a simplified process wherein the photosensitivity of an image sensor prepared therefrom is enhanced in comparison to conventional processes.
Having described the exemplary embodiments of the present invention, it is further noted that it is readily apparent to those of reasonable skill in the art that various modifications may be made without departing from the spirit and scope of the invention which is defined by the metes and bounds of the appended claims.
Claims
1. A method of forming an image sensor, comprising:
- providing a semiconductor substrate having a pixel region and a peripheral circuit region;
- forming a photoelectric transformation section at the semiconductor substrate of the pixel region;
- forming a plurality of interlayer dielectrics over the semiconductor substrate with interconnections interposed therebetween;
- forming a passivation layer;
- partially patterning the passivation layer at the peripheral circuit region to form a via hole exposing the interconnection and removing the passivation layer and the underlying interlayer dielectric at the pixel region;
- forming a conductive layer to fill the via hole; and
- etching the conductive layer to remove the conductive layer at the pixel region and form a via plug and a conductive pad at the peripheral circuit region, the via plug filling the via hole and the conductive pad protruding outwardly from the via hole.
2. The method as recited in claim 1, further comprising:
- removing the interlayer dielectrics on the photoelectric transformation section at the pixel region to form a cavity;
- forming a resin layer to fill the cavity;
- forming a planarization layer;
- forming a color filter layer on the planarization layer at the pixel region; and
- forming a microlens on the color filter layer.
3. The method as recited in claim 1, wherein patterning the passivation layer and the interlayer dielectric is conducted using a fluorocarbon gas as an etch gas.
4. The method of claim 1, wherein the first etch-stop layer and the second etch-stop layer are made of silicon nitride (Si3N4).
5. The method of claim 1, wherein the plurality of interlayer dielectrics each comprise a material selected from the group consisting of silicon oxide (SiO2) and silicon oxyfluoride (SiOF).
6. The method of claim 3, wherein the fluorocarbon etch gas is selected from the group consisting of trifluoromethane (CF3H), difluoromethane (CF2H2) fluoromethane (CFH3), and carbon tetrafluroide (CF4).
7. The method of claim 1, wherein the conductive layer is formed by a chemical vapor deposition (CVD) process.
8. A method of forming an image sensor, comprising:
- preparing a semiconductor substrate having a pixel region and a peripheral circuit region;
- forming device isolation layers on the semiconductor substrate to define active regions;
- forming a photoelectric transformation section at the active region of the pixel region;
- forming a shield layer on substantially an entire surface of the semiconductor substrate;
- forming a plurality of intermediate interconnection layers on the shield layer, each of the intermediate interconnection layers comprising a first etch-stop layer, a first interlayer dielectric on the first etch-stop layer, and a first interconnection overlapping the device isolation layer at the active region and penetrating the first interlayer dielectric and the first etch-stop layer;
- forming at least one top interconnection layer on the intermediate interconnection layer, the top interconnection layer comprising a second etch-stop layer, a second interlayer dielectric on the second etch-stop layer, and a second interconnection disposed only at the peripheral circuit region and penetrating the second interlayer dielectric and the second etch-stop layer;
- forming a passivation layer on the top interconnection layer;
- partially patterning the passivation layer at the peripheral circuit region to form a via hole exposing the second interconnection while removing the passivation layer and the top interconnection layer at the pixel region to expose the intermediate interconnection layer;
- forming a conductive layer to fill the via hole; and
- etching the conductive layer to remove the conductive layer at the pixel region and form a via plug and a conductive pad at the peripheral circuit region, the via plug filling the via hole and the conductive layer protruding outwardly from the via hole.
9. The method as recited in claim 8, wherein the passivation layer is a triple layer comprised of silicon nitride, silicon oxyfluoride, and silicon nitride, and the conductive layer is comprised of a material selected from the group consisting of aluminum, copper, and tungsten.
10. The method as recited in claim 9, wherein patterning the passivation layer and the interconnection layer is conducted using a fluorocarbon gas as an etch gas.
11. The method as recited in claim 8, further comprising:
- removing the first interlayer dielectric and the first etch-stop layer of the intermediate interconnection layer at the pixel region to form a cavity exposing the shield layer;
- filling a resin layer to fill the cavity;
- forming a planarization layer;
- forming a color filter layer on the planarization layer at the pixel region; and
- forming a microlens on the color filter layer.
12. The method as recited in claim 11, wherein forming the resin layer comprises:
- coating a thermosetting resin layer on the semiconductor substrate to fill the cavity;
- heating the semiconductor substrate to harden the thermosetting resin layer; and
- etching back the hardened thermosetting resin layer to form a resin layer within the cavity.
13. The method of claim 8, wherein the first etch-stop layer and the second etch-stop layer are made of silicon nitride (Si3N4).
14. The method of claim 8, wherein the first interlayer dielectric and second interlayer dielectric each comprise a material selected from the group consisting of silicon oxide (SiO2) and silicon oxyfluoride (SiOF).
15. The method of claim 10, wherein the fluorocarbon etch gas is selected from the group consisting of trifluoromethane (CF3H), difluoromethane (CF2H2) fluoromethane (CFH3), and carbon tetrafluroide (CF4).
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Type: Grant
Filed: Jan 19, 2006
Date of Patent: Apr 29, 2008
Patent Publication Number: 20060170069
Assignee: Samsung Electronics, Co., Ltd. (Suwon-Si)
Inventor: Ki-Hong Kim (Yongin-si)
Primary Examiner: Cuong Nguyen
Attorney: F. Chau & Associates, LLC.
Application Number: 11/334,936
International Classification: H01L 21/00 (20060101);