Abstract: The present invention provides secure IP protocol capable storage devices using Virtual Local Area Network (VLAN) techniques. Specific embodiments of the present invention provide techniques for securing VLAN aware storage devices, and the like. In specific embodiments, techniques according to the present invention can provide Internet data centers that are responsible for keeping their customer's computers and storages safe and secure with the capability to strictly separate LAN access for different customers using VLAN (virtual LAN) technology.

Abstract: A communication control apparatus includes a storage device configured to store corresponding weighted values for each of a plurality of predetermined portions of a sender address, a connection request receiver configured to receive a connection request packet including a connection request, a weight detector configured to obtain a weighted value corresponding to a part of the sender address assigned to the connection request packet from among the weighted values stored in the storage device, a connection controller configured to reject the connection request, when the obtained weighted value exceeds a predetermined value, by determining that a communication apparatus consumes more than a predetermined amount of a resource and discarding the connection request packet, and allow the connection request when the obtained weighted value falls within a predetermined range that is lower than the predetermined value, a weight updater configured to update the weighted values, and a packet transmitter.

Abstract: A system and method for the management of communication services from a service provider by a customer of the provider. The management system employs an Internet-based architecture that provides access to user's virtual private networks via an end user browser. The customer service management (CSM) system service director (SD) maintains a relational database for storing user specific information retrieved from the network manager.

Abstract: Content subscribers can dynamically activate content and content publishing resources that are distributed on a network. A content request from the content subscriber can engage a content locator in determining an appropriate content publisher to activate the content. Once the appropriate content publisher is found, the content publisher activates the content by presenting appropriate content publishing resources. Optionally, two more content publishers cooperate together to activate the requested content. Licenses to the content and content publishing resources are monitored to ensure that content publishers are compensated. System components, such as content subscribers, content locators, content publishers, are auto-configured during initial registration and dynamically updated if configuration parameters change. Optionally, a performance driver changes various configuration parameters of system components to ensure a desired performance during content activation.

Abstract: Methods and apparatuses for processing media data transmitted in a data communication medium. A digital processing system is provided with a time related sequence of media data provided to the digital processing system based on a set of data, wherein the set of data indicates a method to transmit the time related sequence of media data according to a transmission protocol. The set of data, itself, is a time related sequence of data associated with the time related sequence of media data. The time related sequence of media data may be presented and/or stored by the digital processing system.

Abstract: A method and apparatus for servicing transit and transmit traffic in a node of a network. The network includes a plurality of nodes connected by first and second rings formed by two or more transmission media. The method includes receiving usage data from a downstream node, identifying a first weighted value associated with a provisioning rate associated with the downstream node and a second weighted value associated with a provisioning rate of the node, determining an allowed usage for the node using the usage data and the first and second weighted values and servicing transmit and transit traffic received at the node including limiting the servicing of the transmit traffic in accordance with the determined allowed usage.

Abstract: A system and method of active latency detection for network applications that allows network latency to be calculated from a single host system. Periodic requests are generated from the host system and directed to a remote system in a way that requires minimal processing by the remote system. Latencies are calculated from the timing information associated with the periodic requests and can be combined with timing information associated with application packets to generate a latency trace for one or more network applications.

Abstract: A proxy computer of a network can receive incoming telephony messages from one or more computers outside of the network and proxy them to computers within the network. Similarly, the proxy computer can receive outgoing telephony messages from within the network and proxy them to computers outside of the network. To set up inbound calls, a proxy program on the proxy computer looks for the presence of an alias in the call signaling messages, references a data structure to determine which computer on the network is associated with the alias, and proxies the call signaling and control messages between the callee computer and the calling computer based on the association, thereby creating a logical connection between the calling computer and the callee computer.

Abstract: A system and method for the optimized storage and retrieval of video data at distributed sites calls for the deployment of “Smart Mirror” sites throughout a network, each of which maintains a copy of certain data managed by the system. User addresses are assigned to specific delivery sites based on an analysis of network performance with respect to each of the available delivery sites. Generalized network performance data is collected and stored to facilitate the selection of additional delivery sites and to ensure the preservation of improved performance in comparison to traditional networks.

Abstract: The present invention is directed at a method and apparatus of resolving an address location for a web site when connected with a virtual private network (VPN). Once the public host is connected to, or logged on to, the VPN, a software module within the public host monitors domain name requests and routes them to a domain name server (DNS) associated with the VPN. The VPN DNS then resolves the address location request and returns the address location to the software module in the form of a domain name response. The software module then forwards the address location to the requesting public host.

Abstract: Multiple access internet portals are provided. A representative system, among others, includes a communication facility and a wireless internet server. The communication facility is operable to connect to a plurality of wireless devices through a mobile network. The wireless internet server is coupled to the communication facility and retrieves a personalized profile associated with a registered user an one of the plurality of wireless devices, and provides substantially similar personalized content to said at least one registered user on a variety of platforms associated with the wireless devices. Methods and other systems for multiple access portals are also provided.

Abstract: A method is provided for sending notifications to a mobile device to indicate that there is data on a computing device to be synchronized. Under one embodiment, the notification is sent as a short message service message. Multiple levels of notification are possible with the lowest level indicating only that there is data to be synchronized and the highest level identifying the object that changed and the content of the change.

Abstract: An apparatus for a node of a peer-to-peer network having a plurality of nodes comprises one or more I/O adapters; a cache component; one or more inter-node routing components; a memory mapping component for presenting to the I/O adapters a single address space mapped across a plurality of memory elements each associated with the cache component; and a direct memory access component for performing a memory operation on the memory elements via the memory mapping component on behalf of the I/O adapters.

Abstract: An apparatus, program product and method in which a memory address space is allocated non-uniformly to IO resources in a memory mapped IO fabric based upon the locations of individual IO endpoints to which such IO resources are coupled. In a PCI-based environment, for example, PCI adapters are allocated memory address ranges in a PCI bus address space based upon the locations of the particular slots within which the PCI adapters are mounted.

Abstract: A document processing system may include a document processing device (e.g., a copier), a host (e.g., a computer server), and a multi-device compatible interface for enabling operation of the host and the document processing device from among a plurality of different possible document processing devices. That is, the multi-device compatible interface may determine a set of signals to use with the document processing device upon being connected therewith, and thereafter use the determined set of signals. Accordingly, the multi-device compatible interface may advantageously be used with numerous types of document processing devices despite the differences in their various protocols, connector types, etc.

Abstract: A system for controlling I/O transfers includes a host system or initiator including an adapter driver layer; and a storage controller. The storage controller includes a priority store and an operation queue. The adapter driver is selectively responsive to a datapath command from an initiator application for setting a default I/O priority for a specified logical unit, for storing the default I/O priority for the logical unit to a priority store of the storage controller, and selectively responsive to a data transfer command from an initiator application for storing the data transfer command to the storage controller. The storage controller is responsive to the datapath command for storing the I/O priority default value for the logical unit to the priority store; and responsive to the data transfer command with respect to the logical unit for queuing the data transfer command for execution based on the I/O priority default value.

Abstract: Disclosed is a technique for buffering work requests. It is determined that a work request is about to be placed into an in-memory structure. When the in-memory structure is not capable of storing the work request, a work request ordering identifier for the work request is stored into an overflow structure. When the in-memory structure is capable of storing the work request, a recovery stub is generated for the work request ordering identifier, and the recovery stub is stored into the in-memory structure.

Abstract: A method according to one embodiment may include reserving a plurality of buffers having an aggregate capacity, receiving a frame having a size less than the aggregate capacity, and releasing at least one of the plurality of buffers that is unused to store the frame. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A circuit for buffering data is disclosed. The circuit comprises a first circuit which is coupled to receive a stream of data blocks using a first clock signal. The first circuit removes data blocks, such as idle data blocks or a sequence ordered set of a pair of consecutive sequence ordered sets, from the stream of data blocks to create a first modified data stream which is coupled to a memory device. Finally, a second circuit coupled to the memory device generates a second modified data stream using a second clock signal. The second modified data stream preferably comprises the data blocks of the first modified data stream and idle data blocks inserted among the data blocks of the first modified data stream. Methods of buffering data received in a first clock domain and output in a second clock domain are also disclosed.

Abstract: A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corrected by an error avoidance module in accordance with the invention. Bytes transferred to and from buffers, used by an I/O controllers to temporarily store data while being transferred between synchronous and asynchronous devices, are counted and an error condition is forced based on the count. If the count exceeds the capacity of the buffer, an error condition is forced, thereby reducing chances that errors are incurred into the data transfer.

Abstract: A data transfer control system includes a buffer controller that controls access to a data buffer and a transfer controller that controls data transfer between a PC connected to a BUS1 and the logical units LUN1 and LUN2 connected to a BUS2. The transfer controller includes: a command processing section that starts data transfer to or from the LUN1 based on a command indicated by an ORB for the LUN1 when the ORB is received, and starts data transfer to or from the LUN2 based on a command indicated by an ORB for the LUN2 when the ORB is receive; and a wait processing section that waits the processing of the ORB for the LUN2, when a bus reset occurs during the processing of the ORB for the LUN1 and the ORB for the LUN2 is received after the bus reset has occurred.

Abstract: Methods and apparatus for correlating physical and logical attributes of devices include associating logical-tags (L-tags) and physical-tags (P-tags) with electronic devices. A P-tag includes a P-tag identifier, which can be read by a P-tag reading device, regardless of whether power is applied to the electronic device. In one embodiment, a system includes a P-tag comprising a radio frequency identification (RFID) tag having a non-volatile memory to store physical and logical attribute information; and an electronic device associated with the RFID tag, the electronic device having a processor and a bus, and being communicatively coupled to the RFID tag over the bus, the processor to execute instructions to read information from and write information to the non-volatile memory of the RFID tag.

Abstract: A statistics interface for a media access controller is described. The media access controller core includes a receive engine configured to provide a receive statistics vector associated with receive traffic. The receive engine is configured to output the receive statistics vector within an inter-frame gap over a number of receive clock cycles, where a portion of the receive statistics vector is provided with each clock cycle of the receive clock cycles.

Abstract: An apparatus, system, and method enable access to a storage system by distinguishing SCSI Object-Based Storage Device Commands (OSD) commands from Fibre Channel (FC) SCSI commands on the same port and storage subsystem. The storage subsystem has the capability of identifying the storage protocol from a corresponding command, and processes the command accordingly for a storage device formatted for use with the respective storage protocol. This way, a storage subsystem can consolidate data from several dedicated command ports to a single physical port, while also enabling a single storage system to store and provide access to data in multiple different storage protocol formats.

Abstract: Data speed in an I2C system is increased by operating a master CPU (110) to pipeline a stop/start/address byte transfer instruction by setting a stop bit, setting a start bit, and storing an address byte, operating a control circuit (87) in response to the stop bit to automatically send a stop condition on the I2C bus, operating a timing circuit (40) to count a predetermined delay from the stop condition, and operating the control circuit (87) in response to the start bit to automatically send a start condition on I2C bus after the delay has elapsed. The control circuit (87) automatically sends the address byte on the I2C bus after the start condition has been sent.

Abstract: A computing system includes one or more buses, a plurality of bus agents, and a chip set. The plurality of bus agents are capable of accessing at least one of the buses. The chipset arbitrates access to a bus for at least two of the bus agents such that utilization of the bus for each agent is changeable.

Abstract: A circuit arrangement, program product and method for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices according to a predetermined sequence. The arbiter then automatically alters the sequence for a second group of devices, granting access to the bus for the second group according to the altered sequence. These features allow the order in which the arbiter sequences through the groups to be automatically varied with respect to each other, diminishing the likelihood of lockout.

Abstract: A method, system, and firewall for controlling access to resources within an information technology (IT) system. Commands received from a requesting entity request access to a resource associated with each command. An assigned authority level of the requesting entity is identified. At least one required authority level of the requesting entity is determined for each command as a function of each command and a resource criticality classification of the resource associated with each command. The requesting entity is granted or denied the requested access to the resource associated with each command if a determination has been made that each condition of at least one specified condition has or has not been satisfied, respectively. The at least one specified condition is specific to each command and includes a condition of the assigned authority level matching or exceeding an authority level of the at least one required authority level of each command.

Abstract: An information processing system is provided which includes a plurality of system resources, and an event queue having a predetermined number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.

Abstract: Interrupt process generated in a processor for arithmetic operation is offloaded onto a system control processor, thereby reducing disturbance to the processor for arithmetic operation. A heterogeneous multiprocessor system includes: means which accepts an interrupt in each CPU; means which inquires the accepted interrupt of an interrupt destination management table to select an interrupt destination CPU; means which queues the accepted interrupt; means which generates an inter-CPU interrupt to the selected interrupt destination CPU; each means which receives the inter-CPU interrupt in the interrupt source CPU, performs interrupt process of the interrupt source CPU, and generates the inter-CPU interrupt to the interrupt source CPU in the interrupt destination CPU; means which performs an interrupt end process; and means which performs interrupt process in its own CPU when the interrupt destination CPU selected as a result of the inquiry to the interrupt destination management table is its own CPU.

Abstract: A serial communication system is provided which performs serial communication between host and slave apparatus using half-duplex channel communication with a serial data signal generated by superimposing a data signal on a clock signal. The host apparatus transmits through a transmission path an identification signal generated by superimposing on the clock signal identification data for specifying a slave apparatus to be requested, after transmitting through the transmission path a preamble signal generated by superimposing successively repeated data on the clock signal.

Abstract: A method and apparatus for adaptively adjusting the bandwidth of a data transmission channel having multiple buffered paths. Each output path includes a buffer for holding respective portions of the data. A value representative of at least the number of buffers that are nearly empty of data as compared to a predetermined threshold is determined, and the transmission rate of the input path is adjusted according to the value. Preferably, the buffers are display pipes provided in a graphics controller IC for interfacing between one or more hosts and a graphics display device.

Abstract: Apparatus and systems, as well as methods and articles, may bridge between a link layer and a transport layer in a multi-lane serial-attached small computer system interface (SCSI)-serial SCSI protocol (SAS-SSP) device. A lane number first-in first-out buffer (FIFO) array may operate to order frame processing such that frames associated with an input-output (IO) stream subset of a plurality of SAS-SSP frames received at a plurality of lane receive buffers are processed in an IO stream subset order.

Abstract: An integrated circuit comprising a plurality of processing modules M, S and a network N; RN arranged for providing at least one connection between a first and at least one second module M, S is provided. Said connection supports transactions comprising outgoing messages from the first module to the second modules and return messages from the second modules to the first module. Said integrated circuit comprises at least one dropping means DM for dropping data exchanged by said first and second module M, S. Accordingly, an alternative scheme for transaction completion is provided, where full and immediate transaction completion is merely applied for certain cases. The invention is based on the idea to allow the dropping of data in certain cases.

Abstract: A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the cache lines are split among the towers, unaligned cache access can be performed. Furthermore, power can be conserved because not all the memory towers of the cache unit needs to be activated during some memory access operations.

Abstract: A circuit for driving and controlling a second cache that is incorporated in a processor and comprises a plurality of RAM. The circuit comprises a second-cache control unit 1A and a chip-enable control unit 61. The second-cache control unit 1A receives an access request for an access to the second cache and designates some of the RAMs, which need not operate, in accordance with the type or address of the access request, or both. The chip-enable control unit 61 outputs an intra-macro stop-instructing signal to the RAMs that have been designated by the second-cache control unit 1A.

Abstract: A memory system has a memory controller and a plurality of memories. The plurality of memories are connected via a switch to an end of a bus, which is connected to the memory controller, wherein the plurality of memories are controlled by the switch. By suppressing reflection and loads on the bus, a higher data transmission speed can be obtained.

Abstract: A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are possible. The semiconductor memory device may include an address bank buffer, address buffer, column predecoder and/or a decoder. The semiconductor memory device may begin execution of a write command in a bank in one clock cycle and begin execution of a read command in the following clock cycle, therefore, bus efficiency is increased and/or write-to-read turn around time is reduced.

Abstract: Described herein are a method and system for memory access. As the complexity of digital signal processing applications increases, designs may require multiple memory chips. To optimize the bandwidth of the data being accessed from the memory chips, blocks of data are read alternatively from each memory chip. The size of a block of data is determined by the bit width of a word and the number or memory arrays in a chip.

Abstract: A system and method for updating electronic files and file components are provided. An upgrade client of a remote device receives a delta file block that codes differences between an original and a new version of a file. The upgrade client stores the delta file block in a first memory area. The upgrade client writes an original file block corresponding to the delta file block from an original memory area to a second memory area. A file updating algorithm generates an updated file block in the host device using the received delta file block and the original file block. This updated file block corresponds to the original file block, and is stored in a third memory area. The upgrade client updates the original file block of the remote device by writing the updated file block over the original file block in the original memory area of the remote device.

Abstract: A memory controller is utilized to overcome NAND flash memory's propensity for comprising bad blocks of memory. The memory controller utilizes minimal hardware and is essentially transparent to a device requesting access to the NAND memory. A NAND flash memory device is configured to comprise a set of main blocks of memory and a set of auxiliary blocks of memory. Each block is divided into pages of memory and each page includes metadata. The metadata includes a block status indicator, indicating whether a block is good or bad. When receiving a request to access a page in the NAND flash memory, if the block in which the page resides is good, that block is accessed. If the block is bad, auxiliary memory is searched until a block containing the address of the bad block in its metadata is found. The found block is accessed in lieu of the bad block.

Abstract: Update data to a non-volatile memory may be recorded in at least two interleaving streams such as either into an update block or a scratch pad block depending on a predetermined condition. The scratch pad block is used to buffered update data that are ultimately destined for the update block. Synchronization information about the order recording of updates among the streams is saved with at least one of the streams. This will allow the most recently written version of data that may exist on multiple memory blocks to be identified. In one embodiment, the synchronization information is saved in a first block and is a write pointer that points to the next recording location in a second block. In another embodiment, the synchronization information is a time stamp.

Abstract: A method for transmitting a command signal and an address signal to a rank which is to be accessed includes receiving and buffering the command signal and the address signal, and transmitting the buffered command signal and address signal to the rank, in response to a clock signal and a select signal for accessing rank. Transmitting the buffered command signal and address signal to the rank includes latching the buffered command signal and address signal, in response to the select signal, and transmitting the latched command signal and address signal to the rank, in response to the clock signal. The method and an associated apparatus can selectively transmit a command signal and an address signal to a rank or plurality of memory devices in a memory module, thereby reducing the amount of current consumed by memory modules that are not to be accessed.

Abstract: A memory controller is connected with a first memory requiring refresh and a second memory not requiring refresh, both of which share part of a bus, comprising: a first memory controller that conducts access control and auto-refresh control for the first memory; a second memory controller that conducts access control for the second memory; and an arbiter that adjusts the timing of outputting a signal generated for the first memory and another signal generated for the second memory to a bus, wherein, with a judgment that the signal from the first memory controller is an auto-refresh request, a refresh request signal for the first memory is outputted even while the second memory is being accessed.

Abstract: An apparatus and method for expediting parity checked TLB access operations is described in connection with a multithreaded multiprocessor chip. This parity checking mechanism eliminates the need to read a CAM entry from a TLB during a TLB access by storing the tag parity value in a RAM portion of a TLB, using the CAM key input to generate a tag parity check value for a matched entry, and comparing the generated tag parity check value to the stored tag parity value to determine if there is a parity match or error.

Abstract: A method and circuit to implement a match against range rule functionality. A first rule entry and a second rule entry are stored. The first rule entry includes at least two consecutive identical bits. The first rule entry represents a numerical range. A first field of a binary key is compared with the first rule entry to determine whether any of the bits of the first field are not identical. A logical result of the comparison between the first field and the first rule entry is inverted to generate a first comparison result. A second field of the binary key is compared with a second rule entry to generate a second comparison result. The first comparison result is then logically ANDed with the second comparison result to determine whether the binary key falls within the numerical range represented by the first rule entry and matches the second rule entry.

Abstract: A system includes a processor and a size bounded first-in first-out (FIFO) memory that is connected to the processor and a display is connected to the processor. A managing process to run on the processor to manage the FIFO memory structure. The FIFO memory includes a counter portion and a value portion for each of a tail portion and a head portion, and the managing process is non-blocking. The counter portion is used as a timestamp to maintain FIFO order.

Abstract: A robotic data storage library comprising a virtual port and a method for providing a virtual port for a robotic data storage library are disclosed. The virtual exit port, for example, comprises one or more storage locations of the library that are defined as a virtual port. In one embodiment, for example, the virtual port comprises a virtual exit port for holding a data storage element that is to be exported from the library. In this embodiment, for example, the virtual exit port is defined prior to the library receiving a command to export a data storage element. In another embodiment, the virtual port comprises an entry port, an exit port or an entry/exit port. In yet another embodiment, a method for transferring a data storage element directly between an actual port (entry and/or exit) of a robotic data storage library and another location within the robotic data storage library not defined as the virtual port is disclosed.

Abstract: In information storage systems in which data retrieval requires movement of at least one physical element, a measurable amount of time is required to reposition that physical element in response to each data write or read request. After selecting one or more data requests for dispatch based solely on an approaching or past due time deadline, additional requests are identified for data to be read or written to locations which are in close proximity to previously scheduled requests, previously selected additional requests, or the present position of the moveable physical element, obviating the need to expend the full amount of time required to accelerate the physical element and then decelerate the physical element to position it over the desired area within the information storage system. In this manner, data may be transferred to or retrieved from an information storage system more efficiently with less expenditure of time.

Abstract: This invention provides a specified retention date within a data set that is locked against deletion or modification within a WORM storage implementation. This retention date scheme does not utilize any proprietary application program interfaces (APIs) or protocols, but rather, employs native functionality within conventional file (or other data containers, data sets or block-based logical unit numbers) properties available in commonly used operating systems. In an illustrative embodiment, the retention date/time is calculated by querying the file's last-modified time prior to commit, adding the retention period to this value and thereby deriving a retention date after which the file can be released from WORM. Prior to commit, the computed retention date is stored in the file's “last access time” property/attribute field, or another metadata field that remains permanently associated with the file and that, in being used for retention date, does not interfere with file management in a WORM state.