Abstract: A control apparatus provides a transfer instruction to one of storage apparatus and a cache apparatus, in which relevant data is stored, when receiving an access request from a client apparatus for the data for which the storage location is managed; and the one of the storage apparatus and the cache apparatus receiving the transfer instruction directly returns a reply message, to the client apparatus, having information of the storage location of the data added thereto, which data the access request requests.

Abstract: One embodiment of the present invention is directed to providing a software layer that provides a Content Addressable Storage (CAS) capability in a computer system in which the content units are ultimately stored on a block I/O storage system. An application program may issue access requests to content units referring to them via a content address, and the software layer can convert such access requests to block I/O commands to be processed by the block I/O storage system. Thus, a CAS capability can be provided despite the absence of a storage system that provides such a capability natively.

Abstract: A technique places content, such as data, of one or more data containers on volumes of a striped volume set (SVS). The placement of data across the volumes of the SVS allows specification of a deterministic pattern of fixed length. That is, the pattern determines a placement of data of a data container that is striped among the volumes of the SVS. The placement pattern is such that the stripes are distributed exactly or nearly equally among the volumes and that, within any local span of a small multiple of the number of volumes, the stripes are distributed nearly equally among the volumes. The placement pattern is also substantially similar for a plurality of SVSs having different numbers of volumes.

Abstract: In an exclusive lock management in common to both the In-Band and the Out-of-band, a lock control technique of a storage system capable of removing the factor that may cause the discrepancy in the configuration information in a disk array system is disclosed. In the storage system, a shared memory in a DKC of a storage subsystem has lock management information for uniformly managing the operation authority for the configuration information in the shared memory that is used in common by both the channels of the host terminals and the management client terminals, and a CPU in the DKC gives the operation authority for changing the configuration information to either the host machine or the management client based on the lock management information in the shared memory in response to an access request from the host terminals or the management client terminals.

Abstract: A disk array includes a drive management unit, which is a program for identifying kinds of disk devices and managing different disk devices separately, and a drive management table for storing information to be utilized by the drive management unit. The disk array further includes a program for managing ac-cumulated time of disk devices. The program includes a drive lifetime setting portion for setting lifetimes of drives, a drive start/stop portion for intentionally starting/stopping ATA disk devices, and an operation time measurement portion for measuring accumulated operation time. Since it is necessary to be conscious of difference in reliability and performance among disk devices when forming a RAID, a drive kind notification unit, which is a program for notifying of the kind of a disk device when forming the RAID, is provided.

Abstract: The invention relates to a method for processing data in connection with a portable terminal. In the method, a memory that is external of the terminal is used for storing groups of data, and at least one attribute is determined for said groups of data. Data is stored in the storage of the portable terminal, and at least one group of data can be processed in the portable terminal. In the method, at least one group of data stored in the external memory is selected, and at least one attribute of the selected at least one group of data is transmitted to the portable terminal. The attribute is stored in the portable terminal, wherein when the portable terminal is to process data from the at least one group of data, at least a part of the data from the at least one group of data is transmitted to the storage memory of the portable terminal.

Abstract: A cache memory logically associates a cache line with at least two cache sectors of a cache array wherein different sectors have different output latencies and, for a load hit, selectively enables the cache sectors based on their latency to output the cache line over successive clock cycles. Larger wires having a higher transmission speed are preferably used to output the cache line corresponding to the requested memory block. In the illustrative embodiment the cache is arranged with rows and columns of the cache sectors, and a given cache line is spread across sectors in different columns, with at least one portion of the given cache line being located in a first column having a first latency, and another portion of the given cache line being located in a second column having a second latency greater than the first latency.

Abstract: A circular buffer having an active cache window can be configured to temporarily allocate one or more locations in the active cache as permanent memory locations to eliminate the possibility of overwriting the contents of the permanent memory locations. The cache window can be a subset of the entire circular buffer. If contents within the cache window are identified as persistent data, the locations corresponding to the persistent data can be identified as permanent memory locations. The position of the cache within the circular buffer can be frozen based on the permanent memory locations. A write mask can be used to maintain the contents of the permanent memory locations, while the remainder of the cache is configured as a temporary circular buffer. Operation of the cache returns to the entire circular buffer once the contents of the permanent memory locations no longer need to be maintained.

Abstract: A computer system may include a system memory, an active device configured to access data stored in the system memory, where the active device includes a cache configured to store data accessed by the active device, an address network for conveying address packets between the active device and the system memory, and a data network for conveying data packets between the active device and the system memory. An access right corresponding to a given block allocated in the cache transitions in response to a corresponding data packet being received by the cache. An ownership responsibility for the given block transitions in response to a corresponding address packet being received by the cache. The access right transitions at a different time than the ownership responsibility transitions. The cache is configured to inhibit receipt of the corresponding data packet based on a value of a timestamp associated with the corresponding data packet.

Abstract: A data processing system includes a memory controller of a system memory that receives first and second castout operations both specifying a same address. In response to receiving said first and second castout operations, the memory controller performs a single update to the system memory.

Abstract: Techniques for pushing data to multiple processors in a clean state.

Abstract: Provided are a method, system, and article of manufacture, wherein a controller receives a request from one of a plurality of hosts. The controller determines whether a primary storage control unit coupled to the controller is operational. A response is generated by accessing the primary storage control unit, in response to determining that the primary storage control unit is operational. The response is generated by accessing a secondary storage control unit, in response to determining that the primary storage control unit is not operational, wherein data is replicated synchronously from the primary storage control unit to the secondary storage control unit.

Abstract: A multi-processor, multi-cache system has filter pipes that store entries for request messages sent to a central coherency controller. The central coherency controller orders requests from filter pipes using coherency rules but does not track completion of invalidations. The central coherency controller reads snoop tags to identify sharing caches having a copy of a requested cache line. The central coherency controller sends an ordering message to the requesting filter pipe. The ordering message has an invalidate count indicating the number of sharing caches. Each sharing cache receives an invalidation message from the central coherency controller, invalidates its copy of the cache line, and sends an invalidation acknowledgement message to the requesting filter pipe. The requesting filter pipe decrements the invalidate count until all sharing caches have acknowledged invalidation.

Abstract: In a shared memory system, ineffective write operations (“dead stores”) can be handled in a manner to reduce unnecessary consumption of resources. In a shared memory system, when a non-owning processing unit requests data from a shared memory location owned by another processing unit, the memory controller for the shared memory requests a most current copy of the data from the owner processing unit. Instead of the owner processing unit reflexively sending its data to the memory controller, the owner processing unit determines whether the data has been changed, and, if it has not changed, transmits indication of such to the memory controller. Since the data has not changed, then the data at the shared memory location is proper and can be sent to satisfy the requesting processing unit.

Abstract: A protected configuration space is implemented as at least one range of memory addresses that are mapped to logic external to system memory. The memory addresses access logic that performs control and status operations pertaining to a protected operating environment. Some of the addresses may access protected configuration registers. Commands having destination addresses within the protected configuration space may not be completed if the commands are not issued by a processor, or if the commands are not part of a group of one or more designated protected commands. A separately addressable non-protected configuration space may also be implemented, accessible by processors, non-processors and/or non-protected commands.

Abstract: A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.

Abstract: The present inveniton provides a method for improving data reading performance and a controller performing the same. After a read request is sent to a storage device, the processing time of the read request starts to be counted. If the read request does not successfully read data in a predetermined time period, redundant data identical to the read data is generated in order to achieve the action of reading data. The read request process is still ongoing while generating the redundant data. When the data is read or generated successfully by either of the read request process or the redundant data generating process, the data is returned to a request unit.

Abstract: Embodiments of the present invention are directed to systems and methods of controlling data transfer between a host system and a plurality of storage devices. One embodiment is directed to a virtualization controller for controlling data transfer between a host system and a plurality of storage devices. The virtualization controller comprises a plurality of first ports for connection with the plurality of storage devices each having a storage area to store data; a second port for connection with the host system; a processor; and a memory configured to store volume mapping information which correlates first identification information used by the host system to access a first storage area in one of the storage devices, with second identification information for identifying the first storage area, the correlation being used by the processor to access the first storage area.

Abstract: In an embodiment, a memory scheduler is provided to process memory requests. The memory scheduler may comprise: a plurality of arbitrators that each select memory requests according to age of the memory requests and whether resources are available for the memory requests; and a second-level arbitrator that selects, for an arbitration round, a series of memory requests made available by the plurality of arbitrators, wherein the second-level arbitrator begins the arbitration round by selecting a memory request from a least recently used (LRU) arbitrator of the plurality of arbitrators.

Abstract: A page replacement method is provided. The page replacement method includes (a) establishing a first page list in which a plurality of pages in a main memory are listed in an order that they have been used, (b) establishing a second page list in which some of the pages in the main memory whose images are stored in a storage medium are listed in an order that they have been used, and (c) storing data downloaded from the storage medium in the pages included in the second page list in an order opposite to the order that the corresponding pages are listed in the second page list.

Abstract: A system, to locate at least two storage devices from among a plurality of storage devices, receives a request for the data item. The request includes a data identifier for the data item. Next, the system generates a start number and a step number based on the data identifier. The system locates a first storage device utilizing the start number and, if the first storage device is available, the system reads the data item from the first storage device. However, if the first storage device is unavailable, the system utilizes the step number and the start number to compute a backup number that is utilized to locate a second storage device. If the second storage device is available, the system reads the data item from the second storage device.

Abstract: A disk array having an internal mirror architecture may include: a plurality of disk drives configured to provide a primary logical storage device (LDEV), a first instance of an internally-mirroring secondary LDEV and a second instance of an internally-mirroring secondary LDEV.

Abstract: A framework for taking shadow copies and performing backups in systems that may have data spread across multiple machines. A requester communicates names to a primary coordinator and requests the creation of shadow copies of all the volumes associated with the names. The primary coordinator communicates with one or more writers and one or more secondary coordinators to create the shadow copies of the volumes. The primary and one or more secondary coordinators create shadow copies of one or more of the volumes that reside on the machines upon which they execute. After the shadow copies of the volumes have been created, the requester may obtain data from the shadow copies and create a consistent backup.

Abstract: A method of incremental backup of a storage device includes reading descriptors of logical storage units of the storage device; comparing the descriptors of the logical storage units of the storage device with descriptors of archived logical storage units; for logical storage units of the storage device whose descriptors are not identical to the descriptors of the archived logical storage units, backing up contents of physical storage units that correspond to those logical storage units of the storage device; and, for logical storage units of the storage device whose descriptors are identical, performing a comparison step to check if these logical storage units need to be backed up. The logical storage units can be files. The comparison step can be, e.g., (1) bit-wise comparison of the logical blocks, (2) comparing control sums of the logical blocks, and (3) comparing log files relating to the logical storage units The physical storage units can be blocks. The descriptors can be, e.g.

Abstract: A storage device is capable of sequentially inputting a command, which includes address information and attached information, from an information processor through an input/output unit. The storage device includes a storage unit for storing data; an extractor for extracting the address information and the attached information from an input command inputted through the input/output unit; a generator for, in response to input of the input command, generating transition information that transitions according to rules using an initial value; a comparator for determining whether the attached information and the transition information agree with each other; and an output controller for, only when the attached information and the transition information agree with each other, outputting storage data out of the data, which corresponds to the address information extracted by the extractor, through the input/output unit.

Abstract: Embodiments of the invention provide a computer readable medium having computer executable instructions for synchronizing files between at least two portable media devices. A connection is established between one of at least two portable media devices and a portable synchronization device. A synchronization manager is initiated comprising predetermined instructions for synchronizing portable media devices. Based upon the instructions of the synchronization manager, and without requesting real-time user input, a determination is made whether to copy a file on the one of the at least two portable media devices. The file is ultimately transferred to another of the at least two portable media devices if the synchronization manager determines that the file should be transferred. A method is also provided comprising these steps. A portable media synchronization device is also provided for synchronizing at least two portable media devices.

Abstract: A method and apparatus are provided for interfacing with a synchronous dynamic memory in which memory commands are provided to the memory. The memory is accessed in response to the memory commands. Read data is captured in a data capture circuit having a delay setting. The delay setting is updated in response to detection of a period of read inactivity of the memory.

Abstract: A reproduction apparatus capable of saving power consumption, wherein starting time data of a hard disk drive (HDD), is detected every time the HDD starts and, based on threshold value data generated by using a value obtained by adding standard deviation data to average value data of the starting time data, a timing of activating the HDD and starting an operation of writing song data read from the HDD to an SDRAM is determined.

Abstract: A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled to the processor bus is a memory hub controller coupled to a memory hub of at least one memory module having a plurality of memory devices coupled to the memory hub. The memory hub is coupled to the memory hub controller through a downstream bus and an upstream bus. The downstream bus has a width of M bits, and the upstream bus has a width of N bits. Although the sum of M and N is fixed, the individual values of M and N can be adjusted during the operation of the processor-based system to adjust the bandwidths of the downstream bus and the upstream bus.

Abstract: Provided are a method, system, network processor, network device, and article of manufacture for enqueueing entries in a packet queue referencing packets. When adding a packet to a first memory area, an entry is written to a packet queue in a second memory area referencing the added packet. A pointer is read referencing one end of the packet queue from a queue descriptor in the second memory area into a third memory area in one read operation. The pointer is updated in the third memory area to point to the added entry in the packet queue and the updated pointer in the third memory area is written to the queue descriptor in the second memory area in one write operation.

Abstract: Described herein are exemplary storage network architectures and methods for block size allocation in copy operations. A copy operation from a first storage cell to a second storage cell is initiated. The copy operation initially utilizes a first write block size. The write block size is changed to utilize a second write block size, different from the first write block size, and a performance parameter is measured at the second write block size. The second write block size is maintained if the performance parameter exceeds a threshold.

Abstract: A burden placed on an administrator in creating a volume is reduced. An evaluation hint value and a performance hint value are employed as hint values for each hint. The evaluation hint value is determined by the administrator considering a service usage and the like of the service server 1 to which the volume is allocated. The performance hint value is used to determine a performance and a setting of the volume to be created in the storage system 3. The management server 2 has a conversion table indicating a correspondence between the evaluation hint value defined considering the hardware configuration and the performance hint value, with respect to each storage system 3. The management server 2 converts the evaluation hint value designated by the administrator to a performance hint value, by use of the conversion table associated with the storage system to which the volume is to be created, and the management server creates the volume in the storage system 3 according to the performance value.

Abstract: The present invention provides a method for copying data through a virtualized storage system using distributed table driven (I/O) mapping. In a system having a virtual disk (the “original disk”), a persistent mapping table for this virtual disk exists on a controller, and volatile copies of some or all entries in this mapping table are distributed to one or more more mapping agents. The method of the present invention creates a new virtual disk mapping table that has the exact same entries as the mapping table as the original virtual disk. The new snapshot disk then shares the same storage as the original disk, so it is space efficient. Furthermore, creating new snapshot disk involves only copying the contents of the mapping table, not moving data, so the creation is fast. In order to allow multiple virtual disks to share storage segments, writes to either the original virtual disk or the snapshot copy cannot be seen by the other.

Abstract: A system for optimizing translation lookaside buffer entries is provided. The system includes a translation lookaside buffer configured to store a number of entries, each entry having a size attribute, each entry referencing a corresponding page, and control logic configured to modify the size attribute of an existing entry in the translation lookaside buffer if a new page is contiguous with an existing page referenced by the existing entry. The existing entry after having had its size attribute modified references a consolidated page comprising the existing page and the new page.

Abstract: By the same method as that of making data access to a data storage area in an online state, it is performed to access a data storage area other than the data storage area. A plurality of logical volumes carried by a disk array apparatus includes an online volume that is in an online state to a host and an offline state that is in an offline state to the host. The host transmits an access command including target information designating a target volume to the disk array apparatus as an access command to a starting volume other than the target volume. The disk array apparatus receives the access command to the starting volume and offers the data access to the target volume on the basis of the target information carried by that access command to the host.

Abstract: A method for determining a stack distance including spatial locality for running software. The method may include receiving a plurality of memory references each including a corresponding address. The method may also include performing a merge function on each address corresponding to each received memory reference to generate a modified version of each corresponding address, and then performing a first hash function on the modified version of each corresponding address. In addition, the method may include performing a filter function on each address corresponding to each received memory reference. The method may further include selectively storing an indication representative of the modified version of each corresponding address in a hash table dependent upon results of the first hash function and the filter function. A stack distance may then be determined based upon contents of the hash table.

Abstract: A configuration memory space is scanned to locate an identification register whose value matches a predetermined value. The identification register identifies the location of a structure within the configuration space. The location of the beginning of the structure is used along with a predetermined (known) offset to determine the address of a desired configuration register.

Abstract: A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, one vector register is loaded with the “add-in” values, and another vector register is loaded with address values of “add to” elements to be gathered from memory into a third vector register. If the vector of address values has a plurality of elements that point to the same memory address, the algorithm should add all the “add in” values from elements corresponding to the elements having the duplicated addresses. An indirectly addressed load performs the “gather” operation to load the “add to” values. A vector add operation then adds corresponding elements from the “add in” vector to the “add to” vector. An indirectly addressed store then performs the “scatter” operation to store the results.

Abstract: Apparatus and method for dispatching a very long instruction word (VLIW) instruction having a variable length are provided. The apparatus for dispatching a VLIW instruction includes a packet buffer for storing at least one or more VLIW instructions, and a decoding unit configured to constitute a VLIW instruction to be currently executed among the VLIW instructions stored in the packet buffer and decode predetermined bits of each sub-instruction contained in the VLIW instruction. The apparatus dispatches a corresponding sub-instruction to an FU which corresponds to each sub-instruction, based on the results of decoding performed in the decoding unit, position information on the sub-instructions that are placed on the packet buffer, and position information on the sub-instructions that are placed in the current VLIW instruction. Sub-instructions can be effectively dispatched to corresponding FUs using simple decoding logic even in a case where the length of the VLIW instruction is not fixed.

Abstract: A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced.

Abstract: In one embodiment, a state machine receives a plurality of instructions from an instruction register to be processed by a digital signal processor. After receiving a single RTI, the state machine loads each of the plurality of instructions one at time and determines the validity of each instruction. If the instruction is valid, the state machine transfers the instruction to the decoder. If the instruction is invalid or if a no-operation instruction is present, the state machine discards the instruction and immediately loads the next instruction.

Abstract: A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.

Abstract: A processor buffers asynchronous threads. Current instructions requiring operations provided by a plurality of execution units are divided into phases, each phase having at least one math operation and at least one texture cache access operation. Instructions within each phase are qualified and prioritized, with texture cache access operations in a subsequent phase not qualified until all of the texture cache access operations in a current phase have completed. The instructions may be qualified based on the status of the execution unit needed to execute one or more of the instructions. The instructions may also be qualified based on an age of each instruction, a divergence potential, locality, thread diversity, and resource requirements. Qualified instructions may be prioritized based on execution units needed to execute current instructions and the execution units in use. One or more of the prioritized instructions is issued per cycle to the plurality of execution units.

Abstract: A method and apparatus are provided for entering and exiting multiple threads within a multithreaded processor. A state machine is maintained to indicate a respective status of an associated thread of multiple threads being executed within a multithreaded processor. A change of status for a first thread within the multithreaded processor is detected and, responsive to the change of status for the first thread within the multithreaded processor, a partitioning scheme for the functional unit is altered to service a second thread, but not the first thread, within the multithreaded processor when the change of the status of the first thread comprises a transition from an active state to an inactive state.

Abstract: One embodiment of the present invention provides a system that predicts a result produced by a section of code in order to support speculative program execution. The system begins by executing the section of code using a head thread in order to produce a result. Before the head thread produces the result, the system generates a predicted result to be used in place of the result. Next, the system allows a speculative thread to use the predicted result in speculatively executing subsequent code that follows the section of code. After the head thread finishes executing the section of code, the system determines if a difference between the predicted result and the result generated by the head thread has affected execution of the speculative thread. If so, the system executes the subsequent code again using the result generated by the head thread. If not, the system performs a join operation to merge state associated with the speculative thread with state associated with the head thread.

Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

Abstract: A processor is provided with a address calculation unit so as to generate addresses for elements of object oriented data structures in one processor clock cycle.

Abstract: A context switching system for a multi-thread execution pipeline loop having a pipeline latency and a method of operation thereof. In one embodiment, the context switching system includes a context switch requesting subsystem configured to: (1) detect a device request from a thread executing within the multi-thread execution pipeline loop for access to a device having a fulfillment latency exceeding the pipeline latency, and (2) generate a context switch request for the thread. The context switching system further includes a context controller subsystem configured to receive the context switch request and prevent the thread from executing until the device request is fulfilled.

Abstract: A method for optimizing loop control of microcoded instructions includes identifying an instruction as a repetitive microcode instruction such as a move string instruction, for example, having a repeat prefix. The repetitive microcode instruction may include a loop of microcode instructions forming a microcode sequence. The microcode sequence is stored within a storage of a microcode unit. The method also includes storing a loop count value associated with the repetitive microcode instruction to a sequence control unit of the microcode unit. The method further includes determining a number of iterations to issue the microcode sequence for execution by an instruction pipeline based upon the loop count value. In response to receiving the repetitive microcode instruction, the method includes continuously issuing the microcode sequence for the number of iterations.

Abstract: A computer system having a computer main body and a monitor displaying a video signal from the computer main body and a control method thereof. The control method includes storing a display information of the video signal displayed on the monitor based on EDID supplied from the monitor in the computer main body; determining whether the display information of an input video signal transmitted from the computer main body to the monitor is suitable for the EDID of the monitor; displaying the input video signal if the display information of the input video signal is suitable for the EDID and supplying an error signal to the computer main body if the display information of the input video signal is not suitable for the EDID; and processing the input video signal according to the display information stored in the computer main body and supplying it to the monitor if the error signal is supplied to the computer main body.