Abstract: The present invention relates to a method for synchronizing a number of digital clocks to a synchronizing signal, said method comprising generating centrally a reference clock, synthesizing said digital clocks from said reference clock using a clock multiplier, respectively, resetting said clock multiplier in response to said synchronizing signal, and masking an output signal of said clock multiplier during settling time of said clock multiplier.

Abstract: An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a soft reset signal for resetting the second circuitry, the integrated circuit further including: a soft reset hold circuit clocked in the first clock environment connected to receive the soft reset signal and to generate an output reset signal in an asserted state; and a synchronizer clocked in the second clock environment connected to receive the output reset signal and to generate a retimed reset signal in an asserted state after a predetermined period, wherein the retimed reset signal is fed back to the soft reset hold circuit to cause the output reset signal to adopt a deasserted state at the end of said predetermined period.

Abstract: Precise timing control across multiple standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL within each chassis, and by providing these control signals to other chassis. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. A start sequence allows all PXI expansion cards in the test system to start at the same time. A MATCH line enables pincard modules to check for expected DUT outputs and either continue execution of their local test programs or loop back and repeat a section of the local test program in accordance with the result of the DUT output check. An End Of Test (EOT) line enables any one pincard module to abruptly end the local test programs running in all other pincard modules if an error is detected by the local test program in the pincard module.

Abstract: A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided.

Abstract: The invention provides for the arrangement and management of timing of various domains on a large integrated circuit which introduces a phase offset between clock domains of neighboring cells to create a wavefront clock which propagates through the circuit at the same speed data propagates though the circuit. The cells of the integrated circuit are wavefront clock synchronized in that the phase offset introduced in a particular cell's clock is such that the arrival of a skewed clock and propagation delayed data from that cell's neighbor is synchronized with that particular cell's own clock. Wavefront clock synchronization mitigates at least some of the problems of clock skew and the associated effects of slowing data propagation and reduction of clock frequencies associated with large surface integrated circuits utilizing synchronized clock domains.

Abstract: A signal sampler and method for high-speed input sampling of a signal are disclosed. A first sampler samples a data signal at a rising edge of a clock signal and generates a first sampled signal. A second sampler samples the data signal at a falling edge of an inverted clock signal and generates a second sampled signal. The first and second sampled signals may be combined to determine the next signal sampler output. An evaluation may include asserting the output signal if the first and second sampled signals are asserted, negating the output signal if the first and second sampled signal are negated, and toggling the output signal if the first and second sampled signals are in opposite logic states. The signal sampler and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.

Abstract: Synchronization is attained between a source clock domain and a target clock domain of arbitrary frequency ratios and each of which periodically has edges nominally aligned to edges of a reference clock signal, marked by the assertion of a periodic sync signal. The periodic sync signal, synchronous with the source clock, is used to output to an unload pointer counter in the target clock domain the deassertion of a reset signal prior to the nominal alignment of the source clock and the target clock for sampling on the nominally aligned target clock edge. The deassertion of the reset signal is output to a load pointer in the source clock domain coincident with the nominally-aligned edges of the source clock and the target clock. Both loading and unloading start based on the reset deassertion being sampled on the nominally aligned edges in the appropriate clock domain.

Abstract: The subject invention relates to systems and methods for automatic recovery from errors in a computing environment. A system is provided to facilitate failure recovery in the computing system. The system includes at least one driver component that enumerates at least one layer of a driver stack. A module associated with the driver component requests re-enumeration of the driver stack upon detection of an error in the computing system. When an error is detected by a driver or operating system component, a protocol can be established whereby a new copy of the driver's stack or system resources is re-enumerated in parallel to existing resources that may be in an unknown or error state. The new copy of the stack may allow the driver to become operational in lieu of the previous stack which can be reclaimed for other system uses over time.

Abstract: The present invention discloses a method for backup of Home Location Register (HLR), comprising: configuring a universal HLR as a disaster recovery center HLR which is to backup many HLRs, establishing network connection and loading user data to disaster recovery center through uniform text files; during operating, each active HLR will synchronize the user's data to the disaster recovery center; and a signaling will be forwarded to disaster recovery center to process after active HLR fails. So the present invention can realize service backup compatibility with equipment by different manufacturers, decrease cost, and be realized and managed easily, therefore the present invention has solved problems of characteristic service data backup in different HLRs.

Abstract: Redundancy in a read only memory (ROM) embedded dynamic random access memory (DRAM) is accomplished by programming redundancy elements such as antifuses or registers with ROM data which is read instead of erroneous data. Multiple identical arrays of ROM bits can also be used for redundancy.

Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register.

Abstract: According to one embodiment, a method comprises assigning a first processor of a multi-processor system a role of spare processor for at least a second processor, and responsive to detecting loss of lockstep (LOL) for any of the at least a second processor, the first processor replaces the processor for which the LOL is detected. The method further comprises reestablishing lockstep for the processor for which the LOL is detected, and assigning the processor having its lockstep reestablished the role of spare processor for at least the first processor.

Abstract: A distributed software application comprises a plurality of software components within a plurality of executables. A manager component for the distributed software application performs a recovery of two or more software components, of the plurality of software components, in an ordered sequence based on one or more dependency relationships among the plurality of software components.

Abstract: An information processing apparatus having a resume function which can maintain the security even when a plurality of users commonly use the apparatus. A work state at a power-off time of the apparatus is preserved together with a work state name including a user's ID in a different area in a plurality of preservation areas for resume function on a main memory for each user. When a power source is again turned on, data in the preservation area corresponding to the user's ID is used to reproduce the work state of the user at the power-off time. The work preservation areas can be provided on a file server apparatus in a network not needing battery back-up. When the information processing apparatus is used, a work state at a power-off time can be independently preserved and reproduced for each user.

Abstract: A method and apparatus for generating processor test programs using a formal description of the processor's instruction set. An instruction set for a processor is formally described using a language such as ISDL. The formal description of the instruction set identifies certain characteristics of the instructions making up the instruction set. The formal description is combined with a test specification that describes desired properties of a test program by formally specifying test sequences that are to be applied to instructions having particular characteristics. A test program is generated by applying the formal test specification to the formal description of the instruction set including test sequences applicable to instructions having the particular characteristics.

Abstract: In some embodiments, a receiver can receive from an interconnect information packets and idle packets, where one or more of the idle packets includes a test pattern. A condition detector can detect a condition of the interconnect in response to the test pattern. Other embodiments are described and claimed.

Abstract: A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the cache memory, the BIST being operable to determine whether any of the subdivisions is defective. When it is determined that one of the subdivisions of the cache memory determined defective by the BIST is non-repairable, the SE logically deletes the defective subdivision from the system configuration, and the SE is operable to permit the processor to operate without the logically deleted subdivision. The SE is further operable to determine that the processor is defective when a number of the defective subdivisions exceeds a threshold.

Abstract: A data transfer device comprises a unit for collecting data of a control state by monitoring the control state of a circuit which controls communications protocols within the local device, and a unit for detecting an abnormal state of a data transfer based on the collected state data.

Abstract: A test execution system has a central repository that contains a management unit, available test suites and a single test execution harness. Using the management unit, a system administrator establishes active versions of the various test suites, and their individual configurations. End users install clients of the central repository, using a system-provided installer program. In the client, an execution script is created, which downloads the harness and a local configuration file. Then, when the harness is executed at the client, it loads with all designated test suites already installed, configured and ready for execution. The client always has the most current versions of all test suites. All necessary information is obtained from a single central location.

Abstract: In one aspect, a value of a variable shared by multiple threads for executing the program code is stored in a thread-local variable. A data race condition is detected based on a comparison of values of the shared variable and the thread-local variable. Detection of the data race condition is reported. In another aspect, a machine-readable instruction to store in a thread-local variable a value of a variable shared by multiple threads for executing the program code is generated. A machine-readable instruction to detect a data race condition based on a comparison of values of the shared variable and the thread-local variable is generated. The machine-readable instructions are stored in a machine-readable medium.

Abstract: The present invention is a method and system for providing a complete validation of an initiator and target within bus architecture. A target's behavior may be controlled by an initiator. Control of the target may be through execution of initiator commands including vendor unique commands relating to desired characteristics for testing. The initiator's response to the target's behavior may be verified due to the handshaking communication protocol between a target and initiator. Additionally, by altering the behavior of the target to test initiator response, a target's behavior is also validated.

Abstract: One embodiment of a method may include, in response, at least in part, to one or more received frames, generating an interrupt and preventing transmission of one or more other frames. The one or more received frames may indicate, at least in part, an error condition or a commencement of a data transfer. The method of this embodiment also may include, in response, at least in part, to the interrupt, executing one or more instructions. The one or more instructions, when executed, may optionally result in deleting the one or more other frames, and if the one or more received frames indicate, at least in part, the error condition, commencing recovery from the error condition. If the one or more received frames indicate, at least in part, the commencement of the data transfer, the method of the embodiment may include storing data associated with the data transfer.

Abstract: A communications processing section of a management apparatus sends a request for malfunction information via the Internet to one or more electrical devices being managed. A database manager of the management apparatus refers to data stored in a database and updates the record of the electrical device therein. A timing control section of the management apparatus carries out control so that the number of electrical devices requested upon by the management apparatus does not exceed a predetermined value. In this way, despite the management apparatus centrally manages the malfunction information of each electrical device, a peak quantity of the malfunction information received by the management apparatus can be suppressed and the workload on the management apparatus can be relieved, as opposed to the case where each electrical device sends the malfunction information at its own timing.

Abstract: In a server cluster, a system and method is provided for mitigating redundant resource failure notifications and other problems resulting from late handling of messages. Traditional resource management can result in the generation of redundant resource failure notifications that trigger unnecessary recovery actions, or cause other cluster problems such as performing an action that has previously been handled as part of failure recovery. The present invention tracks resource failures and eliminates recovery actions for redundant resource failure notifications. An incarnation number is passed to a resource each time it is called, and is incremented whenever a resource failure notification is delivered. Failure notifications having an incarnation number lower than the current incarnation number are discarded.

Abstract: In accordance with a specific aspect of the present disclosure, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. In addition, primary elementary stream data can be handled by separate primary elementary stream parsers based upon the packet identifier of the primary elementary stream. Video packets can be parsed based upon stream identifier values. Specific packets of data are stored in one or more system memory or video memory buffers by an output controller based upon allocation table information. Private data associated with specific elementary streams or packet adaptation fields are repacketized and written to an output buffer location.

Abstract: An interleaving/deinterleaving method and apparatus may interleave/deinterleave first data to produce second data so that the arrangement of data elements of the second data is different from that of the first data. To accomplish this, word data that are part of the first data are read from a data storage section and a data element to be processed is selected from the word data for output. The operations of reading word data and selecting data elements of the word data to output are repeated, and a sequence of data elements to be processed at the time of repetition is determined in accordance with the arrangement of the data elements of the second data.

Abstract: The present invention is directed to a data recording method of notifying degree of deterioration of recording medium thus to perform stable recording operation. Even in the case where uncorrectable address read error does not exist, deterioration information is displayed in accordance with generated and stored deterioration information. Whether or not address read error of ATIP is detected over successive two frames or more, or whether or not four errors or more are detected on the average at 75 frames is discriminated. In the case where error detecting state is adapted to affirmative discrimination condition, warning is displayed. In the case where 200 errors or more detected from deterioration information generated in processing with respect to random missing with respect to written data exist on the average with respect to successive 750 frames, or in the case where one error or more detected in processing with respect to random missing exist, disc deterioration warning display is similarly performed.

Abstract: A loopback test to test a communication link for a layered interface where in a master agent programs the electrical parameters for the slave agent, such as, the offset, timing, and current compensation with a loopback control register. The slave and master agent to support an entry into the loopback test based on detection of a header within a packet. The slave and master agent to support exit out of the loopback test based on whether the loop count is finite.

Abstract: Test functions are expanded by adopting a self test part, and circuit scale is reduced by adding the self test part. A semiconductor integrated circuit includes a memory that includes plural memory banks and is accessed by specifying a bank address, an X address, and a Y address, and a self-test part that tests the memory in response to commands. The self-test part has an address counter covering plural addressing modes that are different in the updating of X addresses, Y addresses, and bank addresses. A variety of addressing modes provided expand BIST-based test functions.

Abstract: A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in each of its branches and a second signal distribution tree that includes a second delay line in each of its branches, thereby producing respective first and second delayed clock signals. A test signal generator generates a plurality of test signals that may simulate memory command or address signal. A multiplexer couples the test signals to first and second inputs of a transmitter in a normal test mode but to only the first input in a special test mode. The transmitter outputs the signal applied to its first input responsive to the first delayed clock signal and it outputs the signal applied to its second input responsive to the second delayed clock signal.

Abstract: Methods of testing a semiconductor device are provided in which a test pattern is generated for the semiconductor device that is based on the semiconductor device operating under a first CAS latency number. Then, the semiconductor device is tested using this test pattern where, at least part of the test is performed when the semiconductor device is operating under a second CAS latency number that is different from the first CAS latency number. This may be accomplished, for example, by increasing the number of clock cycles in the timing clock signal during a CAS latency-variable interval in situations where the CAS latency is changed after generation of the test pattern.

Abstract: A data processing apparatus capable of preventing contention of memory access between the HARQ synthesis and rate dematching in the HARQ processing using two or more single-port memories is provided. A buffer includes two physical memories. One of the physical memories is used as an even address memory, and the other is used as an odd address memory. With respect to access to the buffer conducted by the HARQ synthesis and rate dematching, access control is conducted so as to make the rate dematching access the odd address memory when the HARQ synthesis accesses the even address memory.

Abstract: Various methods and systems for implementing Reed Solomon multiplication sections from exclusive-OR (XOR) logic are disclosed. For example, a system includes a Reed Solomon multiplication section, which includes XOR-based logic. The XOR-based logic includes an input, an output, and one or more XOR gates. A symbol X is received at the input of the XOR-based logic. The one or more XOR gates are coupled to generate a product of a power of ? and X at the output, wherein ? is a root of a primitive polynomial of a Reed Solomon code. Such a Reed Solomon multiplication section, which can include one or more multipliers implemented using XOR-based logic, can be included in a Reed Solomon encoder or decoder.

Abstract: The invention relates to a method for detecting addressing errors in control devices of motor vehicles, whereby test data are input into all addressable memory cells by means of a present model, then read out and compared with the test data.

Abstract: Disposed on both sides of a parity cell array are a first regular cell array and a sub parity generation circuit therefor, and a second regular cell array and a sub parity generation circuit therefor. The sub parity generation circuit generates sub parity data according to read data that are simultaneously read from the first and second regular cell arrays. A main parity generation circuit generates according to sub parity data parity data in common to the regular cell arrays, is not disposed in a distributed manner but disposed corresponding to the parity cell array. Thus, the layout design, layout verification, and so forth of a semiconductor memory can be prevented from being complexed. As a result, the parity generation circuit can be optimally laid out, decreasing the development time and defect analysis time for the semiconductor memory can be decreased.

Abstract: A mediator having at least a ranking component, a listening component, and a control component, selectively controls a group of devices from a plurality of network devices in a network environment to reproduce multimedia content. The mediator correlates the multimedia content with the plurality of network devices. The listening component collects data about the network environment to enhance a user's experience with the multimedia content. The mediator utilizes the network environment data and the correlation of the multimedia content and the plurality of network devices to automatically select the group devices from the plurality of network devices that maximize a user's viewing or listening pleasure when reproducing the multimedia content on the group of devices.

Abstract: A system and method for providing a document object model to represent components of related entities for in-memory representations. The system and method provide for tangled data structures that are more readily parsed than conventional object models. Data is represented as items, relations and attributes. Items are described in terms of relations and attributes. Relations represent item associations. While attributes, represent other information about items. The present invention solves the problems associated with representing an XML document as a DOM component. The DOM component does not allow for relations of text with elements.

Abstract: According to the invention, this invention redefines the concept of a template as a set of template attributes, such as font types and color schemes, that are accessed by document-generating applications to provide uniform functionality across an organization. The template attributes are stored and distributed throughout an organization in lieu of full document templates in order to reduce storage and transmission bandwidth requirements. The template attributes are distributed from a global server to regional servers and then to user workstations to facilitate propagation and enforcement of organization-wide document formatting protocols.

Abstract: Some embodiments of the invention provide a computer system that includes a media server, a media client, and a media-server interface. The media server application produces media data, where the media data has a plurality of segments. For example, in some embodiments, the media data is a movie with video and audio components. In this example, the segments of the movie can be specified in two groups, where one group includes the frames of video in the movie and the other group includes the seconds of audio in the movie. The media client application is typically an application that needs to process the media data of the media server application without the need to have any familiarity with the implementation of the media server application. The media-server interface directs the server application to successively generate individual segments of the media data and to store each generated segment in a location that is accessible by the media client.

Abstract: Methods, systems, and computer program products, for using a web browser to view stored data over the World Wide Web, where the data is stored in a format normally incompatible with such viewing. A client computer processes a view descriptor and a general view class to generate a specific view class, or template, and a query. The specific view class is used as a template to display data the client receives from a data server after submitting the generated query to the data server. The result of using a specific view class as a template for the data is that the data is output in Hypertext Markup Language, so as to be easily displayable on a web browser. View classes and view descriptors may be developed using existing Web development tools such as Extensible Style Language and Extensible Markup Language.

Abstract: The present invention provides a way to validate data entry at both the client and the server with minimal engineering effort. The system allows the specification of data validation rules for a form on a server. The system provides a version of the rules with the form to the client computer. The system also executes the rules on the server for further validation. The system may translate the rules into JavaScript data structures, passed as the version to the client for client-side validation. Because the rules for the form are specific only once, there is no possibility of the rules becoming out of sync between the form on the client and on the server.

Abstract: Methods and systems provide for imposing structure onto a freeform or irregular table so that a subsequent consuming application may use the table, including presentation of the table and location of the data in the table. A generic grid structure is created having a plurality of uniformly-shaped cells such that if the generic grid is overlaid onto the irregular table, each cell within the irregular table may be located based on its position relative to the uniform cells or grids. The grid structure creates a coordinate system for defining the shape of the irregular table, for defining locations and shapes of cells comprising the irregular table and for addressing the locations of data contained in the irregular table.

Abstract: An apparatus for annotating a document is presented. The invention allows the addition of verbal annotations to a digital document such as a movie script, book, or any other type of document. In an embodiment, the invention the stores audio comments in data storage as an annotation linked to a location in the document being annotated. The invention may be implemented in a variety of smart mobile devices, including automotive entertainment systems, cell phones, and other portable computing devices.

Abstract: One or more embodiments of the invention enable a user to establish, configure, and associate one or more output devices with a file. Prior art applications provide for configuring an output device (e.g., a printer) on an application wide basis. Users often format a file or document based on an output device. Consequently, it is useful to associate an output device with a particular file or information. In graphics programs, a user may define a drawing (referred to as a model) with various layouts or views of the drawing. Each layout or view may be formatted for a particular output device. Consequently, one or more embodiments of the invention associate one or more files, layouts, or views with one or more output devices. Additionally, each output device may be configured for a particular file, layout, or view. One or more embodiments of the invention provide for the association of one or more output device configurations with one or more files, layouts, or views.

Abstract: An image forming device for dividing a continuous document without the concept of pages, such as an HTML document, into pages, the device being capable of responding to a user's various needs in connection with page dividing. A page dividing processor (304) is provided with a plurality of page dividing algorithms which differ in terms of treatment of a document element placed across a page boundary. When a user inputs a page dividing policy using a user interface (301), a dividing algorithm designating section (305) specifies a page dividing algorithm corresponding to the policy, and notifies the page dividing processor (304) of the algorithm. The page dividing processor (304) divides an HTML document into pages according to the algorithm.

Abstract: Modular content framework and document format methods and systems are described. The described framework and format define a set of building blocks for composing, packaging, distributing, and rendering document-centered content. These building blocks define a platform-independent framework for document formats that enable software and hardware systems to generate, exchange, and display documents reliably and consistently. The framework and format have been designed in a flexible and extensible fashion. In addition to this general framework and format, a particular format, known as the reach package format, is defined using the general framework. The reach package format is a format for storing paginated documents. The contents of a reach package can be displayed or printed with full fidelity among devices and applications in a wide range of environments and across a wide range of scenarios.

Abstract: A spell checker based on the noisy channel model has a source model and an error model. The source model determines how likely a word w in a dictionary is to have been generated. The error model determines how likely the word w was to have been incorrectly entered as the string s (e.g., mistyped or incorrectly interpreted by a speech recognition system) according to the probabilities of string-to-string edits. The string-to-string edits allow conversion of one arbitrary length character sequence to another arbitrary length character sequence.

Abstract: The names of contacts are stored as characters. Each character may include one or more phonic codes that are encoded into the character. A smart filter decodes the character into its constituent sounds. An input string is received that includes phonic codes. An application matches the decoded constituent sounds with the specified phonetic codes from the input string in accordance with rules of the spoken language and character boundaries to determine a contact to display.

Abstract: A software control method and apparatus for displaying a text based markup language interface. The interface can interact with a computer to provide reference documents, install system drivers and perform various system utilities. The interface can reference optical drives, hard disk drives or other storage medium and files available over a network, such as a local area network (LAN) or a wide area network (WAN) including the Internet. A graphical user interface using a text markup language such as hypertext markup language (HTML) can allow for activation of a user interactive control such as an icon or a hyperlink. Activation of an interactive control can hook onto a hypertext link target associated with the activated user interactive control result in the performance of an initial action responsive to variables including the control, a uniform resource locator associated with the interactive control and the hypertext link target.

Abstract: An MPEG data receiving apparatus adapted to interact with a MPEG data providing apparatus. A storage unit stores scene description information (SDI) from a received MPEG stream and a command recognition unit outputs node identification information based on user-selected objects and scene correction commands input by the user. A correcting unit searches for SDI stored in the storage unit corresponding to the scene correction commands and selectively updates the SDI on the object or requests the MPEG stream providing apparatus to update the SDI corresponding to the scene correction commands according to a result of determining whether the SDI corresponding to the scene correction commands exists in the storage unit. Accordingly, interaction between the MPEG data receiving apparatus and the MPEG data providing apparatus is enabled. Effective results are obtainable under a narrow bandwidth environment by reducing an amount of SDI transmitted from the providing apparatus.