Abstract: A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.

Abstract: Methods, apparatus and machine-readable medium are described that attempt to protect secrets from sleep attacks. In some embodiments, the secrets are encrypted and a security enhanced environment dismantled prior to entering a sleep state. Some embodiments further re-establish a security enhanced environment and decrypt the secrets in response to a wake event.

Abstract: A method for controlling power consumption associated with a processor in which, depending on the respective embodiment, a relative amount of idle time, activity time, or idle time and activity time associated with the processor are measured or detected, results of the measuring being used by the processor for controlling a clock speed.

Abstract: A device for transferring data signals between a first clock domain and a second clock domain comprises a serial memory element and a parallel memory element which are coupled. The serial memory element comprises at least one extra memory position more than the parallel memory element for the storage of the data signals.

Abstract: An apparatus and method is disclosed for providing capacity on demand using control to alter latency and/or bandwidth on a signaling bus in a computer system. If additional capacity is required, authorization is requested for additional capacity. If authorized, bandwidth of the signaling bus is increased to provide additional capacity in the computing system. Alternatively, upon authorization, latency of data transmissions over the signaling bus is reduced. In another alternative, upon authorization, memory timings are adjusted to speed up memory fetches and stores.

Abstract: The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal.

Abstract: A system, method and article of manufacture are provided for the automatic recovery from errors encountered during an automated Licensed Internal Code (LIC) update on a storage controller. The present invention functions with a concurrent or nonconcurrent automated LIC update. The automated recovery from many error conditions is transparent to the attached host system and on-site service personnel, resulting in an improvement in the LIC update process.

Abstract: The present invention provides a framework for managing both clustering and data replication in a software system distributed across multiple nodes. The framework includes at least one agent running at nodes comprising the distributed system. The framework also includes a master to coordinate clustering and replication operations. The framework further includes a library of software programs, called primitives, that are used by agents to communicate with the master. The agent(s) obtain cluster status information and replication status information, which are used by the master to manage clustering and replication operations. The framework is designed to work with existing cluster management applications and data replication facilities. The framework provides status information needed for coordinating clustering and replication operations to ensure that applications and data remain in a consistent state for disaster recovery purposes.

Abstract: Methods and apparatus for implementing peer-to-peer relay. In one implementation, a method of detecting and recovering from violations in a peer-to-peer relay network includes: receiving a message at a peer system from a sending peer system connected to said peer system in a peer-to-peer relay network detecting a violation in said received message; and sending an alert message to each peer system connected to said peer system in said peer-to-peer relay network; wherein each peer system in said peer-to-peer relay network stores a connection limit defining a number of other peer systems up to which that peer system is permitted to connect, and each peer system stores a set of one or more relay rules for relaying data to other peer systems connected to that peer system.

Abstract: Computer tools and methods novelly combine periodic backup and restore features with migration features to transfer the components of a failed system to a new system, which new system may be dissimilar to the old system. As well as backing up and transferring critical data files during the disaster recovery operation, the present invention also transfers, inter alia, applications, user states, hardware settings, software settings, user preferences and other user settings, menus, and directories. In another aspect of the present invention, a network of shared end-user computers periodically backs up each individual end-user computer to a central instrumentality, in a novel manner to reduce storage and time requirements.

Abstract: A router and routing protocol redundancy are disclosed to reduce service outage or degradation for a network device and thus to increase service availability on a network due to software and hardware failures of the network device. A network device such as router includes a redundancy platform having an active controller system and a standby controller system. A routing protocol state change is received or generated by the active controller system. The received or generated routing protocol state change is replicated to the standby controller system. By replicating the routing protocol state change, the standby controller system can maintain the routing protocol sessions for the network device if a failure occurs in the active controller system. Furthermore, the routing protocol states are maintained in realtime to handle the dynamic changes created by routing protocols.

Abstract: A data storage system has two computers. Each computer is assigned to a set of data. Two copies of each set of data are maintained. A first copy is stored on a first set of disks and a second copy is stored on a second set of disks. Each time that a data is written by a computer, a label is written to each set of disks, the label having fields for a status of each computer, a first ordinal which is increased each time that a new data is written, and a time stamp giving a time at which the last write was performed. After failure of a computer, a processor determines, in response to reading the labels of the first set of disks and the second set of disks, the most up to date copy of the data assigned to the failed computer.

Abstract: An electronic module is provided. The module includes a first logic device having at least two processors and a first comparator and a second logic device having at least one processor and a second comparator. Each of the at least two processors are coupled to each of the first and second comparators. The first and second comparators operate as a distributed comparator system. Each comparator independently identifies faults in the processors.

Abstract: The invention is intended to provide a backup control technique for protecting the safety of data stored in a storage system while minimizing the processing load in the storage system. A storage system 10 receives a command from a host computer 50 to write data control limitation data stipulating backup limitations, the data control limitation data is written to an expanded VTOC part where a storage area protected as the VTOC among the storage areas in the volume has been expanded, and backup is controlled based on the data control limitation data written to the expanded VTOC part.

Abstract: Data associated with the state of a parity update operation in a disk array system such as a RAID-6 system is stored during performance of the operation so that, in the event the operation is interrupted, recovery may be initiated using the stored data. The stored data may include a state indicator that is indicative of the status of the parity update operation, and snapshot data (e.g., a delta value indicative of a difference between new and old data) captured during the parity update operation.

Abstract: A system and method for maintaining persistent data during an unexpected power loss uses a memory controller and a supplemental power source. An entity running on the computer, for example, an application program, a utility, the operating system or other entity, may identify data for preservation using an application program interface. The application program interface may be provided by the memory controller. A sensor determines when an unexpected power loss has occurred and signals the memory controller. Using power from the supplemental power source, i.e. a battery or capacitor, the memory controller copies the identified data to a non-volatile memory. The memory controller may set a flag to indicate that preserved data is available for later recovery.

Abstract: Under the present invention, a configurable dictionary is provided. The configurable dictionary includes a set of objects that identify: (1) attribute conditions of the computer system to be checked; (2) associated locations within the computer system for checking the attribute conditions; and (3) actions to be taken based on results of the checks for the computer system. The health of the computer system is checked by processing the set of objects in the configurable dictionary. Specifically, the attribute conditions identified in the configurable dictionary are checked at their associated locations, and any necessary action are implemented.

Abstract: In-circuit-emulation of an integrated circuit includes a digital data processor capable of executing program instructions. A first debug event is detected during normal program execution. The causes the in-circuit-emulation to suspend program execution except for real time interrupts. A debug frame counter increments on each interrupt and decrements on each return from interrupt. If a debug event is detected during an interrupt service routine, that interrupt service routine is suspended and the count of the debug frame counter is stored. Execution of other interrupt service routines in response to corresponding interrupts is still permitted. The integrated circuit includes plural debug event detectors and the debug frame count is stored at the detector detecting a debug event during an interrupt service routine. This permits a determination of the order of interrupts triggering debug events by reading the stored debug frame count from each debug event detector.

Abstract: A few inexpensive hardware facilities are incorporated in a tightly synchronized cross checked design. These facilities allow initialization software to quickly bring the two processors to the same state by rapid, repeated resets and execution of the initialization software. The resets are done in a way as to be transparent to the rest of the system and to the end user.

Abstract: Briefly, according to the invention in an information processing system including a plurality of information processing nodes, a request for checkpointing by an application includes node health criteria (or parameters). The system has the authority to grant or deny the checkpointing request depending on the system health or availability. This scheme significantly improves not only the system performance, but also the application running time as the system. By skipping a checkpoint the application can use the same time to run the application instead of spending extra time for checkpointing.

Abstract: A logic analyzer data processing method used in a logic analyzer having a control circuit adapted to read in test data from a test sample, a memory controlled by the control circuit to store the test data received from the test sample, and a display adapted to display the test data fetched by the control circuit from the memory, the method including the step of enabling the control circuit to drive a compressor to compress the test data received form the test sample before storing it in the memory, and to decompress the compressed test data before transmitting it from the memory to the display.

Abstract: An email gateway diagnostic, tool, system, and method are provided for automated troubleshooting of email gateway functionality. Troubleshooting can occur in multiple modes of operation including: full diagnostic, interactive, and undeliverable mail status information. Based upon a set of rules and conditional statements, network and email gateway configurations, and user responses, an automated troubleshooting tool performs necessary testing to the email and network systems to interpret the available information and present the user with the source of the problem or suggest solutions and make recommendations as to why the email gateway may not be functioning properly.

Abstract: A method of operating a memory device when a program failure occurs is provided.

Abstract: A system and method to test a host bus adapter's (“HBAs”) ability to handle stream of invalid characters is provided. A data presenter module presents data to a HBA without being aware of a data format. A data producer module that is aware of the data format and schedules special characters so that the HBA can perform alignment operations. A bit offset change module changes a bit offset that is used by the data presenter module and causes to send random serial data to the HBA, which results in loss of alignment in the HBA and causes the HBA to decode invalid characters.

Abstract: An automatic safety test system, which comprises a control interface of a control unit for controlling the switching of a switch in a server unit and automatically switching to a specified testing point of an electronic product, and connects a bus interface of the control unit to a plurality of testing instruments for sending the values measured by the testing instrument at the specified testing point to a communication interface record of the control unit through the bus interface. Therefore, the automatic safety test system of the invention can automatically test every specific safety testing item at each testing point of the electronic product, and thus further achieves the objectives of saving time, manpower and resources.

Abstract: A computer process establishes data frequencies for recording data in zones of a zone bit recording medium in a disc drive. At least three data points are identified for each zone correlating data frequencies and corresponding bit error rates, and a slope of a curve between each two data points is calculated. The slopes are averaged, and the data frequency is calculated based on the average slope. If a difference between the average and default slopes exceeds a first threshold value, or if a spread of the slopes exceeds a second threshold value, the data frequency is calculated based on the average slope and the default slope. In one embodiment, each of the three data points is generated by recording data in the zone at each of three selected data frequencies, reading the recorded data, and calculating bit error rates based on the recorded and read data.

Abstract: An optical signal receiving equipment including an optical-electrical converter configured to convert optical signals into electronic signals; first deciders configured to transform the electronic signals into first binary signals; a second decider configured to transform the electronic signals into a second binary signal; a decision encoder configured to compute identification signals based on the plurality of first binary signals, and to compute reliability information of the computed identification signals; a converter configured to combine the identification signals and the second binary signal to combined identification signals; and a controller configured to execute an initial identification of the electronic signals in any one of the plurality of first deciders by using an initial threshold level in the plurality of first deciders, to measure an average amplitude of the electronic signals, and to correct the threshold level of the plurality of first deciders based on a variation of the average amplitud

Abstract: A system, apparatus, computer program product and method of performing operational validation on a system are provided. The system may include a CPU with a cache, a communications network, and a plurality of devices exchanging data during a test. When the test is ready to be performed, the CPU may set up a pool of buffers in the cache. The pool of buffers may generally have a set of locations corresponding to locations in an actual destination buffer and a set of locations corresponding to locations in an actual source buffer. During the performance of the test, data is exchanged over the communications network to and from the source and destination buffers. Snooping logic in the cache may snoop data on the communications network. The data snooped may be entered in appropriate locations in the pool of buffers. This allows the CPU to perform operational validation by using cached data instead of data that is in the actual source and destination buffers.

Abstract: A built-in self-test (BIST) architecture having distributed algorithm interpretation is described. The architecture includes three tiers of abstraction: a centralized BIST controller, a set of sequencers, and a set of memory interfaces. The BIST controller stores a set of commands that generically define an algorithm for testing memory modules without regard to the physical characteristics or timing requirements of the memory modules. The sequencers interpret the commands in accordance with a command protocol and generate sequences of memory operations. The memory interfaces apply the memory operations to the memory module in accordance with physical characteristics of the memory module, e.g., by translating address and data signals based on the row-column arrangement of the memory modules to achieve bit patterns described by the commands. The command protocol allows powerful algorithms to be described in an extremely concise manner that may be applied to memory modules having diverse characteristics.

Abstract: Method and apparatus for testing memory cells of a DRAM memory chip arranged together with a nonvolatile memory chip in a multichip memory module. The multichip memory module may be incorporated in an application apparatus, in particular in a mobile telephone or a notebook. One embodiment provides a method for the DRAM memory chip to be subjected to a self-test, during which the functionality of the memory cells is checked, in a time in which the memory cells of the DRAM memory chip are not accessed in an operative operating mode of the application apparatus.

Abstract: The present method generates a greater number of hot holes than those generated by normal write/erase operations, thereby making it possible to evaluate an operation of a non-volatile memory with respect to hot holes. The present method performs a write operation to the non-volatile memory at lower temperatures than normal temperatures at normal use or/and at a lower operation voltage than a normal operation voltage at normal use, so as to generate a greater number of hot holes than those generated by normal write/erase operations between floating gates and drains of the memory, and then evaluates the operation of the memory while exposing it to the normal operation temperatures. This method is applicable to reliability tests of non-volatile memories such as FLASH memories.

Abstract: Methods and apparatus are provided that allow an electronic system having a signaling bus with a fault on a signaling conductor to operate at a degraded performance. A block of data is transferred from a first electronic unit to a second electronic unit over the signaling bus. A transmission sequence sends the block of data using all of the nonfaulty signaling conductors using a minimum number of beats required to complete the transmission.

Abstract: Testing an integrated circuit having programmable logic is described. Programmable logic is configured as a daisy-chain of registers (310-1 through 310-(N+1)) in a closed input/output loop to register a logic 1 and logic 0s. The logic states are circulated around the closed input/output loop. Operation of output blocks (210-1 through 210-N) is controlled responsive to a series of outputs (316-1 through 316-N) provided from a portion of the daisy-chain of registers (310-1 through 310-N) to selectively place an output block of output blocks (210-1 through 210-N) in an output mode responsive to the logic 1 output in the series of outputs while leaving the output blocks remaining in a non-output mode responsive to the logic 0s in the series of outputs. The output blocks (210-1 through 210-N) are commonly coupled at an output node (212) for coupling to a single test channel, as only one output block is in the output mode at a time.

Abstract: The invention provides a method and circuitry to save power in a synchronous logic ASIC with low overhead. The scan chain(s) and boundary scan mechanism of the synchronous logic ASIC are used and modified for shifting out current states of internal memory devices of the synchronous logic ASIC to an external memory and for retaining the power-off blocks' primary output values to the memory devices of the boundary scan circuit, so the proposed gated power method is efficient and low overhead in the synchronous, flop-based, logic circuit design.

Abstract: Methods and apparatus are provided for testing digital circuits. In one implementation, a scan chain test structure is provided that includes a cell chain, a first scan chain, and a second scan chain. The first scan chain is operable to test digital circuitry within a first portion of the cell chain, and the second scan chain is operable to test digital circuitry within a second portion of the cell chain. The first scan chain is further operable to test digital circuitry within the second scan chain, and the second scan chain is further operable to test digital circuitry within the first scan chain.

Abstract: A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the scan chain, and if the scan chain is defective (for example, based on the unloaded logic values), then localizing a defect in the scan chain from the unloaded logic values by comparison thereof with the known locations of the latches of the scan chain loaded with the known logic value via the fuses. The scan chain may be predesigned with fuses spaced periodically across the chain every n latches to facilitate subsequent localization of a detected defect in the scan chain.

Abstract: A method and an apparatus of compensating for a signal receiving error at a receiver in a packet-based communication system. In the invention, frequency offset estimation and DC offset estimation obtained in a current packet are re-used in a next packet if the receiver is an intended recipient of the current packet and the current packet is received correctly, verified by CRC-32 checking in the PHY layer and the DA checking in the MAC layer, respectively. Thereby, the overall receiver performance and stability can be improved from packet to packet and the estimation algorithm is simplified.

Abstract: A packet data retransmission control method, where a base-station upper-level control system transmits downstream packet data, which is terminated at a terminal station, to a plurality of base stations. A specific base station that is one of the base stations transfers the downstream packet data to the terminal station. The plurality of base stations receive an upstream control signal with which reception of the downstream packet data is acknowledged and which is returned from the terminal station. Base stations other than the specific base station notify the specific base station via the base-station upper-level control system that they have received the upstream control signal. The specific base station determines packet data to be retransmitted according to the receiving situation thereof for the upstream control signal returned from the terminal station and the receiving situations of the other base stations for the upstream control signal.

Abstract: A medium access control-high speed (MAC-hs) comprises a hybrid automatic repeat request (H-ARQ) device configured to receive data blocks over a wideband-code division multiple access (W-CDMA) high speed-downlink shared channel (HS-DSCH). The H-ARQ device generates an acknowledgement (ACK) or negative acknowledgement (NACK) for each said data block received. Each received data block having a transmission sequence number. The H-ARQ device receives a new transmission instead of a pending retransmission at any time. At least one reordering device has an input configured to receive an output of the H-ARQ device and the at least one reordering device configured to reorder the received data blocks based on each received data block's transmission sequence number (TSN). Received data blocks are immediately forwarded for processing for higher layers when the received data blocks are received in sequence.

Abstract: Information signals such as grayscale images or audio signals are represented as a sequence of PCM signal samples. To embed auxiliary data in the least significant bits of the signal, the samples are slightly distorted. There is a so-termed “rate-distortion function” (20) which gives the largest embedding rate R given a certain distortion level D. It appears that the efficiency of prior art embedding schemes such as LSB replacement (21,22) can be improved. The invention discloses such embedding schemes (23,24). According to the invention, the signal is divided into groups of L (L>1) signal samples (x). For each group of signal samples, a vector of least significant portions (x mod n) of the signal samples is created. For n=2, the vector comprises the least significant bit of each signal sample. The syndrome of said vector (as defined in the field of error detection and correction) represents the embedded data.

Abstract: Method and apparatus for decoding a one-point algebraic geometric code of dimension k and length n, in order to identify the position of the errors in a received word, the syndromes matrix S, of dimension (n?k)×(n?k) is defined, of which the elements Sij of each line i are calculated, for j between 1 and w(i), where the boundary w is a decreasing function, using the syndrome s of the received word, as well as the matrix S* obtained by “extending” the matrix S, that is to say by calculating the value of certain elements S*ij where j is greater than w(i). This method makes it possible in certain favorable cases to find the erroneous positions of the received word when the number of errors is greater than (n?k+1?g)/2, even if it is not possible to calculate all the elements of S* conventionally required by a two-stage algorithm to perform that correction.

Abstract: The invention relates to an error correction coding method, using at least two distinct sections of a predetermined elementary code, associating an arrival vector (s2, s3) with a starting state vector (s0, s1), according to a vector of branch labels (b0, b1, b2, b3), defining a code word, two sections of said elementary code being distinct when the order and/or the role of the elements of said branch label vector are changed.

Abstract: Write check bits are generated in a predictive manner for partial-word write transactions in a memory system implementing error code correction. A read data word and associated read check bits are read from an address of the memory. If an error exists in a byte of the read data word, this byte is identified. At the same time, one or more bytes of the uncorrected read data word are merged with one or more bytes of a write data word, thereby creating a merged data word. Write check bits are generated in response to the merged data word. If the merged data word includes a byte of the read data word, which contains an error, the write check bits are modified to reflect this error. The merged data word and the modified (or unmodified) write check bits are then written to the address of the memory.

Abstract: A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory information at regular time intervals or at the timing of connection of electric power supply, independently of reading out the memory information according to external access request. Therefore, it is possible to improve reliability of data retention in the non-volatile memory without the host device reading out the memory information from the non-volatile memory of the memory card.

Abstract: When parity checking in a disk array such as a RAID-6 system determines data and parity information is unsynchronized, additional calculations are performed to determine whether the error may be attributed to faulty data on a disk drive or to a more systemic problem such as a faulty controller. In particular, for each particular error detected, the parity generating information is analyzed to determine if each error involves a common disk index. If so, the data can be corrected on that disk; if not other corrective procedures are implemented.

Abstract: At the receiver in a wireless communications system, the likelihood of a false CRC pass that can occur when a weak received signal produces an all ZERO output from a convolutional or a turbo decoder is minimized. To prevent an all ZERO output, a convolutional decoder selects from among those determined equally most likely transmitted sequences of bits in a data block one that has a weight greater than the one having the minimum weight. A turbo decoder selects a ONE rather than a ZERO as the value of a transmitted bit in a data block when for that bit a bit value of a ZERO and a ONE are determined to be equally likely.

Abstract: A method of mobile communication including a transmitter having multiple transmitters and a receiver having multiple receivers. The method includes adding a cyclic redundancy check (CRC) code to a data block to be transmitted and spatially segmenting the data block according to a modulation scheme and a coding rate of each respective transmit antenna of the multiple antennas.

Abstract: The present invention concerns a method and apparatus of decoding a one-point algebraic geometric code defined on an algebraic curve represented by an equation in X and Z of degree 2?? in Z, where ? is a strictly positive integer and ? an integer greater than 1, obtained by taking the fiber product of ? component algebraic equations, each of said component equations governing the unknown X and an unknown Yi, where i=0, . . . , ??1, and being of degree 2? in Yi. This method comprises the decoding of 2(??1)? “clustered” codes, all defined on the same algebraic curve represented by one of said component equations.

Abstract: Encoding inputs corresponding to a set of powers of state matrix is added. Powers of state matrix have period T. The set of the powers of the state matrix has an identical state matrix value. One of the powers of the state matrix is multiplied by input matrix and the added encoding inputs. Multiplied results are added so as to find last state of the turbo encoder. The last state corresponds to encoding state of the turbo encoder when the turbo encoding is started at zero state. Final state of the turbo encoder is found using the last state. The final state is identical to initial state of the turbo encoder, and corresponds to encoding state of the turbo encoder when turbo encoding is started with the initial state. Encoding inputs are encoded using the final state.

Abstract: An apparatus for reproducing data includes a branch metric computation unit and a plurality of parallel computation units. Each parallel computation unit includes path metric computation units that compute path metric values based on branch metric values. Path metric memories store the path metric values to be used in a next following path metric computation, and reliability computation units compute path reliability. Modified-path generating units generate an inverted path that is inverse to a path indicated by an output of the reliability computation units as having low reliability. If any one of the modified-path generating units generates the inverted path, a corresponding one of the path metric computation units stores a path metric value corresponding to the inverted path in a corresponding one of the path metric memories as a path metric value to be used in a next following path metric computation.