Abstract: For making outputs of a drive circuits accurate, the drive circuit is composed of a plurality of current signal generation circuits for outputting a current signal to each of a plurality of output units, a current signal output line to which outputs of the plurality of current signal generation circuits are commonly connected, a correction value output circuit for outputting a correction value obtained by evaluating the output of one or more specific circuits of the plurality of current signal generation circuits on a basis of current values output through the current signal output line, and a correction circuit for correcting an image signal supplied to the current signal generation circuits by means of the correction value.

Abstract: According to one exemplary embodiment, an amplitude compensation circuit includes a first composite programmable buffer for receiving a first input signal with a first input amplitude. The amplitude compensation circuit further includes a second composite programmable buffer for receiving a second input signal with a second input amplitude. The amplitude compensation circuit also includes a feedback circuit coupled to respective outputs of the first and second composite programmable buffers. According to this embodiment, the feedback circuit compares a first output amplitude of the first composite programmable buffer with a reference voltage and a second output amplitude of the second composite programmable buffer with the reference voltage and provides first and second control signals for adjusting the respective gains of the first and second composite programmable buffers so as to reduce respective differences between the first and second output amplitudes and the reference voltage.

Abstract: The present invention relates to an oscillator outputting two triangle waves having the same amplitude and whose phases are inverted; and a pulse width modulator using the oscillator. A capacitor 3 is charged or discharged by a charge pump circuit 2 controlled by a Schmitt circuit 1, and a voltage integrated by a two-output differential amplification circuit 6 is positively fed back to the input of the Schmitt circuit 1 to output two triangle waves having the same amplitude and whose phases are inverted. Since the output stage is composed of a differential amplification circuit, the circuit has low output impedance and is protected from wiring capacity and connected input capacity, and since integral operation is caused to be performed by the differential amplification circuit, the distortion in the waveform of the triangle waves can be prevented.

Abstract: A clock generator includes a current source for generating a constant current; a current mirror coupled between a supply voltage and the current source for generating a mirror current equal to the constant current multiplied by a predetermined value; and a charge control module coupled with the current source and the current mirror for charging a capacitor when a voltage thereof is lower than a predetermined threshold voltage and for discharging the capacitor when the voltage thereof is higher than the predetermined threshold voltage, thereby generating a clock signal at a predetermined frequency, wherein the charge control module adjusts the predetermined frequency by changing the predetermined threshold voltage.

Abstract: A power-on-reset circuit for generating a reset voltage including a voltage divider and a temperature compensator that is insensitive to a change in PVT (Process, Voltage, Temperature) is disclosed. The temperature compensator compensates for a voltage variation of the voltage divider in an inversely proportional direction of a voltage variation of the voltage divider. The power-on-reset circuit of the present invention generates a reset signal during a power-off as well as during a power-on.

Abstract: A method and apparatus for generating multi-phase clock signals. The multi-phase generating method includes: generating L reference clock signal groups having predetermined phase delay intervals from an external clock signal, wherein each reference clock signal group includes M sub reference clock signals; averaging phases of sub reference clock signals for each reference clock signal group, and generating L main reference clock signals from the L×M sub reference clock signals; and sequentially delaying the L main reference clock signals, and generating the N multi-phase clock signals having the different phases. Because a plurality of clock signals having equal phase delay intervals between each other are generated regardless of the frequency of a received clock signal, the yield of Delay Locked Loop (DLL) circuits is improved using the multi-phase generating apparatus.

Abstract: A charge pump circuit is disclosed, including: a dummy current path comprising a first junction node; a normal current path comprising a second junction node; a switch, coupled between the dummy current path and the normal current path; wherein when the switch is closed a first voltage is at the first junction node and the second junction node, and when the switch is open a second voltage is at the first junction node; and a comparator, for comparing the first voltage and the second voltage to balance a current mismatch of the charge pump circuit. The disclosed charge pump circuit can be implemented in a phase locked loop system.

Abstract: An oscillating apparatus is provided that includes: a filter circuit that includes a capacitor and outputs a control signal based on an amount of charge accumulated in the capacitor; an oscillator that outputs an oscillation signal of a frequency that is based on the control signal; a phase comparator that compares the oscillation signal with a reference signal of a predetermined frequency, to detect a phase difference between the oscillation signal and the reference signal; a switch circuit that controls whether to charge the capacitor according to a predetermined charge current or to discharge the capacitor according to a predetermined discharge current, based on the phase difference; and a current stabilizing current that defines each of the charge current and the discharge current based on a predetermined reference current or a reference voltage.

Abstract: The present invention relates to a delay fixing loop circuit including a delay fixing loop for reducing a skew between an external clock and a data, or between an external clock and an internal clock, and a clock locking method thereof. The delay fixing loop circuit includes a delay circuit delaying a reference clock in which an external clock is buffered and outputting the delayed reference clock as an internal clock; a control circuit comparing the reference clock and a phase of a feedback clock of the internal clock, and increasing or decreasing delay of the reference clock of the delay circuit according to the comparison result if a delay fixing loop is in an enable state, and decreasing delay of the reference clock of the delay circuit according to a reset signal provided from outside if the delay fixing loop is in a disable state; and a clock driver providing the internal clock of the delay circuit which is controlled by the control circuit as an output clock of the delay fixing loop.

Abstract: A delay locked loop (DLL) circuit is disclosed. The DLL circuit includes a first delay locked loop (DLL) configured to receive a plurality of first clock signals, delay each of the first clock signals by a predetermined period of time in response to a first control signal, and generate a plurality of first internal clock signals and a second delay locked loop (DLL) configured to receive the first internal clock signals, delay the first internal clock signals by a predetermined period of time in response to a second control signal, and generate a plurality of second internal clock signals.

Abstract: A delay locked loop is disclosed which includes a clock selector for selecting and outputting any one of normal-phase and reverse-phase external clocks in response to a clock selection information signal, a first delay line for delaying an output signal from the clock selector by a predetermined amount of time, a second delay line for delaying an inverted version of an output signal from the first delay line by a predetermined amount of time, and a phase mixer for mixing a phase of the output signal from the first delay line and a phase of an output signal from the second delay line and outputting an internal clock having a corrected duty cycle as a result of the mixing.

Abstract: A time-to-digital converter (TDC), a system-on-chip including a TDC, a method of phase detection for use in synthesizing a clock signal and a non-linearity corrector for a TDC. In one embodiment, the TDC includes a chain of delay elements configured to receive a clock signal and generate delayed clock signals. Each one of the delay elements includes: (1) a non-inverting buffer configured to delay the clock signal by about twice a delay of an inverter to provide a buffer-delayed clock signal and (2) a first transmission gate coupled to the non-inverting buffer and configured to delay the clock signal by about the delay of an inverter to provide a first gate-delayed clock signal.

Abstract: Systems and methods for transmitting a signal having a desired phase at the device are disclosed. The systems and methods further include determining a signal path length to a device over a transmission line and adding a delay to a signal to be transmitted over the transmission line. The determination is made in response to determining the path length to the device.

Abstract: In general, in one aspect, the disclosure describes an apparatus having a capacitor to receive an input signal and to block DC portion of the incoming signal. A buffer is used to receive the DC blocked incoming signal and output an outgoing signal. A low pass filter is used to convert duty cycle error in an outgoing signal to a DC offset and to provide the DC offset to the capacitor. The DC offset is used to bias the capacitor. The biasing of the capacitor can adjust the DC blocked incoming signal so as to reduce the duty cycle error in the outgoing signal.

Abstract: Disclosed is a multi-threshold CMOS (MTCMOS) flip-flop circuit. The MTCMOS flip-flop circuit includes a data input unit including an inverter for receiving an input data signal, inverting the input data signal and then outputting an inverted data signal; a clock signal generator including an inverter for receiving an input clock signal and a logic gate for generating a pulsed clock for latching the inverted data signal at a rising time of the input clock signal; a data transmitting unit including a switch for receiving the data signal output from the data input unit to selectively output the inverted data signal and controlling transmission of data based on the pulsed clock; and a data latch and output unit including a feedback inverter having a feedback path used for data latch so as to receive the inverted data signal and generate an output Q.

Abstract: A signal driver having a selectable aggregate slew rate, a method of driving a signal driver and a signal driver incorporating the driver or the method. The driver includes plural partial drivers configured to output signals based on time constants established by corresponding plural time-delay networks associated therewith. The signal driver further includes a slew rate selector coupled to the plural time-delay networks and configured to provide a common signal thereto to cause the plural time-delay networks to achieve target time constants, the target time constants causing the output signals to be generated such that the signal driver achieves the selectable aggregate slew rate.

Abstract: A time delay circuit includes an RC circuit with a resistor and a capacitor connected, and a switch. The switch includes a first terminal, a second terminal, and a control terminal for controlling conduction of the first and second terminals. The first terminal is connected to an end of the resistor, which is connected to the capacitor. The second terminal is connected to ground, and the control terminal is connected to the other end of the resistor configured for receiving an input signal. When the input signal changes from logical low to logical high to turn off the switch, the capacitor is charged to a predetermined value with a predetermined rise time beginning from the change of the input signal. When the input signal changes from logical high to logical low to turn on the switch, the first and second terminals of the switch conduct to quickly discharge the capacitor to the predetermined value substantially synchronized with the change of the input signal.

Abstract: The present invention relates to a semiconductor memory device having a clock buffer circuit which buffers an external clock to generate an internal clock, wherein the clock buffer circuit comprises a rising clock buffer which buffers an external clock to generate a rising internal clock corresponding to a rising edge of the external clock; and a falling clock buffer which buffers the external clock to generate a falling internal clock corresponding to a falling edge of the external clock, whereby the external signal is input to the internal circuit in synchronization with the rising internal clock and the falling internal clock.

Abstract: A DC offset calibration apparatus is disclosed. The DC offset calibration apparatus includes an adjustment circuit and an offset calibration circuit. The adjustment circuit is utilized for receiving an input signal and an offset calibration signal, and for adjusting the input signal to generate an output signal according to the offset calibration signal. The offset calibration circuit is coupled to the output signal and to the adjustment circuit for determining the offset calibration signal according to at least the output signal and a predetermined threshold value.

Abstract: A DC offset calibration apparatus includes a first adjustment unit, a first offset calibration circuit, a second adjustment unit, and a second offset calibration circuit. The first adjustment unit adjusts a first input signal to generate a first output signal according to a first offset calibration signal. The first offset calibration circuit is coupled to the first output signal and the first adjustment unit for determining the first offset calibration signal according to the first output signal and predetermined threshold value. The second adjustment unit adjusts a second input signal to generate a second output signal according to a second offset calibration signal. The second offset calibration circuit is coupled to the second output signal and the second adjustment unit for determining the second offset calibration signal according to the second output signal and the predetermined threshold value. The first and the second input signals are a differential signal pair.

Abstract: A level shifter circuit 28 has a first buffer circuit 30 and a second buffer circuit 32, 34. An intermediate signal generated by the first buffer circuit 30 is directly passed to the second buffer circuit 32, 34 to control output of one of its output signal levels. A feedback signal generated in response to the input signal within the first power domain containing the first buffer circuit 30 is passed directly to the second buffer circuit 32, 34 to control the output signal level reaching the other of the output values. A feedback circuit comprising cross-coupled PMOS transistors 38, 40 is provided to boost the feedback signal level up to the voltage level of the second voltage domain which contains the feedback circuit 38, 40 as well as the second buffer circuit 32, 34. The level shifter circuit 28 has a low latency and a low static power consumption.

Abstract: A switching control circuit, controlling a transistor, of a voltage generating circuit generating an output voltage of a target level from an input voltage applied to the transistor, comprising: an error amplifier circuit outputting an error voltage obtained by amplifying an error between a voltage according to the output voltage and a first reference voltage; a first comparison circuit comparing the error voltage with a second reference voltage to output a first control voltage; a second comparison circuit comparing the error voltage with a third reference voltage to output first and second voltages; a charging and discharging circuit for charging and discharging a capacitor based on the first and second voltages; a third comparison circuit comparing a charged voltage of the capacitor with a fourth reference voltage; and a control circuit outputting a second control voltage for turning off the transistor according to a result of the third comparison circuit.

Abstract: A compensating quantity-providing circuit includes a frequency signal generator having an output for a frequency signal the frequency of which depends on mechanical stress in a circuit, and a compensating quantity provider having an input for the frequency signal and an output for a compensating quantity which is based on the frequency signal.

Abstract: A design structure for electrically programmable fuse sense circuit having an electrically programmable fuse and a reference resistance. A first current source is coupled, through a first switch, to the electrically programmable fuse. A second current source is coupled, through a second switch, to the reference resistance. A precharge signal enables the first current source, the second current source and closes the first switch and the second switch, creating voltage drops across the electrically programmable fuse and the reference resistance. When the precharge signal goes inactive, the first current source and the second current source are shut off, and, at the same time the first switch and the second switch are opened. A latching circuit uses a difference in the voltage drops when the precharge signal goes inactive to store a state of the electrically programmable fuse, indicative of whether the electrically programmable fuse is blown or unblown.

Abstract: Unified voltage generation techniques for efficiently generating a plurality of operational voltages for use within an electronic device, such as a memory system (e.g., memory product) providing data storage, are disclosed. A voltage generation circuit can generate a regulated base output voltage. The voltage generation circuit can include one or more voltage output circuits that produce different operational voltages from the regulated base output voltage. According to one aspect of the invention, the voltage output circuits can be disabled when the different operational voltages are at their appropriate voltage potentials, thereby reducing power consumption by the voltage output circuits. The voltage generation circuit is therefore able to operate with improved power efficiency.

Abstract: A multiple polarity reversible charge pump circuit is disclosed which, in certain embodiments, may be configured to generate a positive voltage at times and may be reversed to generate a negative voltage at other times. Such a charge pump circuit is advantageous if both the positive and negative voltage are not simultaneously required. In certain other embodiments, a charge pump circuit generates a high output current for only a positive boosted voltage in one mode of operation, but lower current positive and negative boosted voltage outputs in another mode of operation. Use with certain erasable memory array technologies is disclosed, particularly certain resistive passive element memory cells, and more particularly in a three-dimensional memory array.

Abstract: A multiple polarity reversible charge pump circuit is disclosed which, in certain embodiments, may be configured to generate a positive voltage at times and may be reversed to generate a negative voltage at other times. Such a charge pump circuit is advantageous if both the positive and negative voltage are not simultaneously required. In certain other embodiments, a charge pump circuit generates a high output current for only a positive boosted voltage in one mode of operation, but lower current positive and negative boosted voltage outputs in another mode of operation. Use with certain erasable memory array technologies is disclosed, particularly certain resistive passive element memory cells, and more particularly in a three-dimensional memory array.

Abstract: A voltage reference generation circuit having switch pairs coupled to systematically commutate a flying capacitor among adjacent pairs of voltage rail outputs. The circuit requires only a single flying capacitor, N+1 switch pairs, and N storage capacitors, to generate N intermediate voltage references between VDD and GND. A signal generator produces N+1 non-overlapping switch enable signals to systematically enable the switch pairs and commutate the single flying capacitor between the rail pairs. The flying capacitor remains charged to VDD/(N+1). The N storage capacitors hold their respective reference outputs at VDD*N/(N+1), VDD*(N?1)/(N+1), VDD*(N?2)/(N+1), and so forth.

Abstract: An internal voltage generation device is disclosed which includes an internal voltage generator operated in response to an enable signal, the internal voltage generator generating an internal voltage using a reference voltage, and a sub-voltage generator for driving an output terminal of the internal voltage generator to a predetermined voltage level in response to a control signal.

Abstract: A charge pump type booster circuit generates a positive or negative boosted output voltage by switching booster paths one by one. This charge pump type booster circuit includes a plurality of booster paths, each of the plurality of booster paths including at least one booster capacitor, wherein a number of the booster capacitor at each of the plurality of booster paths is different between one booster path and the other booster path. This makes it possible to suppress an increase in a number of an external capacitor for setting an output voltage of the booster circuit constant.

Abstract: A design structure embodied in a machine readable medium used in a design process includes a voltage divider device, including a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region; the first and second gates configured to have an input voltage coupled thereacross; and at least one of a source of the FET and a drain of the FET configured to have an output voltage taken therefrom; wherein the output voltage represents a divided voltage with respect to the input voltage.

Abstract: Unified voltage generation techniques for efficiently generating a plurality of operational voltages for use within an electronic device, such as a memory system (e.g., memory product) providing data storage, are disclosed. A voltage generation circuit can generate a regulated base output voltage. The voltage generation circuit can include one or more voltage output circuits that produce different operational voltages from the regulated base output voltage. According to one aspect of the invention, the voltage output circuits can be disabled when the different operational voltages are at their appropriate voltage potentials, thereby reducing power consumption by the voltage output circuits. The voltage generation circuit is therefore able to operate with improved power efficiency.

Abstract: There is provided an internal voltage generation circuit generating an internal voltage used for a semiconductor memory device. The internal voltage generation circuit includes a current mirror type internal voltage detector generating a comparison voltage and comparing the comparison voltage with a reference voltage to output the comparison result as a detection signal, and a charge pump outputting the internal voltage and controlling the level of the internal voltage by the detection signal. The current mirror type internal voltage detector generates a comparison voltage whose level is determined in accordance with the output of the current mirror having a variable current source in which current varies in accordance the output internal voltage.

Abstract: A standard voltage generation circuit is provided with a function of automatically stopping charging when a standard voltage reaches a stable voltage point by rapidly charging a standard voltage stabilization capacitor during transition from a standby state to a normal operation state. The standard voltage generation circuit is also provided with a function of precharging an output terminal of the circuit to a voltage close to the stable voltage by a potential division effect of the capacitor during transition from the standby state to the normal operation state. Thereby, it is possible to prevent an increase in the amount of time that is required until the standard voltage reaches the stable voltage when the state of an analog circuit included in the standard voltage generation circuit changes from its off state to its on state.

Abstract: A coil section detects undesirable radiation generated from a baseband process circuit section mounted at a specific position on a substrate, the coil section including a wire with a specific shape that is disposed at a position close to the baseband process circuit section, and a cancellation signal generation section generates a signal that cancels the undesirable radiation detected by the coil section.

Abstract: A cancellation signal generation section generates a cancellation signal which cancels an alternating-current component of a power supply terminal voltage of a digital signal processing circuit section, and a synthesis section synthesizes the generated cancellation signal and a power supply voltage of an analog signal processing circuit section to cancel noise superimposed on the power supply voltage.

Abstract: The present invention addresses a need for reducing the power consumption in a baseband filter used in a front-end wireless receiver while providing the necessary linearity. In particular, relatively high linearity can be obtained with lower power consumption than has heretofore been the case. This is achieved in embodiments of the invention using an optimized single-branch fully differential structure which operates as a “composite” source-follower (when using CMOS devices) with an ideal unitary dc gain. A positive feedback internal to the source follower allows one to synthesize two complex-poles.

Abstract: An integrated circuit including a tunable capacitance multiplier. The integrated circuit includes a reference capacitor and a current source arrangement coupled in parallel to the reference capacitor. The current source arrangement can include a plurality of current sources that are switchably coupled to the reference capacitor in a manner that causes the capacitance of the reference capacitor to vary based on which current sources are coupled thereto. The current sources can be current mirror arrangements of other suitable current sources. The gain factors of the current sources are configured to establish the capacitance variability range and the incremental variance steps therein. In phase-locked loop (PLL) applications, the tunable capacitance multiplier is used to replace the main loop filter capacitor to provide a variable loop bandwidth, thus allowing relatively large values of capacitance to be realized using a relatively small physical capacitor.

Abstract: An integrated circuit including a capacitance multiplier having reduced parasitics and injected noise compared to conventional multiplier methods. The integrated circuit includes a reference capacitor and a current mirror arrangement coupled to the reference capacitor. The current mirror arrangement, which includes a current gain factor N, varies the capacitance of the reference capacitor by a factor of N+1, based on the reference capacitor current. The current mirror arrangement includes an operational amplifier operating in conjunction with two mirror transistors to form a current mirror arrangement having little or no series resistance. The current mirror also can include a plurality of resistors configured to reduce the noise from the capacitance multiplier, thus making the capacitance multiplier useful for applications that may require relatively low noise.

Abstract: Embodiments of the present invention are directed to processing an incoming signal by using a demodulation signal, while controlling the phase of the demodulation signal in relation to the incoming signal. The incoming signal can be processed by being mixed with the modulation signal at a mixer. The mixing may thus cause various beneficial modifications of the incoming signal, such as noise suppression of the incoming signal, rectification of the incoming signal, demodulation of the incoming signal, etc.

Abstract: A PLL circuit includes: a clock signal generating unit for generating a first clock signal and a second clock signal of which the phase differs from the first clock signal by ?/2; a computing unit for computing first phase comparison results showing the results of comparing the phases of a signal wherein the first clock signal is subjected to phase shifting with the PSK modulation signal, and second phase comparison results showing the results of comparing the phases of a signal wherein the second clock signal is subjected to phase shifting with the PSK modulation signal, based on first and second parameters, the first clock signal, the second clock signal, and the PSK modulation signal; a control direction setting unit for virtually controlling the control angle; a parameter control unit; and a reading control unit for controlling the timing of reading data from the PSK modulation.

Abstract: A corrective predistortion function is applied to a signal to compensate for or cancel out distortion that is introduced by a component that processes the signal. A disclosed example includes applying a corrective predistortion function to a transmitted signal used for wireless communications. A technique for selecting the corrective predistortion function includes determining a current power level of the signal. When the current power level is at or below a lift level between a maximum signal power level and a minimum signal power level, a corrective predistortion function corresponding to the lift level is applied to the signal. When the actual signal power level is above the lift level, a corrective predistortion function corresponding to the actual current power level is applied.

Abstract: An approach for determining corrective predistortion functions includes maintaining a history of recent estimations of a plurality of corrective predistortion functions. Each of those functions corresponds to a respective signal characteristic. By determining a feature of each of those functions from the history, one of the corrective predistortion functions is selected for a next estimation based upon which of the functions has a feature within the history that satisfies a selected criteria. In a disclosed example, the function having the lowest number of estimations within a recent history is selected as the function to have the highest priority for a next estimation.

Abstract: A predistortion linearization device (D) produces gain and phase expansions making it possible to compensate for the gain compression and phase variation of a power amplifier. This device (D) also allows the conventional adjustment of amplitude, the adjustment of the form of the gain and phase expansions as a function of a microwave input signal (Se).

Abstract: Disclosed is a switch mode power amplifier that provides high power (e.g., 100 W) at a high frequency (e.g., microwave frequency range). The switch mode power amplifier includes a load resistor, an inductor-capacitor (LC) circuit connected in parallel with the load resistor, a first switching mechanism connected to a first endpoint of the load resistor, and a second switching mechanism connected to a second endpoint of the load resistor. In one embodiment, the LC circuit is a first LC circuit connected in parallel with the load resistor and a second LC circuit is connected in series with the first LC circuit (and therefore connected in parallel with the load resistor). The circuit is transformer free.

Abstract: An auxiliary current source is provided that includes MOS transistors feeding startup auxiliary current to the input portion of an output common mode voltage generation circuit amplifying the output of a differential amplifier and generating an output common voltage, and a correction current source is provided that includes MOS transistors feeding correction current corresponding to the auxiliary current to a common mode feedback comparator. Thereby, a control loop that controls the output common voltage to a predetermined voltage even when the input of the differential amplifier is outside the dynamic range at the beginning is correctly started up, thereby stabilizing the output common voltage at a desired voltage.

Abstract: A programmable gain amplifier includes an operational amplifier coupled thereto a plurality of resistors to perform a feedback control, thereby rendering a closed-loop gain A f ? ( s ) = A ? ( s ) 1 + A ? ( s ) · ? , where ? is a feedback factor determined by the resistance of the resistors and A(s) is an open-loop gain of the operational amplifier. The operational amplifier includes a first-stage amplifying circuit, a second-stage amplifying circuit, and a compensating capacitor coupled to an output end of the first-stage amplifying circuit and having an equivalent capacitance variable to adjust a dominant-pole frequency of the open-loop gain of the operational amplifier.

Abstract: Aspects of a method and system for precise current matching in deep sub-micron technology may include adjusting a current mirror to compensate for MOSFET gate leakage currents by using feedback circuits. The feedback circuits may be implemented from active components to create active feedback circuits. If the reference current to be mirrored is noisy, a smoothing effect may be achieved by introducing a low-pass filter coupled to the current mirror design. The active feedback may comprise amplifiers, which may comprise one or more amplifier stages. The amplifier may amplify either a bias voltage error or a bias current error. Furthermore, a transimpedance amplifier may be utilized in the feedback loop. The output bias current of the current mirror may be stabilized dynamically during adjusting. Multiple current sources may be utilized in the current mirrors.

Abstract: A variable frequency amplifier suffering less deterioration of strain characteristic and capable of operating at plural frequencies is disclosed. In one aspect, a changeable amplifier comprises an amplifying element, a changeable matching circuit disposed at an input side of the amplifying element and including a first variable capacity element connected in series with a signal conductor and a second variable capacity element connected in parallel with the signal conductor, and a control circuit for controlling the changeable matching circuit. Based on a feedback signal, the control circuit applies DC bias voltages to the first variable capacity element and the second variable capacity element of the changeable matching circuit and also applies thereto a correction signal.

Abstract: An integrated circuit including a phase-locked loop (PLL) circuit responsive to a voltage controlled oscillator (VCO) frequency band selection circuit that provides automatic frequency band selection in real time to account for run-time variations, such as power supply and temperature variations over time. The PLL includes a charge pump and an LC tank circuit that provides the automatic frequency band selection based on a VCO control voltage signal supplied by the charge pump.