Abstract: Storing data to a storage medium with a device that has moving parts supported by a bearing and which maintains separation between opposing bearing surfaces in the bearing with a pressurized working fluid.

Abstract: A shaft, a circular plate portion and a cylindrical portion are integrally formed with one another through cutting operations to provide a rotor hub of a motor. An inner region on the lower surface of the circular plate portion is formed continuously with the outer peripheral surface of the shaft, and a hub thrust portion is provided in the inner portion so as to axially face a sleeve thrust portion on a sleeve main body. A stepped portion on the lower surface of the circular plate portion is disposed on the outer side of thrust dynamic pressure grooves on the sleeve thrust portion. In this manner, the stepped portion is disposed in a region where a thrust bearing portion is not provided, so that the hub thrust portion can be formed at a low cost in manufacturing the rotor hub by cutting.

Abstract: An information recording apparatus includes a medium for recording information; a head slider including a device for writing the information onto the medium and a reflective surface for reflecting light; a light emitting portion for generating emission light toward the reflective surface; a light receiving portion for detecting light reflected on the reflective surface; and a regulating mechanism for adjusting an amount of the emission light from the light emitting portion in a mode of information recording onto the medium in correspondence to a result of the detection.

Abstract: A magnetic head having an improved fringing field and overwrite capability, and a method of making the same, are described.

Abstract: A transducing head includes a substrate, a writer positioned upon the substrate, and a reader positioned adjacent the writer. The writer is in electrical contact with the substrate.

Abstract: A tape recording head is provided comprising a support plate having a contoured surface with an opening in the contoured surface which allows head chips to protrude far enough to allow proper head tape contact for recording. The support plate is fixed on a coarse actuator so that the support plate and coarse actuator move together perpendicular to the motion of the recording tape. The head chips comprising rowbar substrates containing a multiplicity of recording elements are supported on a carrier mounted on a fine actuator and are not fixed to the support plate to allow low mass fine actuation.

Abstract: A micro-actuator for use with an HGA and/or disk drive device (e.g., a small platform disk drive device) with the micro-actuator having a reduced mass suitable for improving shock performance, and/or methods of making the same are provided. In certain example embodiments, the micro-actuator may comprise a substantially U-shaped frame including a cavity capable of receiving a slider, with the frame including two side arms and a bottom support arm at least partially defining the cavity. The bottom support arm may have a reduced mass capable of providing improved shock performance and capable of conveying a high resonance frequency response at a low gain. The bottom support arm may be, for example, substantially rectangle shaped, substantially I-shaped, toothed, etc. Also, the bottom support arm may be less thick than the side arms.

Abstract: A thin-film magnetic head which can keep performances from fluctuating, while restraining an organic insulating material from peeling off is provided. The thin-film magnetic head comprises a lower magnetic pole layer, an upper magnetic pole layer and a first thin-film coil. A resist film made of an organic insulating material is interposed between turns adjacent to each other in the lead constituting the first thin-film coil. The first thin-film coil has a minimum width part and a maximum width part. The minimum width part is arranged closer to an air bearing surface than is a second upper magnetic pole part, while the whole upper face of the minimum width part is covered with the resist film. The maximum width part is arranged on the side farther from the air bearing surface than is the second upper magnetic pole part, while the upper face of the maximum width part is formed with a resist-uncoated area free of the resist film.

Abstract: A read head and a magnetic hard disk drive having a read head layer stack which has been partially milled to within a partial milling range to form a shaped junction and a hard bias layer which is in contact with the shaped junction of the wafer stack.

Abstract: There is provided a practical magnetoresistance effect element which has an appropriate value of resistance, which can be sensitized and which has a small number of magnetic layers to be controlled, and a magnetic head and magnetic recording and/or reproducing system using the same. In a magnetoresistance effect element wherein a sense current is caused to flow in a direction perpendicular to the plane of the film, if a pinned layer and a free layer have a stacked construction of a magnetic layer and a non-magnetic layer or a stacked construction of a magnetic layer and a magnetic layer, it is possible to provide a practical magnetoresistance effect element which has an appropriate value of resistance, which can be sensitized and which has a small number of magnetic layers, while effectively utilizing the scattering effect depending on spin.

Abstract: A first pinned magnetic sublayer 4a has a multilayered structure including a first insertion subsublayer disposed between a lower ferromagnetic subsublayer and an upper ferromagnetic subsublayer. The first insertion subsublayer has an average thickness exceeding 3 ? and 6 ? or less. This results in an interlayer coupling magnetic field Hin lower than a known art while RA and the rate of resistance change (?R/R) substantially identical to those of the known structure are maintained.

Abstract: A free magnetic layer of a tunnel-effect type magnetic sensor is formed on an insulating barrier layer made of Mg—O, and the free magnetic layer includes an enhancement layer, a first soft magnetic layer, a non-magnetic metal layer, and a second soft magnetic layer, which are laminated in that order from the bottom. For example, the enhancement layer is formed of Co—Fe, the first and the second soft magnetic layers are formed of Ni—Fe, and the non-magnetic metal layer is formed of Ta. The average thickness of the first soft magnetic layer is formed in the range of 5 to 60 ?. Accordingly, a high resistance change rate (?R/R) can be obtained.

Abstract: A magnetic memory device includes a magnetoresistive element and a first wiring layer. The magnetoresistive element includes a fixed layer, a recording layer, and a non-magnetic layer interposed therebetween. The first wiring layer extends in a first direction and generates a magnetic field for recording data in the magnetoresistive element. The recording layer includes a base portion extending in a second direction rotated from the first direction by an angle falling within a range of more than 0° to not more than 20°, and first and second projections projecting from the first and second sides of the base portion in a third direction perpendicular to the second direction. The third and fourth sides of the base portion are inclined with respect to the third direction in the same rotational direction as a rotational direction in which the second direction is rotated.

Abstract: A current-perpendicular-to-plane (CPP) magnetoresistance sensor and a method for forming a current-perpendicular-to-plane (CPP) magnetoresistance sensor. The method includes providing a ferromagnetic shield layer and disposing one or more seed layers on the ferromagnetic shield layer. The method also includes disposing a pinning layer on the one or more seed layers, wherein the pinning layer excludes PtMn, and disposing a pinned layer on the pinning layer. The shield layer, each of the one or more seed layers, the pinning layer, and the pinned layer are comprised of compounds having face-centered-cubic structures.

Abstract: Embodiments of the present invention pertain to a magnetic head that includes negative expansion material. According to one embodiment, the magnetic head includes a read element, a substrate, and at least a partial layer of negative expansion material to control, at least in part, a fly height between an air bearing surface associated with the magnetic head and a disk surface. The material is manganese nitride based and non-insulating and the layer of negative expansion material is parallel to the substrate, according to one embodiment.

Abstract: A protective device for a controlling system of a sewage pump has a protective circuit to protect a start capacitor and to avoid the start capacitor from burnout when an overload is occurred by actuating power source (ON status) or a transient voltage is occurred by malfunction of a controlling circuit. Therefore, the start capacitor is certainly protected and significantly improved in lifespan.

Abstract: A circuit interrupter for interrupting current on a line conductor is provided. The circuit interrupter includes separable contacts, a trip mechanism, a bimetal, a microprocessor, a series arc detection sequence, a low-pass filter circuit, and a high-pass filter circuit. The trip mechanism selectively opens the separable contacts when activated. The series arc detection sequence is resident on the microprocessor and includes a plurality of series fault detection algorithms. The low-pass filter circuit provides a low-pass signal to the series arc detection sequence. The high-pass filter circuit provides a high-pass signal to the series arc detection sequence. The sequence selects a particular algorithm from the plurality of algorithms based on the low-pass signal. The sequence calculates a plurality of statistical features from the high-pass signal and sends an output signal to activate the trip mechanism based on a comparison of the plurality of statistical features to the particular algorithm.

Abstract: Data transmission circuit with ESD protection comprises a first set of data lines and a second set of data lines; a first set of ESD protection components coupled to the first set of data lines; a second set of ESD protection components coupled to the second set of data lines; a first current path coupled to the first set of ESD protection components for dispensing the ESD current; and a second current path coupled to the second set of ESD protection components for dispensing the ESD current.

Abstract: The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging.

Abstract: An ESD network. The ESD network including a redundant voltage clamping element in series with a first voltage clamping element between two voltage pads. The ESD network may be connected to a power voltage pad or a signal voltage pad either directly or through a dummy voltage pad. The voltage clamping elements may further comprise an array of unit cells wherein the array is electrically equivalent to single large transistors currently used in ESD networks. By creating an ESD network as an array of unit cells, benefits greater than those obtained by using a single transistor as a clamping or a trigger element are realized such as increased ballast resistance and less overall damage to the circuitry resulting from cosmic rays and particles.

Abstract: In one aspect, a method for protection of an integrated circuit device includes but is not limited to detecting a first current in the integrated circuit device, wherein the first current is caused by a second current; and shunting the second current away from the integrated circuit device in response to detecting the first current. Such detecting may include but not be limited to detecting the first current by detecting a voltage drop across a sensing resistor, which may include but not be limited to using at least two sensing transistors. Such shunting may include but not be limited to using at least one shunting transistor.

Abstract: An electrostatic discharge protection circuit protects the internal circuits of a semiconductor. The electrostatic discharge protection circuit includes a first electrostatic protection unit connected to a power source supply pad. The first electrostatic protection unit discharges an ESD current into the power source supply pad when an ESD is introduced into the input/output pad, and generates a first driving voltage by utilizing the ESD current flow through a voltage-drop unit. A driver driven by the first driving voltage generates a second driving voltage by an ESD current. A second electrostatic protection unit discharges the introduced ESD current into the power source supply pad by the second driving voltage such that a voltage applied to a gate of the first NMOS transistor is reduced.

Abstract: A method of operating a relay device, the method comprising the steps of: providing main circuit-breakers and a bus-tie-breaker connecting the main-circuit-breakers; defining a partial-differential-zone comprising a main circuit breaker and the bus-tie breaker; assigning a first value to the direction of the fault current flowing into the partial differential zone; -assigning a second value to the direction of the fault currents flowing out of the partial-differential-zone, wherein the first value is not equal to the second value; -comparing the values assigned to the fault currents; determining if the fault currents are flowing into the partial differential zone; and determining if at least two of the fault-currents is flowing in a different direction with respect to the partial-differential-zone wherein one of the fault currents is flowing into the partial-differential-zone and one of the fault currents is flowing out of the partial differential zone.

Abstract: A method of protecting a circuit having power switching devices that includes communicating a current in at least one secondary switching device to at least one master switching device and determining a presence of a fault condition within at least a first zone based at least in part upon characteristics of the current in the at least one secondary switching device communicated to the at least one master switching device to perform differential protection.

Abstract: A protection system for a power distribution system with one or more zones that includes at least one power-switching device connected to a power or current sensing device and a communications device. The power-switching device is communicatively coupled to at least one processing device. The at least one processing device is adapted to execute a plurality of protective functions for a zone based on information of power conditions within the zone and predetermined protective requirements of the zone.

Abstract: A method of operating a relay device, the method comprising the steps of: computing positive-sequence first and second current-phasor for the first and second main circuit-breakers and computing currents from phasors, and the bus-tie-breaker; computing positive-sequence voltage for the bus-tie-breaker; triggering a method when at least one fault current at the bus-tie-breaker exceeds a threshold, without the presence of a fault on one of the feeders; determining whether the fault is internal or external, wherein the fault is internal if the positive-sequence current of the first and second main circuit breakers is in phase; and wherein if the positive-sequence current through the first main circuit breaker is not in-phase with the positive-sequence current through the second main circuit breaker, the fault is external to the bus; determining whether the fault is on a first or second side of the tie circuit; and locating the fault.

Abstract: A field device detects the presence of terminal leakage between a first terminal and a second terminal in the terminal block area of the field device using a voltage variation ratio that is based on variations in a terminal voltage located across output terminals of a field device and variations in a current regulation voltage located within a current regulation circuit. Preferable, the field device measures an initial voltage variation ratio ?0 and a subsequent voltage variation ratio ?t. Based on the initial voltage variation ratio ?0 and the subsequent voltage variation ratio ?t, the terminal leakage existing between the first terminal and the second terminal can be calculated.

Abstract: A battery pack including at least a battery cell and a protection circuit for shutting off a overcurrent discharge, comprising a discharge control switch connected between a negative terminal of the battery cell and a external minus terminal configured to close after the detection of an abnormal discharge shut-off condition. A shut-off holding unit is configured to maintain a discharge shut-off condition after the detection of an abnormal discharge shut-off condition due to the shorting or connection of a low resistance between a external plus terminal and a external minus terminal of the battery pack, and a releasing unit configured to release the discharge shut-off condition maintained by the shut-off holding unit by applying a predetermined voltage between the external plus terminal and the external minus terminal of the battery pack. Additionally, the discharge control switch is one of a mechanical switch, a transistor, and a field effect transistor.

Abstract: Systems and methods are disclosed for compensating electrical leakage and detecting balanced electrical leakage for a machine hosting an HV system. In one embodiment, a fault detection and compensation system includes a DC power supply electrically referenced to a machine frame, a leakage correction switch connected to the machine frame, a current source controlled by the leakage correction switch, and a voltage measuring device that measures an offset voltage reflecting whether the HV system is in an unbalanced fault condition. The fault detection and compensation system further includes a leakage detection and compensation controller that compensates for the unbalanced fault condition by controlling the leakage correction switch and the current source.

Abstract: An apparatus for protecting a device against an over-voltage condition that is in excess of its breakdown voltage includes a detector for detecting the over-voltage condition and a protection circuit for protecting the device in response to detection of the over-voltage condition. The protection circuit may include a transmission gate and a PMOS transistor for producing a protection signal. The protection signal may be applied to a gate and/or a drain and/or a source and/or a well of the device such that a voltage across the device does not exceed the breakdown voltage. The protection signal may be derived from the over-voltage condition independent of whether a supply of power to the device is present.

Abstract: An over-voltage protection arrangement (1) for protecting an electric device from over-voltages, the arrangement comprising an input voltage terminal (2), to be connected to a voltage feed, and an output voltage terminal (3), to be connected to the electric device to be protected, whereby the arrangement (1) is adapted to protect the electric device from voltages on the voltage feed deviating from a predefined threshold range, the arrangement further comprising a field effect transistor (4) connected in between the input terminal (2) and the output terminal (3) so as to enable an electric connection between said terminals (2, 3). The arrangement (1) is distinguished by: at least one trigger circuit (6a, 6b) being adapted to respond to a trigger voltage, a voltage on the voltage feed deviating from the threshold range, by controlling the field effect transistor (4) to throttle the electric connection between the input (2) and output (3) terminals.

Abstract: A circuit for protecting a motherboard of a computer includes a first transistor (Q1) and a second transistor (Q2). A CPU with a CPU voltage terminal (10) configured for electrically connecting to a power supply is mounted on the motherboard. A gate of the first transistor is connected to the CPU voltage terminal. A source of the first transistor is connected to ground. A gate of the second transistor is connected to a drain of the first transistor through a node (11). The node is at low level when the computer is off. A drain of the second transistor is connected to a control signal terminal (PWRBTN#) from the computer. When the computer is turned on and the CPU voltage terminal is not connected to the power supply and is at low level, the control signal terminal turns to low level from high level to turn off the computer.

Abstract: A fault detection circuit and a short-circuit detection circuit for a Cold Cathode Fluorescent Lamp (CCFL) driver integrated circuit having a power bridge and a CCFL load are disclosed that includes a reference circuit operable to generate a reference current in response to an external component, a replica component having a dimension substantially less than the components of the power bridge, a multiplexer circuit, and a comparator circuit. The replica component and the multiplexer circuit pass the reference current and the replica current to the comparator circuit respectively.

Abstract: A method and apparatus providing automatic circuit breaker identification to an electronic trip unit including: a mounting plate with mechanical means to releasably engage said electronic trip unit employing a microcontroller; an electronic module embedded in the mounting plate containing a non-volatile memory device, said device containing data identifying the circuit breaker type and ratings, and in operable communication with the electronic trip unit microcontroller, where the microcontroller reads the identification data from the non-volatile memory, the microcontroller is programmed to configure its overcurrent protection algorithms to match the characteristics of the circuit breaker.

Abstract: A rating plug that, in addition to setting the percentage de-rating on the voltage conditioning (i.e., gain/filter) circuit, by controlling the operational amplifier gain with analog switches in series with the opamp feedback loop, provides breaker frame and/or sensor information to a microprocessor.

Abstract: A method and apparatus providing automatic circuit breaker identification to an electronic trip unit includes a processor and a configuration module comprising configuration data identifying the particulars of a circuit breaker and that is in operable communication with the processor.

Abstract: The present disclosure describes a new pushbutton incorporated into new circuit configurations of an improved intelligent electronic device (“IED”), for use in power substation control systems. The new pushbutton is non-mechanical and configured to control a breaker, or other type of substation equipment, after an IED associated with the circuit breaker, or other type of substation equipment, fails to operate. In an embodiment, the new pushbutton may be a low-energy, membrane-type pushbutton. During normal operation, a microprocessor within the IED operates a solid-state device to control the operation of substation equipment. When the IED fails, manually depressing the new pushbutton bypasses the IED microprocessor and manually controls the substation equipment associated with the failed IED.

Abstract: A travel outlet device is for connecting between an adapter and a power cable. The travel outlet device includes a case, a PCB and at least one power outlet unit. The case is connected with a power input portion and a power output portion. The PCB has a surge-protected circuit and is disposed inside the case. The PCB is electrically connected with the power input portion and the power output portion. The power outlet unit is disposed with the case and electrically connected with the PCB. Accordingly, the travel outlet device can provide the adapter surge-protected function so that users can get more power outlet units to connect to other electric equipments for convenient use.

Abstract: A circuit board, including a static electricity protection conductor formed around a protection target to be protected from static electricity, the static electricity protection conductor having one or more projections and being grounded at one or more points.

Abstract: An exemplary connecting structure (30, 50) is used to electrically connect two conductive members (32, 34, 52, 54). The connecting structure includes an adhesive layer (36, 56) and a conductive element (40, 60). The adhesive layer is used to connect the conductive members and defines a through hole (38, 58). The at least one conductive element is received in the through hole. The at least one conductive element is electrically connected to the conductive members respectively. The present invention also provides a connecting method to make the connecting structure.

Abstract: A high voltage generating circuit includes a boosting portion (e.g., a trigger coil (22)) for boosting DC voltage delivered from a DC power supply (26) so as to deliver high voltage at a secondary side, a switching element (e.g., a MOS FET (23)) for turning on and off current flowing in the primary side of the boosting portion, and a pulse signal generating portion (24B) for generating a pulse signal for controlling on and off of the switching element.

Abstract: An apparatus for interfering with locomotion of a target by conducting a current through a load that includes an ionizable path. The apparatus includes, according to various aspects of the present invention, an energy source, an ionization detector, a charge detector, a controller, and a pulse generator. The controller determines, in response to the detector and by trial and error, a respective quantity of energy for each pulse of a plurality of pulses to be generated. For each pulse of the plurality, the pulse generator receives the respective quantity of energy from the energy source, provides in response to the quantity of energy a respective voltage to ionize the ionization path, and provides the current through the load. The charge detector detects a charge provided through the load. The processor sets the voltage for charging for a next pulse in response to the charge detected by the charge detector.

Abstract: A method of manufacturing a circuit board embedding a thin film capacitor, the method including: forming a sacrificial layer on a first substrate; forming a dielectric layer on the sacrificial layer; forming a first electrode layer on the dielectric layer; disposing the first substrate on the second substrate in such a way that the first electrode layer is bonded to a top of a second substrate; decomposing the sacrificial layer by irradiating a laser beam onto the sacrificial layer through the first substrate; separating the first substrate from the second substrate; and forming a second electrode layer on the dielectric layer.

Abstract: A method of forming a metal-insulator-metal (MIM) capacitor includes forming a first planar dielectric layer with a first metallization layer therein; forming a first passivation layer on top thereof; forming a planar conductive layer above the first passivation layer; patterning and selectively removing the conductive layer up to the first passivation layer in designated areas to form a set of conductive features; patterning and conformally coating the set of conductive features and the exposed first passivation layer with a high strength dielectric coating; disposing a second dielectric layer above the first passivation layer and enclosing the set of conductive features; patterning and selectively removing portions of the second substrate to form channels and trenches; performing a dual-Damascene process to form a second metallization layer in the trenches and channels and to form an upper conductive surface above the high strength dielectric coating.

Abstract: A common centroid symmetric structure capacitor is provided, which includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer. The first metal layer is adjacent to the second metal layer, the third metal layer is adjacent to the first metal layer, the fourth metal layer is adjacent to the second metal layer, and the first metal layer is symmetric to the fourth metal layer, the second metal layer is symmetric to the third metal layer. Each of the metal layers has two sets of metal wires, each set has a plurality of metal wires, and each of the metal wires in each set is arranged in an interlaced manner.

Abstract: A multilayer capacitor array having a plurality of multilayer capacitor devices formed in a single multilayer structure, the multilayer capacitor array including: a capacitor body formed by depositing a plurality of dielectric layers and having first and second side surfaces opposite to each other; a plurality of first polarity internal electrodes and second polarity internal electrodes, disposed oppositely to each other in the capacitor body, interposing the dielectric layer there between, and formed of a single electrode plate comprising a single lead, respectively; and a plurality of first polarity external electrodes and second polarity external electrodes, formed on the first side surface and second side surface, respectively, and connected to a correspondent polarity internal electrode via the lead, the first polarity external electrode formed on the first side surface and the second polarity external electrode formed on the second side surface, wherein the numbers of the first polarity external electro

Abstract: A terminal to, most commonly, a ceramic capacitor, most commonly a multilayer ceramic capacitor (MLCC), is formed by electroless plating, also known as electroless deposition or simply as electrodeposition. In the MLCC having a multiple parallel interior plates brought to, and exposed at, at least one, first, surface, an electrically-conductive first-metal layer, preferably Cu, is electrolessly deposited upon this first surface directly in contact with, mechanically connected to, and electrically connected to, the edges of these interior plates. Lateral growth of the electrolessly-deposited first-metal is sufficient to span from exposed plate to exposed plate, electrically connecting the plates. One or more top layers, preferably one of Ni and one of Sn and Pb, are deposited, preferably by plating and more preferably by electrolytic plating, on top of the electrolessly-deposited Cu.

Abstract: A semiconductor device has a MIM capacitor including a first insulating film formed on a semiconductor substrate, a lower electrode composed of a first metal film formed on the first insulating film, a capacitor insulating film formed on the lower electrode, and an upper electrode composed of a second metal film formed on the capacitor insulating film. The semiconductor device further has a lower interconnect composed of the first metal film formed on the first insulating film and an upper interconnect composed of the second metal film formed on the lower interconnect. The upper interconnect and the upper electrode are formed integrally.

Abstract: A face-centered cubic structure capacitor is provided, which includes a first metal layer, a second metal layer, and a connection layer. The first metal layer comprises a plurality of first metal wires, a plurality of second metal wires, and a plurality of first metal blocks. The first and second metal wires are intercrossed with each other to form a grid structure, and each of the first metal blocks is disposed in each grid of the grid structure. The second metal layer comprises a plurality of third metal wires, a plurality of fourth metal wires, and a plurality of second metal blocks. The third and fourth metal wires are intercrossed with each other to form a grid structure, and each of the second metal blocks is disposed in each grid of the grid structure. The connection layer comprises a plurality of third metal blocks and a plurality of fourth metal blocks.

Abstract: There are provided a capacitor and a thin film capacitor-embedded multi-layer wiring board. The capacitor includes: first and second electrodes connected to first and second polarities; a dielectric layer formed therebetween; and at least one floating electrode disposed inside the dielectric layer and having overlaps with the first and second electrodes. The wiring board includes: an insulating body having a plurality of insulating layers thereon; a plurality of conductive patterns and conductive vias formed on the insulating layers, respectively, to constitute an interlayer circuit; and a thin film capacitor embedded in the insulating body, wherein the thin film capacitor includes a first electrode layer, a first dielectric layer, at least one floating electrode layer, a second dielectric layer and a second electrode layer sequentially formed, and wherein the first and second electrode layers are connected to the interlayer circuit and the floating electrode layer is not directly connected thereto.