Patents Issued in July 17, 2008
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Publication number: 20080169839Abstract: A design structure for an integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.Type: ApplicationFiled: September 6, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wagdi W. Abadeer, George M. Braceras, Albert M. Chu, John A. Fifield, Harold Pilo, Daryl M. Seitzer
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Publication number: 20080169840Abstract: A semiconductor device including an AND-NOR composite gate of which AND unit is supplied with input signals IN and VDD and NOR unit is supplied with an inverted signal EB of an enable signal E, and an AND-NOR composite gate of which AND unit is supplied with an input signal INB and an enable signal E and NOR unit is supplied with VSS. These gates are inserted into a path to which the input signals IN and INB are supplied. Thereby, a symmetric property of a complimentary signal can be retained. Further, outputs of the AND-NOR composite gates are fixed irrespective of a logical level of the enable signal E. Thus, a sub-threshold current also is inhibited.Type: ApplicationFiled: July 23, 2007Publication date: July 17, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Junichi Hayashi, Hiromasa Noda
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Publication number: 20080169841Abstract: A method to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage, comprising the steps of: deriving a local clock activation signal from an external clock activation signal, wherein said local clock activation signal changes its value every cycle the external clock activation signal indicates a propagation, propagating the data signal and the local clock activation signal synchronously cycle by cycle from a particular stage to a succeeding stage whenever a local clock activation signal at the particular stage by derivation from the clock activation signal or by propagation through the synchronous circuit changes its value between two successive cycles, in order to propagate the data signal and the local clock activating signal within the same clock domain through the clock gated synchronous circuit.Type: ApplicationFiled: September 6, 2007Publication date: July 17, 2008Inventors: Tobias Gemmeke, Jens Leenstra, Jochen Preiss
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Publication number: 20080169842Abstract: A design structure to reduce power consumption within a clock gated synchronous circuit, said synchronous circuit comprising at least two successive stages, wherein each stage if activated propagates a data signal cycle by cycle to a succeeding stage the two successive stages comprising at least a control register, a data register and a local clock buffer (LCB) each, wherein each stage if activated propagates a data signal stored within the data register cycle by cycle to a data register of a succeeding stage.Type: ApplicationFiled: September 6, 2007Publication date: July 17, 2008Inventors: Tobias Gemmeke, Jens Leenstra, Jochen Preiss
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Publication number: 20080169843Abstract: A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse, and a design structure on which the subject circuit resides is provided. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.Type: ApplicationFiled: October 16, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony Gus Aipperspach, David Howard Allen, Louis Bernard Bushard, Phil Christopher Felice Paone, Gregory John Uhlmann
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Publication number: 20080169844Abstract: An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.Type: ApplicationFiled: January 15, 2007Publication date: July 17, 2008Applicant: International Business Machines CorporationInventors: Wagdi W. Abadeer, Jeffrey S. Brown, Albert M. Chu, John A. Fifield
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Publication number: 20080169845Abstract: A CMOS image sensor includes a photosensitive region for collecting charge in response to incident light; a charge-to-voltage mechanism for receiving the charge from the photosensitive region and converting the charge to a voltage; an amplifier for receiving and amplifying the voltage; a sample and hold circuit includes (i) a first capacitor one for receiving the voltage and a second capacitor for receiving a reset level; a first bus for receiving the voltage from the first capacitor and a second bus for receiving the reset level from the second capacitor; a differential difference amplifier for receiving the image voltage and the reset level and for determining a difference level between the image voltage and the reset level and for removing offset of the amplifier; and first and second switches respectively connected to the first and second bus for providing an electrical path for removing charge from each bus.Type: ApplicationFiled: January 12, 2007Publication date: July 17, 2008Inventor: Weize Xu
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Publication number: 20080169846Abstract: A device and method are disclosed for synthesizing a waveform having pulse segments. An exemplary generator can include units having a time delay element and pulse generator generating the pulse segments. An input divider divides an input signal into signal instances that propagate through the units and an output combiner combines pulse segments to form the waveform. The pulse generators include a sharpening circuit for sharpening a rising edge and a falling edge of the pulse segments. The sharpening circuit includes a tunable delay element coupled to a non-linear transmission line (NLTL). Another NLTL can be coupled in parallel with the tunable delay element and the first NLTL. The NLTLs include input sections coupled to anodes or cathodes of Schottky diode elements, and the respective cathodes or anodes are coupled to a signal ground.Type: ApplicationFiled: January 11, 2007Publication date: July 17, 2008Applicant: Northrop Grumman CorporationInventors: Xing Lan, Mark Kintis, Flavia S. Fong
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Publication number: 20080169847Abstract: A driver includes an output circuit which converts an input signal to a predetermined output waveform and outputs the predetermined waveform to first and second output terminals, a first output resistor having one end connected to the first output terminal, a second output resistor having one end connected to the second output terminal, an output resistor switch element having one end connected to the other end of the first output resistor, and having the other end connected to the other end of the second output resistor, and a 2-input-2-output amplifier which receives first and second input voltages corresponding to voltages at both ends of the output resistor switch element, and outputs voltages, which are produced by amplifying voltage differences between a reference voltage and the first and second input voltages, a high impedance state being set between both ends of the output resistor switch element.Type: ApplicationFiled: January 10, 2008Publication date: July 17, 2008Inventor: Kyoichi TAKENAKA
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Publication number: 20080169848Abstract: A novel clock splitter that has a local internal clock frequency-divider is presented. The clock splitter comprises an oscillator clock splitter, wherein the oscillator clock splitter splits an oscillator clock signal into a B clock and a C clock; a clock frequency-divider, wherein the clock frequency-divider selectively suppresses clock pulses in the C clock to generate a slower C clock signal that is slower than the oscillator clock; and a B/C clock order logic, wherein the B/C clock order logic phase shifts the C clock relative to a B clock. The clock frequency-divider may selectively suppress pulses in the B clock to generate a slower B clock signal. The slower B and C clock signals may have a same or different frequency. In one embodiment, the clock splitter is located at a terminal leaf of a clock tree.Type: ApplicationFiled: January 17, 2007Publication date: July 17, 2008Inventors: Steven Michael Douskey, Matthew Roger Ellavsky
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Publication number: 20080169849Abstract: A system and method for effectively utilizing a dual-mode phase-locked loop to support a data transmission procedure includes a voltage controlled oscillator that generates a receiver clock signal in response to VCO input control signals. A binary phase detector generates a BPD output signal during a BPD mode by comparing input data and the receiver clock signal. In addition, a lock-assist circuit generates a PFD output signal during a PFD mode by comparing a reference signal and a divided receiver clock signal. A loop filter performs a BPD transfer function to generate a VCO input control signal from the BPD output signal during the BPD mode. The same loop filter also performs a PFD transfer function to generate the VCO input control signal from the PFD output signal during the PFD mode.Type: ApplicationFiled: July 16, 2007Publication date: July 17, 2008Inventor: Jeremy Chatwin
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Publication number: 20080169850Abstract: A phase-locked loop circuit comprises a phase frequency detector, a charge pump associated with a loop capacitance, and a voltage controlled oscillator. The phase frequency detector receives a reference clock signal on a first input and a feedback signal from the voltage controlled oscillator on a second input. The charge pump receives control inputs from outputs of the phase frequency detector. Pulse duration detecting circuitry limits charge and discharge current pulses supplied to the loop capacitance by the charge pump to durations less than predetermined permissible durations.Type: ApplicationFiled: January 9, 2008Publication date: July 17, 2008Applicant: TEXAS INSTRUMENTS DEUTSCHLAND GMBHInventor: Gerd Rombach
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Publication number: 20080169851Abstract: In a delay locked loop, a phase detector compares the phases of an input signal and an output signal; a delay line delays the input signal, wherein the delay line includes a plurality of unit delay elements connected in series and the value of the unit delay of each of the unit delay elements is adjusted by a control signal; a multiplexer selects a number of delay stages of the unit delay elements according to the phase comparison result and generates the output signal. The control signal is related to a clock information signal. When the input signal is high frequency, the value of the unit delay would be small; and when the input signal is low frequency, the value of the unit delay would be large.Type: ApplicationFiled: July 9, 2007Publication date: July 17, 2008Applicant: NANYA TECHNOLOGY CORPORATIONInventor: Wei-Li Liu
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Publication number: 20080169852Abstract: A delay locked loop circuit and a method for controlling the same including a delay locked loop (DLL) circuit for receiving an external clock signal and generating an internal clock signal synchronized to the external clock signal includes at least two delay chains having different types of delay cells for delaying the external clock signal. Thus, the layout area and power consumption can be reduced, and logic failures can be prevented or minimized by replacement or compensation of the main delay cells.Type: ApplicationFiled: January 4, 2008Publication date: July 17, 2008Inventors: Jun-Bae Kim, Chang-Hyung Bae
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Publication number: 20080169853Abstract: An apparatus for detecting a lock failure and correcting a duty cycle includes a lock failure detector configured to determine whether a first internal clock signal is locked to a second internal clock signal and to output a lock failure signal in response thereto, a duty cycle correction unit configured to correct a duty cycle of an external clock signal responsive to the lock failure signal and to output the duty-cycle-corrected external clock signal as the first internal clock signal, and a delay unit configured to generate the second internal clock signal by delaying the first internal clock signal.Type: ApplicationFiled: January 9, 2008Publication date: July 17, 2008Inventors: In-soo Park, Young-soo Sohn
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Publication number: 20080169854Abstract: A trimming system for determining a trim solution for a semiconductor device includes an internal value generating circuit for generating an internal value based upon a counter value. The relationship between the internal delay value and an external reference is compared to determine if the counter value is a possible trim solution, while predetermined counter values are excluded as a trim solution.Type: ApplicationFiled: January 16, 2007Publication date: July 17, 2008Applicant: Infineon Technologies North America Corp.Inventor: Steffen Loeffler
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Publication number: 20080169855Abstract: An apparatus for correcting a duty cycle of an input clock signal to generate a digitally corrected clock signal includes a duty cycle detector, an analog duty cycle correcting unit, and a digital duty cycle correcting unit. The duty cycle detector generates a duty cycle signal indicating a respective duty cycle of the digitally corrected clock signal. The analog duty cycle correcting unit adjusts a current flowing through a node to adjust the respective duty cycle of the input clock signal for generating an analog corrected clock signal at the node. The digital duty cycle correcting unit adjusts the respective duty cycle of the analog corrected clock signal according to the duty cycle signal for generating the digitally corrected clock signal.Type: ApplicationFiled: June 4, 2007Publication date: July 17, 2008Inventors: Won-Hwa Shin, Sung-Man Park, Kwang-Il Park
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Publication number: 20080169856Abstract: The present invention provides a current impulse generator that is fed by a high voltage source. The high voltage from the source creates an electric field which turns into a corona current by means of a corona current source. The corona current source charges a floating electrode with electrostatic energy which is rapidly discharged by means of a discharge switch into a spherical electrode producing a current impulse. The spherical electrode transmits the current impulse to an antenna which emits an electromagnetic wideband energy beam which actuates on electric triggers from a distance.Type: ApplicationFiled: August 3, 2007Publication date: July 17, 2008Inventors: Francisco Jose Roman C., Jose Felix Vega S.
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Publication number: 20080169857Abstract: A hierarchical and modular clock programmable delay circuit structure is described that can achieve almost unlimited fine resolution and unlimited delay range. The same circuit may also be applied to critical circuits that require fine adjustment in timing applications. The modular design allows the circuit and its layout to be synthesized by software to achieve desired delay resolution and range. Constant capacitive load of internal node enhances the linearity of achieved delay by digital controls.Type: ApplicationFiled: January 11, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charlie C Hwang, Phillip J. Restle, Leon J. Sigal
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Publication number: 20080169858Abstract: The present invention discloses a source driver and a level shifting apparatus thereof. The level shifting apparatus is used for shifting a level of a data signal. The level shifting apparatus comprises a first charge pump and a level shifter. The first charge pump supplies a first pumped voltage based on the data signal. The level shifter generates a level-shifted data signal based on the first pumped voltage.Type: ApplicationFiled: January 12, 2007Publication date: July 17, 2008Applicant: HIMAX TECHNOLOGIES LIMITEDInventor: Yu-Jui CHANG
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Publication number: 20080169859Abstract: A sub-harmonic mixer includes a first transistor having a source and a drain and a second transistor having a source connected to the source of the first transistor and a drain connected to the drain of the first transistor. A mixing transistor is configured to be biased in a linear operating region. The mixing transistor includes a drain coupled to the sources of the first transistor and the second transistor. The mixing transistor has its drain driven by a signal at twice a local oscillator (LO) frequency and its gate driven by a radio frequency (RF) signal while the mixing transistor is biased in the linear region such that a process of frequency doubling and mixing are performed simultaneously.Type: ApplicationFiled: January 12, 2007Publication date: July 17, 2008Inventors: ALBERTO VALDES GARCIA, Chinmaya Mishra, Scott Kevin Reynolds
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Publication number: 20080169860Abstract: A multichip package in which characteristics of all semiconductor chips mounted thereon can be controlled in response to a change in temperature. The multichip package can include a substrate and a plurality of semiconductor chips that are sequentially stacked and mounted on the substrate. In this case, a temperature detection circuit may be provided on any one of the plurality of semiconductor chips. The semiconductor chips may be electrically connected to the temperature detection circuit that is provided on any one of the plurality of semiconductor chips, and share temperature data that can be obtained from the temperature detection circuit.Type: ApplicationFiled: December 28, 2007Publication date: July 17, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Ho Uk Song
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Publication number: 20080169861Abstract: The reference current source circuit 10 is provided with a current source circuit 1, a trimming fuse 3, a switching circuit 2 which connects/disconnects the current source circuit 1 and/from the trimming fuse 3, a NAND circuit 4 which controls the operation of the switching circuit 2, and a pull-down resistor R1 which connects one input terminal of the NAND circuit 4 to a GND terminal. The NAND circuit 4 controls the operation of the switching circuit 2 upon receipt of control signals S1 and S2 and also in accordance with a signal of the one input terminal of the NAND circuit 4 so as to connect the current source circuit 1 to the trimming fuse 3. This arrangement makes it possible to measure characteristics of a semiconductor integrated circuit after fuse trimming. In addition, it is possible to maintain the state after fuse trimming without the supply of a signal from outside. Moreover, a reference current source circuit which does not consume extra consumption current is realized.Type: ApplicationFiled: January 14, 2008Publication date: July 17, 2008Inventor: Takahiro INOUE
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Publication number: 20080169862Abstract: A semiconductor device and a method for controlling its patterns is described where the electrical characteristics of the patterns formed by a double patterning process may be individually controlled responsive to critical dimensions (CDs) of the patterns. The method includes controlling two or more patterns having different CDs to optimally operate the patterns. The patterns may be individually controlled by signals provided to the patterns on the basis of the pattern's CDs. The signals may be controlled by controlling the magnitudes or the application time of the signals provided to the respective patterns.Type: ApplicationFiled: November 12, 2007Publication date: July 17, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joon-Soo PARK, Gi-Sung YEO, Pan-Suk KWAK, Han-Ku CHO, Ji-Young LEE
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Publication number: 20080169863Abstract: In a semiconductor integrated circuit device including a charge pump circuit flowing an operating current therethrough, a current circuit is adapted to receive the operating current and a substantially constant current and generate an inverse relative to the operating current and the substantially constant current.Type: ApplicationFiled: October 29, 2007Publication date: July 17, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Ikuo FUKAMI
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Publication number: 20080169864Abstract: A boosting circuit comprises a first boosting cell row and a second boosting cell row. The boosting circuit further comprises an analog comparison circuit for comparing the potential of boosting cells on the same stage, and selecting and outputting the lower or higher of the potentials. The potential of an N well is controlled using the output potential of the analog comparison circuit. Thereby, the amplitude of an N well potential can be suppressed, and a single N well region can be shared.Type: ApplicationFiled: January 17, 2008Publication date: July 17, 2008Inventor: Seiji YAMAHIRA
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Publication number: 20080169865Abstract: An internal voltage generating circuit includes a first detector that compares an internal voltage and a first reference voltage to output a first detection signal. A second detector compares a supply voltage and a second reference voltage to output a second detection signal. A loop selection oscillator performs an oscillation operation in response to the first detection signal, selects a first loop or a second loop for performing the oscillation operation in response to the second detection signal, and outputs an oscillation signal. A charge pump performs a pumping operation according to the output of the loop selection oscillator and generates the internal voltage.Type: ApplicationFiled: July 16, 2007Publication date: July 17, 2008Applicant: Hynix Semiconductor Inc.Inventor: Myung Jin Kim
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Publication number: 20080169866Abstract: A combined charge storage and bandgap reference is disclosed. In one embodiment, a system comprises a bandgap reference circuit; a charge storage circuit, wherein an output of the bandgap reference circuit is provided as an input to the charge storage circuit; and a control circuit in communication with the bandgap reference circuit and the charge storage circuit. The control circuit is operative to control charging of the charge storage circuit by the output of the bandgap reference circuit and control selection of one of the output of the bandgap reference circuit and an output of the charge storage circuit. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.Type: ApplicationFiled: January 16, 2007Publication date: July 17, 2008Inventors: Bendik Kleveland, Thomas H. Lee
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Publication number: 20080169867Abstract: A design structure that includes at least one tunneling device voltage reference circuit for use in low voltage applications is disclosed. The tunneling device voltage reference circuit includes a pair of voltage dividing device stacks, one having a linear voltage output and the other having a non-linear voltage output. A feedback circuit supplies a regulated voltage to each of the voltage dividing stacks so that the output voltages of the two device stacks equalize. Once the feedback circuit has locked, any one of the device stack output voltages and the regulated voltage may be used as a voltage reference.Type: ApplicationFiled: September 6, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wagdi W. ABADEER, Albert M. Chu
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Publication number: 20080169868Abstract: In a layout structure capable of independent supply of a substrate or well potential from a power supply potential, further reduction in layout area is achieved. A reinforcing power supply cell is inserted in a cell line in which a plurality of cells are arranged in series. Each of the cells includes an impurity doped region for supplying a substrate or well potential NWVDD which is different from a positive power supply potential VDD to a p-type transistor arranging region. The reinforcing power supply cell includes a power supply impurity doped region to which an impurity doped region of an adjacent cell is electrically connected and a power supply wire provided in a wiring layer formed above the power supply impurity doped region and electrically connected to the power supply impurity doped region.Type: ApplicationFiled: January 11, 2008Publication date: July 17, 2008Inventor: Tetsurou TOUBOU
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Publication number: 20080169869Abstract: An integrated circuit that includes at least one tunneling device voltage reference circuit for use in low voltage applications is disclosed. The tunneling device voltage reference circuit includes a pair of voltage dividing device stacks, one having a linear voltage output and the other having a non-linear voltage output. A feedback circuit supplies a regulated voltage to each of the voltage dividing stacks so that the output voltages of the two device stacks equalize. Once the feedback circuit has locked, any one of the device stack output voltages and the regulated voltage may be used as a voltage reference.Type: ApplicationFiled: January 15, 2007Publication date: July 17, 2008Applicant: International Business Machines CorporationInventors: Wagdi W. Abadeer, John A. Fifield
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Publication number: 20080169870Abstract: A first transistor is provided in a first route and a second transistor is provided in a second route, the first route and the second route constituting a current mirror circuit. The sources of the transistors are grounded. In order to match VDS of the first transistor and that of the second transistor match each other, there are provided an operational amplifier receiving the drain voltages of the transistors, and a third transistor having a gate thereof connected to the output of the operational amplifier. The third transistor is provided in the first route. As a result, the current fed to the third transistor is controlled so that VDS of the first transistor and that of the second transistor match each other.Type: ApplicationFiled: March 20, 2008Publication date: July 17, 2008Applicant: ROHM CO., LTD.Inventors: Isao YAMAMOTO, Koichi MIYANAGA
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Publication number: 20080169871Abstract: The invention relates to a method for the filtering and analog/digital conversion of an incoming analog signal including an analog filtering of the incoming analog signal so as to filter the frequency components located outside a desired frequency band, and a conversion of the filtered analog signal to a digital signal. The digital signal is reformatted in a form that is substantially similar, at least in the desired frequency band, to the form of the incoming analog signal. A final digital filtering of the reformatted digital signal is performed so as to filter the frequency components located outside the desired frequency band.Type: ApplicationFiled: January 16, 2008Publication date: July 17, 2008Applicant: STMicroelectronics SAInventor: Loic Joet
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Publication number: 20080169872Abstract: A demodulator, chip and method for digitally demodulating an FSK signal utilizing a digital data transfer protocol and a digital demodulator circuit have been developed. The data-rate approaches the carrier-frequency. The one application for this technique is in the magnetically powered wireless systems such as biomedical implants and radio frequency identification (RFID) tags with high data rates above 1 Mbps. The demodulator circuit extracts the serial data bit-stream and a constant-frequency clock from an FSK carrier signal in the 1˜20 MHZ range, which can power the wireless system as well. The digital demodulator circuit is implemented entirely with digital circuitry and is called a digital-FSK (DFSK) demodulator.Type: ApplicationFiled: January 21, 2005Publication date: July 17, 2008Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Maysam Ghovanloo, Khalil Najafi
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Publication number: 20080169873Abstract: A high frequency signal detection circuit includes an input terminal for a high frequency signal to be detected, a switch transferring the high frequency signal as intermittent ringing signal to a first node in response to a pulse signal whose frequency is lower than that of the high frequency signal, a transistor amplifying the signal at the first node, and outputting to a second node, a bias generator generating a bias voltage by which the transistor is operated in its weak inversion region, a resonant circuit outputting the bias voltage to the first node, and resonating the high frequency signal, a capacitor removing a high frequency component of the signal at the second node; and a judgment circuit judging whether or not the high frequency signal is inputted by detecting the signal at the second node, which has the same frequency as the pulse signal.Type: ApplicationFiled: November 21, 2007Publication date: July 17, 2008Inventor: Hiroyuki Toda
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Publication number: 20080169874Abstract: An embodiment of the present invention provides an apparatus, comprising a power amplifier with a tunable impedance matching circuit including a plurality of tunable dielectric varactors and a DC voltage source interface capable of providing voltage to said plurality of saud tunable dielectric varactors.Type: ApplicationFiled: March 17, 2008Publication date: July 17, 2008Inventors: Cornelis Frederik du Toit, Deirdre A. Ryan
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Publication number: 20080169875Abstract: An analog level-shifting buffer for providing signal amplitude and/or common mode adjustment is disclosed. In one example, a receiver system may include a first amplification stage that is powered, for example, via an I/O power supply (e.g., VDDIO) and a second amplification stage that is powered, for example, via a core logic power supply (e.g., VDD). Arranged between the first and second amplification stages may be the analog level-shifting buffer. The analog level-shifting buffer may include a set of variable impedance elements for controlling the output common mode and output signal swing of the level-shifting buffer.Type: ApplicationFiled: January 15, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Songtao Xu
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Publication number: 20080169876Abstract: In one aspect, an operational amplifier is configured to form a quiescent current that is a ratio of a current of a current source of the operational amplifier and to provide a load current to a load that is not ratioed to the current of the current source.Type: ApplicationFiled: January 15, 2007Publication date: July 17, 2008Inventor: John D. Stone
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Publication number: 20080169877Abstract: A cascode-connected transistor includes a common-source transistor which receives an input signal, and a common-gate transistor which is connected to a drain terminal of the common-source transistor and outputs an output signal. A band-pass filter receives the output signal of the cascode-connected transistors. An adjustment circuit is interposed between the drain terminal and the gate terminal of the common-gate transistor, and adjusts the output impedance of the cascode-connected transistor.Type: ApplicationFiled: December 21, 2007Publication date: July 17, 2008Inventor: Seiichi Banba
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Publication number: 20080169878Abstract: A combiner includes a circulator having a series of at least three sequential ports such that a signal input into a port is transmitted as an output at the next sequential port. A bandpass filter has a pass band and is coupled to a first port of the circulator such that a signal in the pass band that is input to the filter is output at a second port of the circulator. A third port of the circulator is configured to be coupled to an input signal that is out of the pass band such that a signal input at the third port is reflected as an output from the first port by the bandpass filter to then be output at the second port. The signals input at the first and third ports are combined at the second port. This configuration might be used in a cascaded fashion for combining multiple signals, together with low loss.Type: ApplicationFiled: January 12, 2007Publication date: July 17, 2008Inventors: Giuseppe Resnati, Marco Santoniccolo, Stefano Galli
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Publication number: 20080169879Abstract: An embodiment of the present invention provides an apparatus, comprising a filter; and a matching network coupled to the filter, the matching network including a plurality of voltage tunable dielectric varactors.Type: ApplicationFiled: March 17, 2008Publication date: July 17, 2008Inventors: Cornelis Frederik du Toit, Deirdre A. Ryan
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Publication number: 20080169880Abstract: An embodiment of the present invention provides an apparatus, comprising a delay line and a matching network coupled to the delay line, the matching network including a plurality of voltage tunable dielectric varactors.Type: ApplicationFiled: March 17, 2008Publication date: July 17, 2008Inventors: Cornelis Frederik du Toit, Deirdre A. Ryan
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Publication number: 20080169881Abstract: An RF assembly of a multiport switch is disclosed. The RF assembly includes an RF cavity housing and a cover. The RF cavity housing includes a common port defined by a cavity in a surface of the RF cavity housing and at least another port defined by a trough in the surface of the RF cavity housing. The trough is connected to the cavity. When covered by the cover, the trough defines a channel connected at one end to the cavity. The distance between opposing surfaces of the RF cavity housing and the cover at a proximal end of the channel is smaller than the corresponding distance of a portion of the channel immediately adjacent the proximal end. A multiport switch having the RF assembly is also disclosed.Type: ApplicationFiled: January 17, 2007Publication date: July 17, 2008Applicant: AGILENT TECHNOLOGIES, INC.Inventors: Chee Leong TEH, Kim Yen ANG
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Publication number: 20080169882Abstract: A filter includes: a first acoustic wave filter having acoustic wave filters cascaded, an input stage of the acoustic wave filters including a first multimode filter; a second acoustic wave filter having acoustic wave filters cascaded, an input stage of these acoustic wave filters including a second multimode filter having an aperture length different from that of the first multimode filter, the second acoustic wave filter receiving an unbalanced in signal applied to the first acoustic wave filter, and having a pass band that does not overlap with that of the first acoustic wave filter.Type: ApplicationFiled: January 10, 2008Publication date: July 17, 2008Applicant: FUJITSU MEDIA DEVICES LIMITEDInventors: Satoru ONO, Osamu KAWACHI, Hidemitsu KUBOI, Kouta OHKUBO
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Publication number: 20080169883Abstract: An LC resonant circuit. The LC resonant circuit comprises an inductor and a conductor. The inductor is an electrode plate of a capacitor. The conductor is over, under, or on both sides of the inductor and used as the other electrode plate of the capacitor.Type: ApplicationFiled: June 26, 2007Publication date: July 17, 2008Inventors: Chia-Jen Hsu, Chuan-Jane Chao
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Publication number: 20080169884Abstract: A thin film bulk acoustic wave (BAW) resonator structure and filter which can be fabricated by inexpensive manufacturing techniques and in smaller size than conventional such products are to be provided. The BAW resonator structure and filter have a substrate, a first BAW resonator placed over the substrate, an acoustic reflection layer placed over the first BAW resonator and a second BAW resonator placed over the acoustic reflection layer, and the acoustic reflection layer is electroconductive. Herein, the acoustic reflection layer constitutes a first electrode, and this first electrode electrically connects and acoustically separates the first BAW resonator and the second BAW resonator.Type: ApplicationFiled: February 13, 2007Publication date: July 17, 2008Inventors: Hisanori Matsumoto, Atsushi Isobe, Kengo Asai
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Publication number: 20080169885Abstract: A piezoelectric thin-film resonator includes: a lower electrode provided on a substrate; a piezoelectric film provided on the lower electrode; an upper electrode provided on the piezoelectric film so as to face the lower electrode across the piezoelectric film to thus define a resonance portion; and a weight load film provided on the upper electrode, the weight load film being provided in the resonance portion and having an area smaller than that of the resonance portion.Type: ApplicationFiled: January 10, 2008Publication date: July 17, 2008Applicants: FUJITSU MEDIA DEVICES LIMITED, FUJITSU LIMITEDInventors: Masanori Ueda, Tokihiro Nishihara, Shinji Taniguchi, Tsuyoshi Yokoyama, Go Endo, Yasuyuki Saitou
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Publication number: 20080169886Abstract: In an acoustic wave filter device, a first filter circuit portion includes a first inductor provided in a series arm that couples an input terminal and an output terminal is serially connected to a first acoustic wave resonator, and a second filter circuit portion includes a second inductor provided in the series arm and second and third acoustic wave resonators and connected between one end and the other end of the second inductor and a ground potential. When the pass band center frequency is set as a first center frequency and the center frequency of a filter defined by the inductance of the first and second inductors and the capacitance of the first to third acoustic wave resonators is set as a second center frequency f2, f1 is less than f2.Type: ApplicationFiled: March 26, 2008Publication date: July 17, 2008Applicant: MURATA MANUFACTURING CO., LTD.Inventor: Katsuhito KURODA
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Publication number: 20080169887Abstract: An apparatus and method for attenuating selected frequency bands in a microstrip filter having a plurality of microstrip resonators. The filter comprises plural resonators, a first of the plural resonators is operatively connected to a first feed point and a second of the plural resonators is operatively connected to a second feed point. A third of the plural resonators is a half wavelength resonator and may be operatively connected to the first, second and/or other plural resonators. The third resonator may also comprise a plurality of resonators whereby the position and number of the third resonator is a function of a predetermined rejected frequency range.Type: ApplicationFiled: January 16, 2007Publication date: July 17, 2008Applicant: HARRIS CORPORATIONInventor: Shruthi Soora
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Publication number: 20080169888Abstract: A system and method for effectively performing a clock signal distribution procedure includes a clock generator configured to generate one or more clock signals that include electronic timing information. A clock load utilizes the electronic timing information from the clock signals to synchronize appropriate system processes. Capacitive coupling means are provided in a series configuration for transferring the clock signals from the clock generator to the clock load in accordance with an alternating-current direct-drive technique.Type: ApplicationFiled: September 24, 2007Publication date: July 17, 2008Inventors: Jeremy Chatwin, Bernard J. Griffiths