Abstract: A semiconductor structure includes a light emitting region disposed between an n-type region and a p-type region. A wavelength converting material configured to absorb a portion of the first light emitted by the light emitting region and emit second light is disposed in a path of the first light. A filter is disposed in a path of the first and second light. In some embodiments, the filter absorbs or reflects a fraction of first light at an intensity greater than a predetermined intensity. In some embodiments, the filter absorbs or reflects a portion of the second light. In some embodiments, a quantity of filter material is disposed in the path of the first and second light, then the CCT of the first and second light passing through the filter is detected. Filter material may be removed to correct the detected CCT to a predetermined CCT.

Abstract: A semiconductor light emission device including: a nitride semiconductor stack having an active layer capable of emitting light, a growth surface of the nitride semiconductor stack being a substantially nonpolar plane or substantially semipolar plane; and a reflection section formed in a surface of the device opposite to a light extraction surface through which the light emitted from the active layer is extracted, the reflection section reflecting the light to the light extraction surface.

Abstract: Methods for fabricating light emitting diode (LED) chips comprising providing a plurality of LEDs typically on a substrate. Pedestals are deposited on the LEDs with each of the pedestals in electrical contact with one of the LEDs. A coating is formed over the LEDs with the coating burying at least some of the pedestals. The coating is then planarized to expose at least some of the buried pedestals while leaving at least some of said coating on said LEDs. The exposed pedestals can then be contacted such as by wire bonds. The present invention discloses similar methods used for fabricating LED chips having LEDs that are flip-chip bonded on a carrier substrate and for fabricating other semiconductor devices. LED chip wafers and LED chips are also disclosed that are fabricated using the disclosed methods.

Abstract: An LED package is provided. The LED package comprises a metal plate, circuit patterns, and an LED. The metal plate comprises grooves. The insulating layer is formed on the metal plate. The circuit patterns are formed on the insulating layer. The LED is electrically connected with the circuit pattern on the insulating layer.

Abstract: The present invention deals with a process for the manufacturing of reflecting optical barriers comprising silicon and useful in combination with light emitting devices, wherein the process comprises anisotropic wet etching of the silicon material in such a manner that the rate of etching along the crystallographic (111) plane of the silicon material is slower than the rate of etching along the (110) and (100) planes. The present invention further comprises a reflecting optical barrier useful in combination with light emitting devices and a system containing at least one light emitting device comprising a reflecting optical barrier.

Abstract: A light-emitting diode (LED) package includes a thermal-conducting substrate, a LED element, a package body, and an optical modulation device. The LED element is formed on the thermal-conducting substrate. The package body is formed on the LED element and the thermal-conducting substrate, and the optical modulation device is disposed on a light outputting surface of the package body and has a plurality of stepped protrusions for adjusting a shape of an optical field of the light beam. The optical modulation device and the package body can be two separate components and be connected together, or the optical modulation device and the package body can be integrally formed as a single piece when they are made. In addition, a manufacturing method of the LED package is also disclosed.

Abstract: A light-emitting diode (LED) device includes a substrate, at least one LED element and an optical modulation structure. The LED element is disposed on the substrate and generates a light beam. The optical modulation structure is disposed at one side of the LED element for adjusting a shape of an optical field of the light beam and an intensity distribution of the optical field. The optical modulation structure is formed with a plurality of stepped protrusions.

Abstract: There is provided an LED package. An LED package according to an aspect of the invention includes a package body including a concave part formed as a mounting section, first and second lead frames mounted to the package body to be exposed at a lower surface of the concave part, an LED chip mounted to the lower surface of the concave part to be electrically connected to the first and second lead frames, and an encapsulant formed by mixing transparent resin and a phosphor and formed inside the concave part to encapsulate the LED chip. Here, a height from an upper surface of the LED chip and an upper surface of the encapsulant is 1 to 5 times larger than that of the LED chip.

Abstract: A semiconductor light-emitting device includes: a printed-wiring board 3; a light-emitting diode element 2 mounted on the printed-wiring board 3; and a resin body for sealing the light-emitting diode element 2. The resin body is composed of a first resin body 7 arranged around the light-emitting diode element 2, and a second resin body 8 which seals the light-emitting diode 2 and the first resin body 7. An upper edge of the first resin body 7 disposed at a lower position of the junction is configured to be at least on or beyond an imaginary line that connects the junction and a lower edge of the second resin body.

Abstract: Light-emitting diode (LED) packages with improved heat transfer paths for LED dies encased therein when compared to conventional LED packages are provided. For some embodiments, the LED package includes a ceramic substrate having a top cavity with one or more LED dies disposed within and having a bottom cavity for receiving a metallic insert to dissipate heat away from the LED dies. For other embodiments, an LED package is provided that includes a ceramic substrate having a heat spreader coupled to thermal vias filled with a highly thermally conductive composite.

Abstract: An edge-emitting light-emitting diode comprises a base, a frame, and at least three chips. The base has a recessed cup on the front side. The frame is fixed on the recessed cup of the base. These chips are electrically connected to the frame inside the recessed cup. A depth between the upper edges of the chips and a top surface of the recessed cup is ranged from 0.3 mm to 3 mm. As a result, the edge-emitting light-emitting diode provides the function of light mixing and provides superior lighting effect.

Abstract: A light emitting diode (LED) package including a carrier, an LED chip, a first transparent encapsulant, a transparent cap, and a second transparent encapsulant is provided. The carrier has a carrying surface and a ring frame disposed on the carrying surface, and the ring frame forms an encapsulant-containing space on the carrying surface. The LED chip is disposed on the carrying surface and in the encapsulant-containing space. The LED chip is electrically connected to the carrier. The first transparent encapsulant fills the encapsulant-containing space to encapsulate the LED chip. The transparent cap is disposed on the carrier to cover the first transparent encapsulant and the ring frame. The second transparent encapsulant fills an interval between the first transparent encapsulant and the transparent cap.

Abstract: A light-emitting semi-conductor diode comprising a light emitting chip at least partially surrounded by a transparent electronics protecting body on which a composite layer foil is disposed, the composite layer foil includes at its side facing away from the electronics protection body a carrier layer, which has a refraction index that is greater than the refraction index of the electronics protection body and, at the opposite side, an active layer of the same material of which the electronics protecting body consists.

Abstract: A semiconductor component comprising an optically active layer and characterized by at least one cooling element and at least one coupling element. Also disclosed is an arrangement comprising a multiplicity of optically active layers and a method for producing a semiconductor component.

Abstract: A semiconductor light emitting element includes: an {0001} n-type semiconductor substrate formed of a III-V semiconductor, which is in a range of 0° to 45° in inclination angle into a <1-100> direction, and which is in a range of 0° to 10° in inclination angle into a <11-20> direction; an n-type layer formed of a III-V semiconductor on the n-type semiconductor substrate; an n-type guide layer formed of a III-V semiconductor above the n-type layer; an active layer formed of a III-V semiconductor above the n-type guide layer; a p-type first guide layer formed of a III-V semiconductor above the active layer; a p-type contact layer formed of a III-V semiconductor above the p-type first guide layer; and an concavo-convex layer formed of a III-V semiconductor between the p-type first guide layer and the p-type contact layer.

Abstract: A semiconductor device includes an ESD device region disposed within a semiconductor body of a first semiconductor type, an isolation region surrounding the ESD device region, a first doped region of a second conductivity type disposed at a surface of the semiconductor body within the ESD region, and a second doped region of the first conductivity type disposed between the semiconductor body within the ESD region and at least a portion of the first doped region, where the doping concentration of the second doped region is higher than the semiconductor body. A third doped region of the second semiconductor type is disposed on the semiconductor body and a fourth region of the first conductivity type is disposed over the third doped region. A fifth doped region of the second conductivity type is disposed on the semiconductor body. A trigger device and an SCR is formed therefrom.

Abstract: An image sensor includes a photo sensitive device and at lest one transistor such as a drive transistor for converting charge accumulated by the photo sensitive device into an electrical signal. That at least one transistor includes a channel region comprised of a plurality of differently doped regions that generates a conduction band offset in the channel region. Such a conductive band offset increases electron mobility in the channel region for minimizing charge trapping at an interface between a gate dielectric and the semiconductor substrate for minimizing flicker noise.

Abstract: A method for manufacturing a metal-oxide semiconductor (MOS) transistor includes providing a substrate having at least a gate structure and a shallow trench isolation (STI) formed thereon, performing a first etching process to form recesses in the substrate respectively at two sides of the gate structure, performing a selective epitaxial growth (SEG) process to form epitaxial silicon layers in the recesses respectively, accordingly a seam is formed in between the epitaxial silicon layer and the STI, forming a dielectric layer in the seam, and performing a self-aligned silicide (salicide) process.

Abstract: NMOS and PMOS device structures with separately strained channel regions and methods of their fabrication are disclosed. The source and the drain of the NMOS device is epitaxially grown of a material which causes a shift in the strain of the NMOS device channel in the tensile direction. While, the source and the drain of the PMOS device is epitaxially grown of a material which causes a shift in the strain of the PMOS device channel in the compressive direction.

Abstract: By combining a respectively adapted lattice mismatch between a first semiconductor material in a channel region and an embedded second semiconductor material in an source/drain region of a transistor, the strain transfer into the channel region is increased. According to one embodiment of the invention, the lattice mismatch may be adapted by a biaxial strain in the first semiconductor material. According to one embodiment, the lattice mismatch may be adjusted by a biaxial strain in the first semiconductor material. In particular, the strain transfer of strain sources including the embedded second semiconductor material as well as a strained overlayer is increased. According to one illustrative embodiment, regions of different biaxial strain may be provided for different transistor types.

Abstract: In one aspect of the present invention, a semiconductor device may include an isolation region provided in a semiconductor substrate and defining an active region, a gate electrode provided on the semiconductor substrate via a gate dielectric layer in the active region, a channel region provided below the gate electrode, a strain supplying layer provided between the channel region and the isolation region and being epitaxially grown, and configured to generate a strain in the channel region, a silicide layer provided on the strain supplying layer, a reformed layer provided between the silicide layer and the semiconductor substrate near the isolation region, and provided under the strain supplying layer, a source/drain region provided in a part of the strain supplying layer and a part of the reformed layer.

Abstract: A diode assembly comprising first and second diodes each having a different breakdown voltage, each of the first and second diodes comprising a semiconductor substrate; an electrically conducting channel layer on the semiconductor substrate; an upper semiconductor layer on the channel layer, the upper semiconductor layer comprising a recess; first and second ohmic contacts on the upper semiconductor layer on opposite sides of the recess, the ohmic contacts being connected together to form a first diode contact; a gate electrode within the recess, the gate electrode forming a second diode contact; characterised in that the area of the recess of the first diode covered by the first gate electrode is different to the area of the recess of the second diode covered by the second gate electrode.

Abstract: An enhancement mode III-nitride power semiconductor device that includes normally-off channels along the sidewalls of a recess and a process for fabricating the same, the device including a first power electrode, a second power electrode, and a gate disposed between the first power electrode and the second power electrode over at least a sidewall of the recess.

Abstract: Bipolar transistors and methods of forming the bipolar transistors. The method including forming a P-type collector in a silicon substrate; forming an intrinsic base on the collector, the intrinsic base including a first N-type dopant species, germanium and carbon; forming an N-type extrinsic base over a first region and a second region of the intrinsic base, the first region over the collector and the second region over a dielectric adjacent to the collector, the N-type extrinsic base containing or not containing carbon; and forming a P-type emitter on the first region of the intrinsic base.

Abstract: The solid image pickup device of the present invention comprises a photoelectric conversion part, a charge-voltage conversion part for converting electric charges from the photoelectric conversion part to voltage signals, a signal amplifier for amplifying the voltage signals generated in the charge-voltage conversion part, charge transfer means for transferring photo-electric charges from the photoelectric conversion part to the charge-voltage conversion part, and means for applying a certain voltage to a charge-voltage conversion part, wherein at least two readout operations for reading out the photo-electric charges accumulated during a period of accumulating photo-electric charges in the photoelectric conversion part via a signal amplifier.

Abstract: A solid-state imaging device is provided. The imaging device includes an imaging portion which includes light receiving portions and vertical transfer registers, a horizontal transfer portion, an output part for outputting an electrical signal converted from electric charges transferred from the horizontal transfer portion, a first reference potential applying means, and a second reference potential applying means. The imaging portion, the horizontal transfer portion and the output part are formed in a first conductivity type semiconductor substrate having a second conductivity type region, and a reference potential is applied to the second conductivity type semiconductor region. The first reference potential applying means applies a reference potential to the second conductivity type semiconductor region corresponding to an area where the output part is formed.

Abstract: In an embodiment, an apparatus includes a first field effect transistor including a first source contact region, a first drain contact region and a first plurality of fins overlying a substrate, a first gate overlying the first plurality of fins, the first source contact region coupled to first ends of the first plurality of fins, and a second field effect transistor including a second source contact region, a second drain contact region, and a second plurality of fins overlying the substrate, a second gate overlying the second plurality of fins, and an interconnection contact region overlying the substrate, electrically coupling the first drain contact region and the second source contact region and abutting the first and the second pluralities of fins.

Abstract: The present invention relates to high performance n-channel field effect transistors (n-FETs) that each contains a strained semiconductor channel, and methods for forming such n-FETs by using buried pseudomorphic layers that contain pseudomorphically generated compressive strain.

Abstract: A unit cell of a metal-semiconductor field-effect transistor (MESFET) includes a semi-insulating substrate having a surface, an implanted n-type channel region in the substrate, and implanted source and drain regions extending from the surface of the substrate into the implanted channel region. A gate contact is between the source and the drain regions, and an implanted p-type region is beneath the source region. The implanted p-type region has an end that extends towards the drain region, is spaced apart vertically from the implanted channel layer, and is electrically coupled to the source region. Methods of forming transistors including implanted channels and implanted p-type regions beneath the source region are also disclosed.

Abstract: A gap fill nitride is formed in an underlapping region between a first semiconductor area with a first stress liner and a second semiconductor area with a second stress liner without plugging other tightly spaced structures. This is achieved by filling the tightly spaced structures with middle-of-line dielectric material such as silicon oxide in both the first and the second semiconductor areas prior to the formation of the gap fill nitride. The combination of the first and second stress liners and the gap fill nitride provides a continuous mobile ion diffusion barrier across the entire surface of a CMOS semiconductor structure.

Abstract: A pixel sensor cell structure and method of manufacture. Disclosed is a pixel sensor cell comprising an asymmetric transfer gate for providing a pinning layer having an edge spaced a further distance from the gate channel region than an edge of a charge collection well. Potential barrier interference to charge transfer caused by the pinning layer is reduced.

Abstract: A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel region and a periphery region, forming a light sensing element on the pixel region, and forming at least one transistor in the pixel region and at least one transistor in the periphery region. The step of forming the at least one transistor in the pixel region and periphery region includes forming a gate electrode in the pixel region and periphery region, depositing a dielectric layer over the pixel region and periphery region, partially etching the dielectric layer to form sidewall spacers on the gate electrode and leaving a portion of the dielectric layer overlying the pixel region, and forming source/drain (S/D) regions by ion implantation.

Abstract: Color image sensors include pixels having varying color characteristics. One of the pixels is a cyan-type pixel, which includes primary and secondary photodetectors therein. The primary photodetector extends adjacent a portion of a surface of a semiconductor substrate that is configured to receive visible light incident thereon. The secondary photodetector is buried in the semiconductor substrate. The secondary photodetector is configured to receive visible light that has passed through the primary photodetector.

Abstract: A CMOS image sensor includes a photosensitive device, a floating diffusion region, a transfer transistor, and a pocket photodiode formed in a semiconductor substrate of a first conductivity type. The floating diffusion region is of a second conductivity type. The transfer transistor has a channel region disposed between the photosensitive device and the floating diffusion region. The pocket photodiode is of the second conductivity type and is formed under a first portion of a bottom surface of the channel region such that a second portion of the bottom surface of the channel region abuts the semiconductor substrate.

Abstract: Spin-on-glass (SOG) or resist is coated on a passivation film formed on a photodiode region, and then a surface layer of the passivation film together with the SOG or the resist is etched back, to thereby remove irregularities of the surface of the passivation film and to optically planarize the passivation film. As a result, attenuation of light due to reflection, absorption, scattering, and interference is prevented, and a reduction in sensitivity due to variation in thickness of the passivation film is improved.

Abstract: An image sensor includes a photosensitive device and a drive transistor for generating an electrical signal from charge accumulated in the photosensitive device. The drive transistor includes a source region of a first conductivity type and an asymmetry junction region abutting a portion of the source region and being of a second conductivity type that is opposite of the first conductivity type. The drive transistor is biased such that the asymmetry junction region reduces an effective channel length of the drive transistor.

Abstract: A semiconductor device has a conductive film formed over a substrate, an insulating film formed over the conductive film, and having a hole on the conductive film, and a conductive plug formed in the hole including a barrier metal film and a conductive film. A nitride concentration of the barrier metal film is decreased towards an interface between the barrier metal film and the conductive film, and the nitride concentration of the side of the barrier metal film is higher than the nitride concentration of the side of the conductive film at the interface.

Abstract: A semiconductor memory device, comprising: a semiconductor substrate; a memory cell section comprising a memory transistor provided on the semiconductor substrate, the memory transistor including a first gate electrode provided on the semiconductor substrate with a gate insulating film interposed therebetween, and a source and drain provided at both sides of the first gate electrode on the semiconductor substrate, and a ferroelectric capacitor provided above the memory transistor, the ferroelectric capacitor including a first electrode film connected to any one of a source and drain of the memory transistor, a second electrode film connected to the other one of the drain and source of the memory transistor, and a ferroelectric film provided between the first electrode film and the second electrode film, the memory cell section having the memory transistor and the ferroelectric capacitor connected in parallel to each other; and a select transistor section, comprising a select transistor provided at an end of t

Abstract: A semiconductor device comprising a barrier insulating layer and a related method of fabrication is disclosed. The semiconductor device semiconductor substrate includes a plurality of active regions, wherein active regions are defined by a device isolation layer and are disposed along a first direction; a plurality of bit line electrodes connected to the active regions, wherein each of the bit line electrodes extends along a second direction; and a plurality of first barrier insulating layers. Each of the first barrier insulating layers extends along a third direction, at least one of the first barrier insulating layers is disposed on a corresponding first portion of the device isolation layer disposed between two of the active regions, the two of the active regions are adjacent along the first direction, and the first direction and the second direction differ from one another.

Abstract: A semiconductor device having a semiconductor substrate including a first region and a second region is provided. The semiconductor device further includes a gate electrode on the first region and having a first sidewall and a second sidewall, a first source region in the first region proximate to the first sidewall, a first drain region in the first region proximate to the second sidewall, an upper electrode on the second region and having a first sidewall and a second sidewall, a second source region in the second region proximate to the first sidewall of the upper electrode, and a second drain region in the second region proximate to the second sidewall of the upper electrode, wherein an impurity doping concentration of the first source region and the first drain region is greater than an impurity doping concentration of the second source region and the second drain region.

Abstract: A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.

Abstract: This semiconductor device has an MOS transistor equipped with a gate electrode formed on a semiconductor substrate, a source region next to one side of the gate electrode, and a drain region next to another side of the gate electrode, wherein an upper end of the source region and an upper end of the drain region are at positions where are higher than a top surface of the semiconductor substrate, and the height of the upper end of the drain region differs from the height of the upper end of the source region.

Abstract: In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.

Abstract: The semiconductor memory device includes: an interlayer insulating film that is formed on a semiconductor substrate; an insulating film that is formed on the interlayer insulating film and has a cylinder hole; and a capacitor that has an impurity-containing silicon film, a lower metal electrode, a capacitive insulating film and an upper electrode, which are formed so as to cover a bottom and a side of the cylinder hole, wherein the cylinder hole extends through the insulating film so as to expose an end side of the contact plug, the end side facing opposite from the source electrode; and the impurity-containing silicon film has a silicide layer near an interface between the impurity-containing silicon film and the lower metal electrode, the silicide layer being produced by a reaction of impurity-containing silicon included in the impurity-containing silicon film with metal included in the lower metal electrode.

Abstract: A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.

Abstract: A memory cell has a floating gate electrode, a first inter-gate insulating film arranged on the floating gate electrode, and a control gate electrode arranged on the first inter-gate insulating film. An FET has a lower gate electrode, a second inter-gate insulating film having an opening and arranged on the lower gate electrode, a block film having a function to block diffusion of metal atoms and formed on at least the opening, and an upper gate electrode connected electrically to the lower gate electrode via the block film and arranged on the second inter-gate insulating film. The control gate electrode and the upper gate electrode have a Full-silicide structure.

Abstract: A nonvolatile semiconductor memory device includes a first insulator, first conductor, element isolation insulator, second insulator and second conductor. The first insulator is formed on the main surface of a substrate and the first conductor is formed on the first insulator. The element isolation insulator is filled into at least part of both side surfaces of the first insulator in a gate width direction thereof and both side surfaces of the first conductor in a gate width direction thereof and is so formed that the upper surface thereof will be set with height between those of the upper and bottom surfaces of the first conductor. The second insulator includes a three-layered insulating film formed of a silicon oxide film, a silicon oxynitride film and a silicon oxide film formed on the first conductor and element isolation insulator. The second conductor is formed on the second insulator.

Abstract: In one aspect of the present invention, A semiconductor device, may include a transistor including a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a gate stacked above the semiconductor substrate with the insulating film placed in between, and element isolation trenches formed in the semiconductor substrate to define an element formation region in which the transistor is to be formed, wherein the semiconductor substrate includes a narrow portion therein, the narrow portion formed by partially narrowing down the element formation region from the side surfaces of the element isolation trenches in the gate width directions in the substrate.

Abstract: A semiconductor device includes: a silicon substrate; a first trench formed on a surface portion of the silicon substrate to isolate a plurality of active regions from one another; a first element isolation layer embedded in the first trench; a plurality of selectively-grown silicon layers formed on the respective active regions; and a second element isolation layer embedded in a second trench defined by the top surface of the first element isolation layer and opposing side surfaces of adjacent two of the selectively-grown silicon layers.

Abstract: A semiconductor device is made on a semiconductor substrate. A first insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a high voltage transistor in a first region of the semiconductor substrate. After the first insulating layer is formed, a second insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a non-volatile memory transistor in a second region of the substrate. After the second insulating layer is formed, a third insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a logic transistor in a third region of the substrate.