Abstract: The architecture for a combined universal sample rate converter and a sample clock synchronizer is presented. The universal sample rate converter can be applied, for example, to audio samples created or mixed using any of the standard audio frequencies in the set H={8, 11.025, 22.05, 44.1, 48, 96, and 192} kHz and played back using any other frequency from the set H. The synchronizer can be used where audio data are streamed or otherwise broadcast from, for example, the Internet, along with a system timestamp, and where this timestamp needs to be matched to the local audio clock for proper play-back. The same synchronizer can also be used for audio/video or video only synchronization.

Abstract: A method and apparatus for encoding and decoding data for a recording system. The method of encoding data involves encoding input data into a predetermined code and precoding the predetermined code so that output levels of a channel can be detected, the channel being defined by a predetermined channel polynomial.

Abstract: An analog front end circuit comprises a variable gain amplifier circuit (VGA circuit), a first sample switch, a second sample switch, a hold switch and an analog to digital converter device. The VGA circuit comprises a first input end, a second input end, and at least one output end. The first input end is used for receiving first voltage level signals. The second input end is used for receiving first reference signals. The output end is used for outputting at least one amplified signal. While the first sample switch is at a first conductive state, the first input end receives the first voltage level signal. While the second sample switch is at the first conductive state, the second input end receives the first reference signal. Finally, while the hold switch is at a second conductive state, the output end outputs the amplified signal.

Abstract: A microcontroller has an integrating analog-to-digital converter (IADC) with an in-situ autocalibrating functionality. On-chip autocalibrating circuitry supplies a first predetermined analog input voltage to the IADC and obtains a first data value from the IADC. The autocalibrating circuitry supplies a second predetermined analog input voltage to the IADC and obtains a second data value. The first and second data values are used to calibrate the IADC such that if the first input voltage is later supplied to the IADC, then the IADC will output a first predetermined desired digital output value and such that if the second input voltage is later supplied to the IADC, then the IADC will output a second predetermined desired digital output value. The first and second analog input voltages are generated on-chip so the calibration is performed automatically without having to supply external calibrating signals to the microcontroller. Other related methods and circuitry is disclosed.

Abstract: Linearity correction is performed by determining whether a data output value (DOUT) from an analog-to-digital converter (ADC) is in a first subrange or a second subrange. If DOUT is in the first subrange, then DOUT is scaled by a first scaling correction factor (SCF1), and the result is adjusted by a first best fit adjustment value (BFAV1). If DOUT is in the second subrange, then DOUT is scaled by a second scaling correction factor (SCF2), and the result is adjusted by a second best fit adjustment value (BFAV2). The data output range of an ADC can be processed in many ranges of such subranges. Techniques are set forth for determining SCF1, SCF2, BFAV1 and BFAV2. Employing the linearity correction method allows a low-cost microcontroller having an ADC to perform adequate linearity correction on the ADC output data without having to store an INL lookup table.

Abstract: An interleaved ADC can advantageously provide synchronous sampling and time-multiplexed output. Differential I and Q input signals can first be stored by charging a plurality of capacitors. These stored differential signals can be buffered in a time-multiplexed sequence. For example, buffering can include transferring voltages stored by a first set of capacitors at a first time and then transferring voltages stored by a second set of capacitors at a second time. Advantageously, this time-multiplexing allow the ADC to be significantly smaller than conventional implementations of two-input ADCs. A folded mixer with gain control is also provided. This mixer can include a first stage having a first set of inductors and a plurality of first type transistors and a second stage having a second set of inductors and a plurality of second type transistors. The plurality of second type transistors in the second stage, which are in a folded configuration, can be driven by the first set of inductors in the first stage.

Abstract: The invention relates to signal processing circuits, analog-to-digital conversion circuits (A/D conversion circuit) and track and hold and sample and hold circuits. A circuit transfers charge from a first capacitor to a second one 5 where the transfer is enhanced by means of a control signal which influences the value of at least one capacitor. This circuit can be used as an amplifier or a sample and hold circuit, and does not consume any standing current. This circuit can be advantageously combined with a novel capacitor arrangement which allows the generation of multiple residues and reference levels, and the carrying out of multiple operations in parallel. This can improve the overall performance of analog-to-digital converters, including multi-step converters as pipeline and successive approximation converters. The present invention provides amplification and sampling of signals without standing current, and generation of many reference levels and multiple residues in parallel.

Abstract: A method and apparatus taught herein provide a digital-to-analog converter (DAC) for use in a conversion feedback path of a sigma-delta type analog-to-digital converter (ADC). The DAC uses current pulse shaping to generate a conversion feedback signal in each feedback cycle of the ADC that provides a consistent charge transfer for accurate digital conversion and has a controlled current pulse shape. In one or more embodiments, the DAC includes a capacitor circuit for charge storage and transfer and a (series) resistive circuit having variable resistance for current pulse shape control. In at least one embodiment, current pulse control limits a peak current of the conversion feedback signal, thereby reducing DC power consumption and gain-bandwidth (GBW) and slew rate requirements of the ADC's integration amplifier, and limiting residual (ending) current in each feedback cycle, which yields commensurate gains in (feedback cycle) clock jitter insensitivity.

Abstract: A method for converting a digital signal to an analog signal, said method including a plurality of signal sources, preferably current sources, one or more of said signal sources being variable output signal magnitude sources, said method including the steps of setting the output signal magnitudes of the one or more variable output signal magnitude sources by individual setting signals being input signals for said respective variable output signal magnitude sources, wherein said conversion is adaptable on a per signal basis in response to needs concerning bandwidth and/or accuracy for achieving a trade-off between sample-rate and resolution of said conversion.

Abstract: A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that is one of a plurality of register frames forming a data chain. The plurality of register frames are serially linked and data within the data chain is shifted among the plurality of register frames. Through a time domain multiplexing scheme, the D2A can be shared by control knobs of the equalization circuit. The bias circuit includes a decoder also coupled to the primary register frame. An output enable logic module is also included. The output enable logic module determines when the primary register has a complete data set as the data within the data chain is shifting according to the clock period. A method for adjusting a signal through a bias circuit is also provided.

Abstract: A wireless communication device reduces undesired audio underflow in a digital to analog receive path that employs time domain isolation. One or more buffers in the receive path receive processed audio samples from a signal processor. A control circuit senses when the buffers in the receive path are substantially empty. In response to a substantially empty determination by the control circuit, the control circuit instructs one of the buffers to repeat the last processed audio sample which that buffer received to reduce or avoid audio underflow.

Abstract: Digital to analog converter circuits and methods are provided for producing an analog output voltage indicative of a digital input signal with at least partial insensitivity to error gradients. Described are split-core resistive elements, which include a plurality of one-dimensional or multi-dimensional resistive strings, that may be used to reduce or substantially eliminate the effects that error gradients have on the linearity of the analog output voltages of a resistive string or interpolating amplifier DACs. The resistor strings that make up the split-core resistive elements are configured in such a manner that combining respective output voltages from each of the resistor strings results in an analog output voltage that is at least partially insensitive to the effects of error gradients.

Abstract: An asynchronous cyclic current-mode analog-to-digital converter (ADC) is disclosed. The ADC comprises a plurality of sub-ADCs cascading from the first stage to the last stage, each sub-ADC comprising a current-mode ADC having a digital output, an analog current input, a reference current input and an analog current output. The analog current input of each stage, except the first stage, is operatively connected to the analog current output of the immediately preceding stage. The plurality of sub-ADCs are configured to operate without synchronization with each other.

Abstract: An A-D converter includes an A-D converter circuit, a D-A converter circuit, a subtraction circuit, a second amplifier circuit, a reference voltage control circuit, a timing control circuit 18, an amplifier control circuit 19, and an output circuit. The reference voltage control circuit controls the range of reference voltage in the A-D converter according to a step or stage of conversion in the A-D converter. In particular, the reference voltage control circuit performs a control so that the range of reference voltage in the A-D converter circuit at the time of conversion in the third step is larger than that in the first and the second step.

Abstract: Converter systems are provided which complement sample capacitors in at least one converter stage with replica capacitors. The replica capacitors are switched to receive replica charges from the analog input signal during the same operational mode in which the sample capacitors receive undesirable remnant charges. In an initial portion of a subsequent operational mode, the remnant capacitors are briefly switched to the sample capacitors to substantially cancel the remnant charges. The sample capacitors then participate in obtaining input-signal samples during the remainder of the subsequent operational mode. Because the remnant charges have been substantially canceled, the accuracy of the subsequent operational mode is considerably enhanced. In another system embodiment, the replica capacitor is replaced by a discharge switch which provides a discharge path in an initial portion of the subsequent operational mode.

Abstract: Certain embodiments of the present invention provide for an imaging system including an index value source, a transmitter, a receiver, and an image processing component. The index value source is capable of generating an index value. The index value source is part of and/or included in an imaging system detector. The transmitter is in communication with the index value source. The receiver is in communication with the transmitter. The image processing component is in communication with the receiver. The image processing component includes a lookup table. The image processing component is capable of generating a pixel value based at least in part on an index value and a lookup table. The pixel value has a bit-width greater than the index value. In an embodiment, the receiver is in wireless communication with the transmitter.

Abstract: A system is for recognizing obstructions and monitoring movements on or above an airport area (1) with sensors (2, 3, 4). A sensor (2) is a radar device having a plurality of antenna elements (12, 14), which are affixed to a curved surface (15) of an antenna carrier (2a) and are turned on, one after the other, in terms of time. Thus a first part of the antenna elements (14) is disposed on a first circular line (13) on the surface of the antenna carrier (2a), and a second part of the antenna elements (12) is disposed on a circular line (15) perpendicular to the first circular line (13). Therefore the data of the radar device (2) are evaluated in a first ROSAR process, to image the situation on the ground, and in a second ROSAR process, to image the heights of the flying objects to be observed.

Abstract: A system and method of using a standard ADS-B transmitter and encoder to identify targets to provide a collision avoidance system, wherein the method includes the steps of providing a standard ADS-B transmitter and encoder, a phase modulator including a digital synthesizer, radio-frequency electronics, antennas, and a radar transceiver; synthesizing digital-based band signals from the ADS-B transmitter with additional random phase modulation using the digital synthesizer; using the antennas to both transmit and receive signals; and estimating angles-of-arrival for every target in a field-of-view. The method may include the steps of demodulating the signals received by the antennas, providing a digital signal processor, and performing matched filtering on received signals. The method may also include the step of estimating a target range of identified targets using the digital signal processor.

Abstract: A laser warning receiver (LWR) to detect a very low power laser beam for a laser beam rider and provide a high angular resolution in determining the angle-of-arrival of that beam. An aperture having a fixed field-of-view (FOV) is located in a detection channel followed by a narrow-band filter and a detector whose output is applied to a pulse analyzer circuit. A localization channel with the same FOV has a similar narrow-band filter and a lens to focus light from that FOV onto a detector through a N×M element LCD matrix, an output of that detector being applied to the pulse analyzer circuit whose output is applied to a LCD pattern selector connected to the matrix which controls elements in the matrix to provide a transparent window of variable size and position. The size and position of that window allows a laser beam to reach the detector, the window being iterative reduced in size when a beam is detected to provide the location of its source.

Abstract: The radar sensor system includes a radar module, a plurality of antenna units, and a signal carrier. The plurality of antenna units are in communication with the radar module and distributed across a sensing region. The antennas may be connected in a series configuration and, further, may form a loop configuration with the radar module. As such, the radar module may include a centralized signal processor unit configured to receive analog signals from each antenna unit.

Abstract: An adaptive broadcast radar system for tracking targets is disclosed. The radar system includes a transmitter having sub-apertures and a receiver having sub-apertures. The transmitter sub-apertures generate and code a signal waveform. The signal waveform is coded with data about the transmitter, including the degrees of freedom. The receiver receives signals that may include direct path signals and scattered signals correlating to the signal waveforms from the transmitter. The receiver includes a signal processor that regenerates a transmit beam for the coded data, delay, and doppler information from the received signals. The signal processor data quads encapsulates the information.

Abstract: An apparatus and method for low frequency asset tracking includes a low frequency transmitter tag associated with a cargo container or other high value commodity, a plurality of receivers that detect low frequency signals, and a microprocessor that uses algorithms and/or data pertaining to the propagation characteristics of the signal to locate the position of the container or high value commodity. The tag may include sensors to monitor container properties or conditions, such as temperature, motion, intrusion, RF fields, or other properties of interest. Sensor data may be modulated on the low frequency transmitter signal.

Abstract: A method and apparatus for signal detection is provided herein. During operation logic circuitry will determine if a de-sensing signal exists within any received signal and, if a de-sensing signal exists, then it will be assumed that a radar pattern exists where the de-sensing signal exists within the signal. Any received signal pattern is then correlated to known radar transmission pattern in order to determine whether or not a radar transmission pattern was received. If a known transmission pattern was received then logic circuitry will prevent further transmission.

Abstract: A system provides integrated communications, navigation and surveillance capabilities. A plurality of satellites broadcast multiple navigation signals and is capable of two-way communication. At least one monitoring station is capable of receiving the navigation signals broadcast by the satellites and of determining its position based upon the received navigation signals. The monitoring station communicates its computed position to a processing apparatus so that an integrity of the system can be ascertained.

Abstract: A system and method is provided for detecting spurious frequency oscillations within Global Navigation Satellite System (GNSS) signal distribution networks. Power levels of Radio Frequency signals within a GNSS signal distribution network are measured or detected to exceed a threshold and compared to levels known to exceed the GNSS signals level of a properly operating system. A system and method is provided for disabling the conditions enabling spurious frequency oscillations when such conditions are detected.

Abstract: A position calculating apparatus that calculates a position of a moving body by using results of positioning by a GPS satellite and a self-contained sensor includes receiving means for receiving GPS orientation data measured by the GPS satellite and navigation orientation data measured by the self-contained sensor; first determining means for determining a reliability of the GPS orientation data; second determining means for determining a reliability of the navigation orientation data; and movement angle calculating means for calculating a movement angle of the moving body from the GPS orientation data or the navigation orientation data in accordance with the determination results of the first and second determining means.

Abstract: A precision antenna pointing system and methods are disclosed. Antenna pointing error is determined by detecting RF signal phases at locations along the edge of an antenna reflector. A set of signal phase reference harnesses are used to compensate for harness induced errors. Furthermore, multiplexing is used to minimize electronics induced phase errors.

Abstract: A beam-forming antenna system includes an array of integrated antenna circuits. Each integrated antenna circuit includes an oscillator coupled to an antenna. A network couples to the integrated antenna units to provide phasing information to the oscillators. A controller controls the phasing information provided by the network to the oscillators. In an alternative embodiment, the phasing to each antenna element is controlled through a fixed corporate feed network. The relative gains of the antenna signals received or transmitted through the fixed corporate feed may be adjusted with respect to each other to provide a beam steering capability.

Abstract: A method of determining the size of a sub-array for an antenna array is described. The method includes choosing a number of elements of a sub-array of antenna elements. Further, the method includes determining a direction of arrival of the signal using data from the sub-array. The method also includes computing weights for the antenna array. Further still, the method includes determining whether the size of the sub-array meets a predetermined criteria.

Abstract: A communications device for separating source signals provided by M signal sources includes an antenna array comprising N correlated antenna elements for receiving at least N different summations of the M source signals, with N and M being greater than 1. A receiver is connected to the antenna array for receiving the at least N different summations of the M source signals. A blind signal separation processor is connected to the receiver for forming a mixing matrix comprising up to the at least N different summations of the M source signals, and for separating desired source signals from the mixing matrix. The mixing matrix has a rank equal to at least N.

Abstract: A method and corresponding device for joint signal detection and direction of arrival estimation, based on the ability to identify both the existence and direction of arrival of a required signal featuring known characteristics, before it is forwarded to a modem. Optionally, after identifying the existence and direction of arrival of a required signal, the direction of arrival is entered into a beamformer featuring high resolution, for obtaining the signal coming from the required direction of arrival. The calculated signal is then entered into a modem.

Abstract: A method for estimating signal/noise ratio is provided. The method comprises calculating a first signal/noise ratio (SNR) estimate using a technique with a first response time, calculating a second SNR estimate using a technique with a second, slower response time, and blending the first SNR estimate with the second SNR estimate.

Abstract: Embodiments of the present invention provide a method and apparatus for all-polarization direction finding. The method and apparatus generally include acquiring measurements at least partially corresponding to an emitted signal and generated utilizing a blind signal extraction algorithm, forming an all-polarization cost function utilizing the acquired measurements, and determining an angle of arrival for the emitted signal utilizing the formed all-polarization cost function. Such a configuration enables angles of arrivals to be easily determined for signals having any polarization without using a multiple signal classification (MUSIC) algorithm.

Abstract: Provided are a Planar Inverted-F Antenna (PIFA), a Radio Frequency Identification (RFID) tag using the PIFA. The present invention miniaturizes the antenna by using a meander line extended from a radiating edge of a radiation antenna and adjusting a resonant frequency of the antenna, and it performs impedance matching by adjusting capacitive reactance of the antenna. Also, it can perform impedance matching by using a stub having a slot formed therein and adjusting inductive reactance and capacitive reactance of the antenna. The present invention miniaturizes the antenna by using a plurality of shorting plates for shorting the radiation patch from a grounding surface and adjusting the resonant frequency of the antenna. The present invention also provides an inexpensive PIFA antenna with an excellent radiation efficiency by forming the radiation patch in the form of metal sheet in the antenna and floating the radiation patch in the air.

Abstract: A circuit board has a first face and a second face opposite to the first face. An antenna element is mounted on the first face. A shield cover is attached to the second face. The shield cover includes a polygonal base portion, a first wall provided on a first side of the polygonal base portion, a second wall provided on a second side of the polygonal base portion, a third wall provided on a corner defined by the first side and the second side, and disposed between the first wall and the second wall, a first extending portion extended from the first wall so as to overlap with the third wall, and a second extending portion extended from the second wall so as to overlap with the third wall. The shield cover is soldered on the second face.

Abstract: An antenna assembly is use in a telecommunication device having a first printed circuit board and a second printed circuit board disposed right below and facing the first printed circuit board. The antenna assembly includes: radiating metal strip having a main strip section for disposing on an upper surface of the first printed circuit board, a feeding strip section extending from the main strip section through a first through hole in the first printed circuit board toward the second printed circuit board, and a grounding strip section extending from the main strip section through a second through hole in the first printed circuit board toward the second printed circuit board. After assembly, the feeding and grounding strip sections tend toward an upper surface of the second printed circuit board.

Abstract: Portable communication devices are provided. A portable communication device includes a housing, an antenna, and a push button. The housing includes a first receiving portion and a second receiving portion. The antenna is detachably disposed in the first receiving portion. The antenna includes a first engaging portion. The battery is detachably disposed in the second receiving portion. The battery includes a second engaging portion. The push button is disposed in the housing and includes a third engaging portion and a fourth engaging portion. The third engaging portion movably engages with the first engaging portion to fix the antenna to the housing. The fourth engaging portion movably engages with the second engaging portion to fix the battery to the housing.

Abstract: The present invention provides apparatuses and methods for an antenna in a wireless receiving system. The antenna includes an opened segmented component that is electrically coupled to a printed circuit board and a capacitive top loaded component that provides a capacitive load. The vertical profile of the antenna may be reduced sufficiently so that the antenna may be internally located in the same enclosure as the printed circuit board. The capacitive top loaded component is situated away from a ground plane of a printed circuit board to reduce the capacitive coupling is reduced, and consequently the required voltage standing wave ration (VSWR) is maintained over a broad operating range. The capacitive top loaded component includes a closed shape that provides a capacitive load. In order to tune the antenna to operate with a desired characteristic (e.g., within a VSWR criterion), the closed shape may be modified.

Abstract: An automobile antenna capable of preserving a good outward appearance of an antenna shape intact while possessing favorable waterproof and dustproof qualities is provided. An antenna mounted on an outside sheet panel of an automobile and comprising a base member that supports electrical parts for reception and transmission, a cover member that receives the electrical parts for reception and transmission, and a pad member made of an elastic material, and wherein the pad member is fitted internally into the cover member while covering an underside and an outer peripheral portion of the base member.

Abstract: The invention relates to a wireless communication device that is coupled to an energy source, such as a battery, capacitor, or solar cell. The wireless communication device is coupled to a slot in the energy source to form a slot antenna for wireless communication. The slot antenna receives communication signals from an interrogation reader or other communication device. The wireless communication device may be attached to a device or container for purposes such as communicating information regarding identification, manufacturing, tracking, and the like. The wireless communication device may also be coupled to the energy source for power.

Abstract: An antenna device has a sheet-shaped support which is folded along various fold-lines. The support includes a first support plane adjacent to one of the fold-lines and a second support place adjacent to the same fold-line. The first and second support places have first and second antenna structures, respectively, each arranged for receiving or emitting electro-magnetic radiation. The second support plane is positioned at an angle with respect to the first support plane. The second antenna structure is sensitive to electro-magnetic radiation which differs in, e.g., polarization from that of electro-magnetic radiation to which the first antenna structure is sensitive.

Abstract: An antenna system includes a helical antenna that includes one or more helically shaped conductors. Each conductor is substantially embedded in a dielectric structure.

Abstract: An antenna apparatus includes a hollow column, a conductive cable, a first metal wire, a column structure, and a second metal wire. The conductive cable is received in the hollow column, and the conductive cable electrically contacts the hollow column via a second conductive wire layer thereof. One side of the first metal wire is electrically connected with a first conductive wire layer of the conductive cable. The column structure has a column body, a metal layer formed on the column body, at least one spiral groove formed on the metal layer for exposing a part of the column body, and two conductive covers respectively disposed on two sides of the column body. Moreover, one of the two conductive covers is electrically connected with the other side of the first metal wire. Furthermore, one side of the second metal wire is electrically connected with the other conductive cover.

Abstract: A three-dimensional FSS fabrication system is described. FSS elements are pre-mapped in two-dimensional form and constructed on a flat FSS panel that is then formed into a desired three-dimensional shape. The 2-D flat surface of the designed FSS is mapped into a desired three-dimensional curvature so that when formed from 2-D into the 3-D shape, the FSS elements are moved into a desired position and/or orientation. In one embodiment, the mapping from 2-D to 3-D is performed using the elastic properties of a desired substrate material. In one embodiment, one or more flat FSS panels are constructed on a formable or thermo-formable substrate. In one embodiment, the substrate includes a thermoplastic. In one embodiment, the substrate includes a thermoplastic material with fiber reinforcement. The FSS elements can be created by printing, deposition, photo-etching, etc. The flat FSS layers are thermoformed or chemically formed over a tool having the desired shape.

Abstract: The present invention is directed to a multi display device that can realize a large-sized screen by interconnecting a plurality of display elements. The multi display device comprises at least two flat display elements of which adjacent sides are closely contact each other to make a large-sized screen, housings receiving and supporting the display elements, respectively, light-compensating means for refracting display light from the display elements toward a center area of the adjacent sides thereof, thereby to minimize or remove the non-display area in the screen.

Abstract: A display system, which is useful for simulation, and training system that provides a mosaic wide field of view display by alternating virtual and direct view display images through the use of a new optical beamsplitter/combiner device. Edge blending and the use of flat panel display devices are used to provide a high brightness, high contrast, high reliability, and continuous unobstructed field of view. The new optical beamsplitter/combiner has an optically flat reflective portion and a curved transmissive portion.

Abstract: An orientation sensor measures the orientation of the orientation sensor itself on a sensor coordinate system, and outputs an orientation measurement value. A first alignment data setting unit reads out first alignment data, which is recorded in an external storage device and represents the gravitational direction on a reference coordinate system, and sets that data in an orientation calculation unit. A second alignment data setting unit sets second alignment data, which represents a difference angle in the azimuth direction between the sensor coordinate system and reference coordinate system in the orientation calculation unit in accordance with a command input by an operator from a command input unit. The orientation calculation unit calculates the orientation of an object on the reference coordinate system using the first and second alignment data on the basis of the orientation measurement value input from the orientation sensor, and outputs it.

Abstract: A PDP driving circuit for a stable operation of a ramp pulse. A capacitor having a temperature characteristic opposite to a temperature characteristic of a part coupled to a switch that operates as a constant current source for generation of a ramp pulse is arranged in the driving circuit for generating a ramp pulse. The ramp pulse linearly increases or decreases a panel voltage of the PDP with respect to time. Parts having opposite temperature characteristics are coupled in parallel to control variation of a gradient of the ramp pulse so that values of the parts may not be varied depending on the temperature changes. Thus, stable operation of the ramp pulse is obtained.

Abstract: Disclosed herein are an apparatus for driving a plasma display panel in which the capability to represent the gray scale can be improved, and method thereof. The apparatus includes an inverse gamma control block for performing an inverse gamma correction process on input data received from the outside by using two or more gamma values, and a select unit for outputting one of two or more output data on which the inverse gamma correction operation is performed, which is outputted from the inverse gamma control block. Therefore, the capability to represent the gray scale can be improved. Furthermore, an error diffusion pattern and pseudo noise can be reduced and the picture quality can be thus improved.

Abstract: A pixel circuit in an organic light emitting device capable of realizing high gradation representation by self-compensating a threshold voltage, and a method for driving the same. The pixel circuit includes an electroluminescent element for emitting light in response to an applied driving current. A first transistor delivers a data signal voltage in response to a current scan line signal. A second transistor generates a driving current to drive the electroluminescent element in response to the data signal voltage. A third transistor connects the second transistor in the form of a diode in response to a current scan signal to self-compensate the threshold voltage of the second transistor. A capacitor stores the data signal voltage delivered to the second transistor. A fourth transistor delivers a power supply voltage to the second transistor in response to a current light-emitting signal.