Abstract: A magnetic detection device of which an output can be completely switched over with an external magnetic field is formed in a small size. A detection circuit is formed by forming circuit elements such as an active element layer and interconnection layers on a substrate. An insulating layer is formed on the detection circuit, and a flat surface is formed on the resultant surface. A magnetic detection element that detects an external magnetic field by using a magneto-resistance effect and a fixed resistance element, which has the same electric resistance as the magnetic detection element but does not react to the external magnetic field, are formed on the flat surface. Electrode layers and a lead layer are formed on the flat surface, and the lead layer and the interconnection layer are electrically connected to each other via a bump penetrating the insulating layer.

Abstract: The invention relates to a fluxgate micromagnetometer implemented in thin layers, fitted with at least one excitation coil with an arrangement and a structure that bring improvements particularly in terms of the magnetometer footprint, reduction in the “offsets” of measurements taken by the magnetometer, common mode rejection.

Abstract: An apparatus for detecting a potentially dangerous ferromagnetic object carried inadvertently by a person approaching the magnet of a magnetic resonance imaging system (14) uses the fringe field (16) of the magnet and provides guide members (11) defining a path along which the person is prescribed to pass. The path (11) is generally or approximately parallel to the field the path. At least one sense coil and generally two sets of sense coils (12, 13) are located on respective sides of the path (11) s the movement of the ferromagnetic object in the field of the magnet causes a voltage to be generated in the sense coil.

Abstract: A system for providing shielded dynamic shimming in a magnet assembly of a magnetic resonance imaging (MRI) scanner includes a main shim coil set located at a first radius in a gradient coil assembly of the magnet assembly. The system also includes a dynamic shim insert located at a second radius in the magnet assembly. The second radius is less than the first radius and is less than a radius of an RF coil in the magnet assembly. The main shim coil set may be operated as a shielding shim coil set for the dynamic shim insert.

Abstract: An RF coil apparatus suitable for a high magnetic field MRI apparatus includes a plurality of subcoils arranged substantially in a cylindrical form. Each subcoil includes a first conductor part and a second conductor part. The second conductor part is disposed on the inside of a cylinder, i.e., on the test subject side. This coil apparatus includes a conduction part for attaining conduction among the subcoils, and a conduction control part for controlling a conduction state between the first conductor part and the second conductor part, conducting connection to a transmission and reception part which conducts signal transmission and reception with a subcoil, and changing over electric capacitance of the subcoil according to whether to receive or transmit. Function changeover between the multi-channel mode and the one-channel mode is accomplished by conducting connection changeover and electric capacitance changeover.

Abstract: A system is provided for facilitating the imaging of a specimen, such as a laboratory rat, within an imaging machine such as an MRI machine. A sliding, self-centering interconnection is provided between a magnetic positioning and spacing assembly and a specimen positioning and retention assembly. Support and abutment surfaces are provided for facilitating the proper mounting locations of a gradient coil and probe coil within the main magnet coil and for optimally locating a specimen with respect to the main magnet coil and with respect to the gradient and probe coils.

Abstract: A metal detection apparatus includes a transmitter for generating a magnetic field in the vicinity of the metal object, and a detector for detecting a secondary magnetic field. The detector include a first gradiometer for providing a first output signal representative of a first direction, y, to the metal object, a second gradiometer arranged substantially orthogonal to the first gradiometer for providing a second output signal representative of a second direction, x, to the metal object, the second direction being substantially orthogonal to the first direction and in the same plane as the first direction, and an outer coil and an inner coil arranged to be substantially concentric with one another and each of which is arranged to provide an output signal representative of secondary magnetic field strength in a third direction, z, which is substantially orthogonal to the plane of the first and second directions.

Abstract: An apparatus for obtaining tool face angles on a rotating drill collar in substantially real time is disclosed. In one exemplary embodiment the apparatus includes a magnetoresistive magnetic field sensor deployed in a tool body. The apparatus further includes a programmed processor configured to calculate tool face angles in substantially real time from the magnetic field measurements. The programmed processor may optionally further be configured to correlate the calculated tool face angles with logging while drilling measurements for use in borehole imaging applications.

Abstract: A method and a system are provided for allowing determination of a direction and distance from a tool to anomaly in a formation. The apparatus for performing the method includes at least one transmitter and at least one receiver. An embodiment of the method includes transmitting electromagnetic signals from the at least one transmitter through the formation near the wellbore and detecting responses at the at least one receiver induced by the electromagnetic signals. The method may further include determining the direction from the device to the anomaly based on the detected responses. The method may also include calculating at least one of an apparent azimuth angle and an apparent dip angle based on the responses, monitoring the at least one calculated apparent angle over time, and determining the direction to the anomaly after the at least one monitored apparent angle deviates from a zero value.

Abstract: A resistivity tool has a body with at lest one pair of grooves on its exterior oriented orthogonal to the tool axis. A coil antenna is oriented orthogonal to the grooves in a hole intersecting the grooves and oriented orthogonal to the tool axis. The antenna and an antenna core define a plurality of small antenna loops.

Abstract: A thin deck water property sensor includes a base, an upper lid, a positive and negative probe, an electric connection element, a processing unit and a display unit. The base and the upper lid are coupled together to form a flat deck. The upper lid has a recess to hold sample water to be tested. The positive and negative probe is extended into the recess in contact with the sample water. The electric connection element has one end connecting to the processing unit and another end coupling with a conductive elastic member. The conductive elastic member is connected to the positive and negative probe. The processing unit receives charged signals of the sample water to generate a test result which is displayed on the display unit.

Abstract: A non-contact apparatus and method for measuring of the leakage current and capacitance of p-n junctions in test structures within scribe lanes of IC product wafers is disclosed. The apparatus has a light source optically coupled with a fiber to a transparent electrode at the end of the fiber, which is brought close to the p-n junction under test. The ac signal generated from the test p-n junction is captured by this transparent and conducting coating electrode. The leakage current of a test p-n junction is determined using the frequency dependence of junction photo-voltage signal and reference signals from a p-n junction with low leakage current and known capacitance.

Abstract: A system and method are used to determine connectivity and/or cable faults of a cable. A signal transmitting and receiving system is coupled to the cable. An analog-to-digital converter (ADC) coupled to the signal transmitting and receiving system. A TDR system coupled to the ADC and a memory, and a controlling system coupled to at least one of the ADC, the TDR system, and the signal receiving and transmitting system. The controlling system includes a controller and one or more state machines that are used to control the TDR system.

Abstract: A method and apparatus adapted to calibrate signal path of a signal analysis system such that loading effects of additional probes are substantially removed from the measurement. A signal under test from a device under test is coupled to a test probe and used with selectable impedance loads in the test probe to acquires sets of samples for characterizing transfer parameters of the device under test and compute open circuit voltages at the test probe. Other probes are coupled to the device under test and a set of measurement samples are acquired via the test probe. An equalization filter in either the frequency or time domain is computed from the open circuit voltage and measurement samples for reducing signal errors attributable to the measurement loading of the device under test by the test probe and other probes.

Abstract: An operator presence control assembly for a walk-behind greens mower includes a handle supported on a frame of the walk-behind greens mower, a ribbon switch on the outer perimeter of the handle, and a circuit including the ribbon switch. The circuit is completed by applying a threshold pressure to the ribbon switch, and a device selectively energizeable via the circuit in accordance with the threshold pressure applied to the ribbon switch. As the user of the greens mower grips the handle, the ribbon switch completes a circuit to energize a switch to engage an electromagnetic clutch.

Abstract: A blade tip clearance probe holder including: a first housing in operable communication with a first feature of a casing for a rotary machine; a spring rod assembly in operable communication with the first housing; an electrical capacitance clearance meter in operable communication with the spring rod assembly; and a second housing in operable communication with the first housing wherein the second housing initiates a preload on the spring rod assembly and wherein the electrical capacitance clearance meter maintains a constant spatial relationship with a second feature of the casing for the rotary machine.

Abstract: A guarded sense impedance for use in a measurement instrument includes a sense impedance adapted to have a spatially distributed electrical potential and at least one guard structure adapted to have the spatially distributed electrical potential. The guard structure is arranged to provide a spatially distributed guard potential for the sense impedance.

Abstract: A sensor (1) for capacitively measuring the distance to a stationary or passing object. The sensor has an electrode (2) that capacitively couples with the object and is formed from an electrically conductive ceramic material. The electrode is substantially surrounded by a housing (4) formed from an electrically non-conductive ceramic. The electrically conductive and electrically non-conductive ceramic materials are chosen to that they have the similar thermal expansion coefficients so that the sensor remains virtually stress free at high temperatures.

Abstract: An electrical condition monitoring method utilizes measurement of electrical resistivity of an age sensor made of a conductive matrix or composite disposed in a polymeric structure such as an electrical cable. The conductive matrix comprises a base polymer and conductive filler. The method includes communicating the resistivity to a measuring instrument and correlating resistivity of the conductive matrix of the polymeric structure with resistivity of an accelerated-aged conductive composite.

Abstract: According to one aspect of the invention, a contact sheet for testing electronic parts, comprising an insulating porous layer; and a connection electrode which is disposed on the insulating porous layer and electrically connect the electrode or terminal of the electronic parts and the terminal of a test apparatus; wherein the connection electrode is embedded below at least one main surface of the insulating porous layer.

Abstract: A test system includes a communications channel that terminals in a probe, which contacts an input terminal of an electronic device to be tested. A resistor is connected between the communications channel near the probe and ground. The resistor reduces the input resistance of the terminal and thereby reduces the rise and fall times of the input terminal. The channel may be terminated in a branch having multiple paths in which each path is terminated with a probe for contacting a terminal on electronic devices to be tested. Isolation resistors are included in the branches to prevent a fault at one input terminal from propagating to the other input terminals. A shunt resistor is provided in each branch, which reduces the input resistance of the terminal and thereby reduces the rise and fall times of the input terminal. The shunt resistor may also be sized to reduce, minimize, or eliminate signal reflections back up the channel.

Abstract: A MEMPCS having high stiffness against bending deformation or distortion is formed by integrating the probe, electronic circuit, circuit connecting pad and dielectric material into a complete unit with flexible multiple-layered substrate structure, and the part of the probe extended outside the dielectric material is further wrapped with a protecting layer to form an reinforced structure for increasing high stiffness to the probe and for preventing environmental dirt and particle from getting into the gap existed between the probes of the MEMPCS.

Abstract: An insertable calibration device for a programmable tester apparatus comprises at least one calibration unit and a control unit. The progammable tester apparatus is configured to test at least one electronic device with electronic circuits. The progammable tester apparatus comprises a holding device, contact-making devices for the electronic device, and tester channels for coupling in signals to the electronic device. The calibration unit is connected to a first tester channel to be calibrated. The calibration unit is configured to detect a calibration signal edge of a calibration signal that is transmitted by the tester apparatus at a certain transmission instant, to detect a reference signal edge of a reference signal that is transmitted by the tester apparatus via a second tester channel at a reference instant, to compare the instants at which the two signal edges arrive, and to output a comparison result.

Abstract: A system in-package test inspection apparatus for measuring and evaluating the high-speed/high frequency characteristic of a system in-package through an electrode pad in which I/O terminals are formed on one side of an LSI package containing metallic wiring internally and plural LSI chips are stacked in multiple layers on the other face while electric connection between the LSI chip and the LSI package and the electric connection between the LSI chips are implemented, the system in-package test inspection apparatus comprising: a printed wiring substrate to which the I/O terminals of the system in-package are connected to enable transmission of high speed and high frequency signals; LSI chip driving means for driving the LSI chip; a contact probe having a contact electrode and for transmitting a high frequency signal; evaluation signal generating means for supplying a high frequency evaluation signal to the contact probe; output signal detecting means for detecting an output signal of the system in-package th

Abstract: A wafer-level test module is disclosed to include a base layer having multiple first apertures spaced from one another at a pitch corresponding to the pitch of the image sensor chips of an integrated circuit wafer, a cover layer having second apertures respectively axially aimed at the first apertures, and an optical layer sandwiched between the base layer and the cover layer having multiple optical lenses of which the optical axes pass through the first apertures and the second apertures, so that when one image capturing device of the image sensor chips of an integrated circuit wafer is adjusted to the image plane of one of the optical lenses and the wafer-level test module is set in alignment with the integrated circuit wafer horizontally and vertically, then the effective test light can be simultaneously projected onto the image capturing devices of the respective image sensor chips through the wafer-level test module to achieve an effective wafer-level test on multiple image sensor chips of the integrated

Abstract: Power measurement and control in transmission systems are affected by changes in load conditions. A method and system are provided for detecting and controlling power levels independent of such load conditions.

Abstract: While a PWM-controlled, FET-switched three-phase motor is operating in a mechanical damping mode, a single current sensor is used to measure current in the motor. When mechanical feedback into the motor exceeds a predetermined threshold, a bank of the FET switches can be closed to provide damping of the mechanical feedback. This causes currents to circulate within the motor, which an external single current sensor cannot measure to determine current load or when the mechanical feedback is no longer a problem. The present invention periodically switches selected switches necessary to sample the current in at least one phase of the motor to determine when the mechanical feedback into the motor is no longer a problem, while preferably also maintaining an average zero voltage vector.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for time-multiplexed dynamic on-die termination. In an embodiment, an integrated circuit receives, during a first clock, an on-die termination (ODT) activation signal at its ODT pin. The integrated circuit also receives, during a second clock, an ODT value selection signal on its ODT pin. In an embodiment, the integrated circuit prevents a reset of the state of the ODT activation signal for a predetermined period of time to enable the multiplexing of signals on the ODT pin. Other embodiments are described and claimed.

Abstract: An integrated multi-function analog circuit includes at least one MOSFET gate-drive circuit coupled to a first I/O pad. At least one voltage-sensing circuit is coupled to a second I/O pad. At least one current-sensing circuit is coupled to the second I/O pad and a third I/O pad. At least one temperature-sensing circuit is coupled to a fourth I/O pad.

Abstract: A non-volatile memory configuration scheme is disclosed for volatile-memory-based programmable circuits in a programmable integrated circuit that includes an FPGA fabric, a plurality of first configurable circuit elements external to the FPGA fabric, and a plurality of second configurable circuit elements external to the FPGA fabric. A plurality of distributed configuration non-volatile memory cells is disposed in the FPGA, each one of the distributed configuration non-volatile memory cells coupled to a different one of the plurality of first configurable circuit elements. A non-volatile memory array stores configuration information for the second configurable circuit elements. A plurality of register cells is disposed with the second configurable circuit elements and is coupleable to the non-volatile memory array, each one of the register cells coupled to a different one of the plurality of second configurable circuit elements.

Abstract: The architecture of a programmable logic device (“PLD”) is modified in one or more of several respects to facilitate inclusion of high-speed serial interface (“HSSI”) circuitry in the PLD. For example, the HSSI circuitry is preferably located along one side of the device, taking the place of regular peripheral IO circuitry in that area. Certain portions of the core logic circuitry are modified to better interface with the HSSI circuitry.

Abstract: A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.

Abstract: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function.

Abstract: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic function, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function.

Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable switch in each routing track. The position of the programmable switch(es) in each connection box connected to same interconnect matrix differs from the position of said programmable switch(es) in corresponding routing tracks of other connection boxes thereby utilizing the connectivity of said switch box for input connections and increasing the flexibility of connections.

Abstract: An input circuit is provided that can identify three states of an external signal without complicated voltage adjustment and that can reduce the power consumption in a standby state.

Abstract: A circuit arrangement for converting logic signal levels has a level converter and a mixing arrangement for influencing a pulse width. The level converter includes a first signal path and a second signal path each having a series circuit comprising two transistors of different conductivity types and two outputs which are each connected to a tap between the transistors which are coupled in series. In this case, the transistors of one conductivity type can be controlled by means of a push-pull signal and the transistors of the other conductivity type in a respective one of the two signal paths can be controlled by means of a signal at the output of the respective other signal path. The mixing arrangement includes two inputs and two outputs, the first input being coupled to the first output and the second input being coupled to the second output.

Abstract: A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.

Abstract: An electromechanical switching device employs a first nanoscale pillar shuttling charge between opposed charged electrodes. Motion of the first pillar is coupled to a second set of pillars providing controlled charge transfer between a second isolated set of electrodes. Standard logic elements may be constructed using this switching device.

Abstract: The clock based voltage deviation detector of the present invention includes a pulse module, an indicator module and a correlation module. The pulse module generates a stream of reset pulses as a function of a clock signal. The indicator module generates a pass/fail indicator signal as a function of the reset pulse stream and a difference between an input signal and a reference voltage. The correlation module correlates an event (e.g., overvoltage or undervoltage) of the pass/fail indicator signal with a period of the clock signal at which the event occurred.

Abstract: A receiver for receiving a switched signal on a communication line (1), such as a LIN bus, the signal varying between first and second voltage levels (sup, ground). The receiver comprises a comparator (31, 54) responsive to the relative values of the received signal voltage level (Vlin) and an input reference voltage level (Vsup). The comparator (31, 54) comprises a current generator (40, 41) selectively operatble when the recieved signal is asserted to produce an input current (Iin) which is a function of the received signal voltage level (Vlin) and a reference current (Isup) which is a function of the input reference voltage level (Vsup), and output means (28, 32, 31; 55, 56) responsive to the relative values of the input current (Iin) and the reference current (Isup). The output means (28, 32, 31; 56) is supplied with power at a voltage (VDD) substantially lower than the difference between the first and second voltage levels (Vsup, ground).

Abstract: A low voltage detection circuit includes a reference voltage generation circuit, a divider circuit, a comparator that serves as a comparison circuit, and a second constant current transistor connected in series with the divider circuit. An auxiliary current transistor as well as a first constant current transistor is connected in series with a load element. The auxiliary current transistor is controlled by a voltage at a drain of the second constant current transistor. A gate of the second constant current transistor and a gate of the first constant current transistor are connected with each other to form a current mirror. A size of the second constant current transistor is adjusted so that the second constant current transistor can provide a second constant current that is several times larger than a first constant current provided by the first constant current transistor.

Abstract: An output buffer circuit includes an input stage of which one end receives an input voltage and the other end receives an output voltage; a class AB output stage that increases a current flowing in the output stage when the difference between the input and output voltages is larger than 0; a floating current source that biases the class AB output stage; a summing circuit that is connected to the input stage, the floating current source, and the class AB output stage so as to sum up the current supplied from the input stage and the internal current supplied from the floating current source; and an offset compensating circuit that is connected to the input stage and is composed of a plurality of switching elements and resistors so as to detect an offset voltage to compensate.

Abstract: In a two-stage inverter circuit including an inverter circuit constituted by first and second FETs and an inverter circuit constituted by two FETs, a source and a gate of a third FET are connected to a first power source and a second power source, respectively. A drain of the third FET is connected to a source of the first FET. A source and a gate of a fourth FET are connected to the first power source and the second power source, respectively. A drain of the fourth FET is connected to a source of a seventh FET. A gate of the seventh FET is connected to the second power source, and a drain of the seventh FET is connected to a back gates of the first, third, fourth, seventh and fifth FETs. The drain of the third FET is connected to the drain of the fourth FET.

Abstract: A device is provided for multiplying the pulse frequency of a pulse train signal. The device includes input means for the signal and means for accessing the signal at points with a predetermined phase difference between them. The device additionally comprises means at a first level for combining accessed signal pairs, with one and the same phase distance within all the combined pairs, the output from each first level combining means being a pulse train. The device additionally comprises combining means at a second level for combining the pulse trains from the first level, and the combining means at the first level are such that the pulses in their output pulse trains have rise flanks which always coincide with the rise flank of the first signal in the combined accessed signal pairs, and fall flanks which always coincide with the fall flanks of the second signal in said pair.

Abstract: Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

Abstract: A device for synchronizing an input clock signal with an output clock signal is disclosed. One embodiment includes includes a bistable trigger circuit for controlling the edges of a clock signal fed to a first delay, a second phase comparator for determining the phase between the first clock signal delayed by the first delay and the input clock signal, and a second controller for controlling the delay of the first clock signal in correspondence with the phase determined by the second phase comparator.

Abstract: A DLL circuit of a semiconductor memory apparatus includes a frequency sensing unit that generates and outputs a high frequency signal and a low frequency signal on the basis of a CAS latency signal. A clock dividing unit divides the frequency of an internal clock by a predetermined value and generates a divided clock in response with whether the high frequency signal is enabled or the low frequency signal is enabled. A phase sensing unit that switches a reference clock and a comparison clock, compares the phases thereof in accordance with whether the high frequency signal is enabled or the low frequency signal is enabled, selectively switches first and second phase control signals generated on the basis of the comparison result, and outputs the switched signals.

Abstract: A delay-locked-loop control circuit and a method of controlling a delay-locked-loop. When the delay-locked-loop is in an off-operation mode, such as a power-down mode, a self-refresh emulation mode, a self-refresh mode, and the like, the delay-locked-loop is updated with a predetermined period, thereby preventing a malfunction of the delay-locked-loop. The delay-locked-loop has an oscillating portion which generates an oscillation signal having a predetermined period when in an OFF state; a pulse generating portion which generates a pulse signal having a predetermined period using the oscillation signal; a dividing portion which divides the pulse signal to generate a delay-locked-loop update signal; and a combining portion which combines the delay-locked-loop update signal and a delay-locked-loop on signal that is enabled by an external command to generate a delay-locked-loop control signal for controlling the delay-locked-loop.

Abstract: A duty cycle correction circuit comprises a tuned circuit, a delay circuit and a phase-locked loop; wherein the tuned circuit receives an input clock, generates a periodic pulse according to the input clock, tunes the periodic pulse depending on a reference voltage, and outputs an output clock; a delay circuit receives the output clock, and generates a complementary signal; a phase lock loop receives the complementary signal, measures the periods of time of the high level state and the low level state of the complementary signal, generates the reference voltage and feeds back to the tuned circuit. By using the technique of the present invention, it is able to track the delay time between the input clock and the output clock, and the drift of the output clock is reduced.