Abstract: A KVM operation console includes a lower body and an upper body. The lower body and the upper body are assembled into and can be separately slid from an industrial console. A lock mechanism is installed in a bottom cover of the upper body. An L-shaped arm and is pivotally connected with the bottom cover. A lock shaft and a handle are respectively pivotally connected with two ends of the L-shaped arm. The handle is moved to retract the lock shaft from or extend the lock shaft into an opening of the bottom cover by a torque of the L-shaped arm. The extended lock shaft is inserted into a hole of the industrial console so as to secure the upper body. The upper body blocks a holder of the lower body to prevent the lower body from sliding out of the industrial console.

Abstract: A battery-backed cache system with a pluggable battery module. The system includes a RAID controller and a cache. A back up power board is provided upon which a second power connector is provided and the two power connectors are connected. A socket assembly is mounted on the board and is connected to the second power connector. The socket assembly is a standard socket for use with PC Cards and includes a bulkhead adapter for mounting to a case wall with a slot of the socket assembly accessible through the case wall. A battery module is included having a body with dimensions corresponding to the slot. A battery is positioned within the body and a connection interface is provided in the battery module for mating with the socket assembly. The body and connection interface of the battery module comply with PCMCIA specifications for card bodies and interfaces.

Abstract: A portable communication device has a modular inner chassis containing a main printed circuit board and an outer housing for releasable engagement over the inner chassis so as to substantially completely enclose and conceal the inner chassis. The outer housing has at least two parts. A first part of the outer housing contains a keypad and a separate keypad printed circuit board for connection with a keypad connector on the main printed circuit board when the housing is engaged over the inner chassis. The outer housing and inner chassis have releasable interengaging formations for releasably securing the first and second parts of the outer housing over the inner chassis.

Abstract: An electronics module assembly for detachably retaining a pair of electronic sub-modules in a single slot of a chassis. A host module of the electronics module assembly is configured to be detachably received and retained in a slot of the chassis. The host module has a height corresponding with a height of the slot of the chassis. A pair of sub-modules are configured to be detachably received and retained in the host module. The combined height of the sub-modules is no greater than the height dimension of the slot of the chassis. Therefore, where there was once only room for one electronics module in a single slot of the chassis, a pair of sub-modules with the host module may now be utilized in the single slot of the chassis.

Abstract: Low inductance capacitors include electrodes that are arranged among dielectric layers and oriented such that the electrodes are substantially perpendicular to a mounting surface. Vertical electrodes are exposed along a device periphery to determine where termination lands are formed, defining a narrow and controlled spacing between the lands that is intended to reduce the current loop area, thus reducing the component inductance. Further reduction in current loop area and thus component equivalent series inductance (ESL) may be provided by interdigitated terminations. Terminations may be formed by various electroless plating techniques, and may be directly soldered to circuit board pads. Terminations may also be located on “ends” of the capacitors to enable electrical testing or to control solder fillet size and shape. Two-terminal devices may be formed as well as devices with multiple terminations on a given bottom (mounting) surface of the device.

Abstract: A semiconductor device (100) comprising a semiconductor substrate (20) and a functional element (31), such as a microstrip, an inductor, a coupler or the like, is provided. Herein the functional element (31) is—at least partially—present in a conductive patterned layer that is mechanically embedded in isolating material (40) and that is connected to the substrate (20) through connection means. In this way, electrical losses through the substrate (20) are substantially reduced. The device (100) is provided in that a foil comprising the patterned layer and a carrier layer is applied to the substrate (20), after which the space between them is filled with the isolating material (40) and the carrier layer is removed.

Abstract: A mounting apparatus for an expansion card (30) includes a computer panel (12), a bracket (14) mounted to the computer panel, and a card holder (20) mounted to the bracket. At least a post (1416) is formed on the bracket. The card holder includes a body (22) glidingly mounted to the bracket for installing the expansion card and a handle (24) resisted by the post of the bracket for preventing the body from sliding out so as to fix the card holder in position.

Abstract: A power supply early warning device for pulling out a power plug is composed of a power supply, which is loosely connected with a handle, with the handle being installed with a locking hole. A long through-hole is installed at a side edge of the power socket, and a locking member is provided with a pushing plate, with an end of which being formed with a projection piece. the locking member is installed with a locking plate which can be locked or loosely connected into the long through-hole, and the pushing plate can be slidingly displaced on an outer wall of a rim of the long through-hole, allowing the projected piece to be locked into or released from the locking hole of the handle, so as to prevent from a deformation or a short-circuiting between the power plug and the socket by a dragging of external force, and to further enable a user to displace the power supply more safely, without damaging the entire power supply system.

Abstract: A circuit board fastening structure includes a seat, a fastening plate movably mounted onto the seat, and a circuit board. Anchoring members are provided to confine the circuit board. The seat has a detent wall to anchor a detent member located on the fastening plate so that the fastening plate and the circuit board may be coupled and anchored securely.

Abstract: Techniques are disclosed to regulate an output current through a load coupled to a power converter using a current source coupled to the load. For instance, one power converter according to the teachings of the present invention includes an energy transfer element coupled between an input of the power converter and an output of the power converter. The power converter also includes a controller circuit coupled to the energy transfer element and the input of the power converter to regulate the output of the power converter. A current source circuit is also included and is coupled to the output of the power converter to limit an output current of the power converter to below a threshold value.

Abstract: A switching power supply apparatus includes a first inductor that is serially connected to a primary winding of a transformer, and a second inductor that is arranged so as to apply a voltage of a capacitor with sine waves obtained by rectifying an AC input voltage for an on-period of a first switching circuit. A diode for preventing the inverse current to the second inductor and a capacitor that is charged by excitation energy charged to the second inductor and applies a voltage to the primary winding for on-period of the first switching circuit. Further, a capacitor is arranged so that the inductor, the primary winding, and a second switching circuit define a closed loop. Switching control circuits control the on-period of a first switching element to control an output voltage Vo, and further control an input voltage Vi by controlling the on-period of a second switching element.

Abstract: A controller controls the output current by measuring and controlling the switching current of the power converter. A first circuit generates a first signal in accordance with the switching current. A second circuit detects a discharge-time of the transformer. A third circuit generates a third signal by integrating the first signal with the discharge-time. The time constant of the third circuit is programmed and correlated with the switching period of the switching signal, therefore the third signal is proportional to the output current. A switching circuit generates a switching signal and controls the pulse width of the switching signal in accordance with the third signal and a reference voltage. Therefore, the output current of the power converter can be regulated.

Abstract: A method for smoothing input current to a power delivery system having regeneration capability. The method comprises evaluating input current to an input converter of the power delivery system for a first fundamental cycle, and shifting a window relative to a waveform of an input voltage after the first fundamental cycle. The method also comprises evaluating input current to the input converter for a second fundamental cycle, and determining whether the input current of the second fundamental cycle is smoother than the input current of the first fundamental cycle.

Abstract: An insulated gate bipolar transistor and a protective circuit are incorporated. The protective circuit has first and second Zener diodes connected in series in directions opposite to each other between the gate and the current sense terminal of the insulated gate bipolar transistor, and third and fourth Zener diodes connected in series in directions opposite to each other between the gate and the emitter of the insulated gate bipolar transistor.

Abstract: A switched current power converter including an input power source, an output terminal, and a plurality of current stages. Each current stage includes a converter coupled to the input power source for providing a current, and a switch circuit for selectively coupling the current in such current stage to the output terminal. A control circuit selectively decouples the input power source from less than all of the current stage converters upon detecting a low load condition, thereby reducing circulating current losses and improving operating efficiency under low load conditions.

Abstract: A switching power supply unit is provided, in which widening of the input voltage range can be achieved while suppressing production of a surge current. A transformer having two primary windings having the number of turns equal to each other, and two inductors are provided correspondingly to two switching circuits. By using an input voltage detection circuit, a control section, and connection changeover switches, when an input DC voltage is lower than a threshold voltage, a first current path and a second current path are connected in parallel to each other, and when the input DC voltage is higher than a threshold voltage, they are connected in series to each other. A turn ratio between the primary windings and secondary windings is large in a case of series connection compared with a case of parallel connection. Moreover, current is gently changes in the circuits by an effect of the inductors.

Abstract: An inverter includes an intermediate circuit, inverter bridge branches downstream of the intermediate circuit for outputting a power signal, and a controller operable for individually turning on and off the inverter bridge branches. The controller may individually turn on and off the inverter bridge branches as a function of an electrical quantity. The electrical quantity may be indicative of a voltage or a change in voltage occurring in the intermediate circuit during operation of the inverter. The electrical quantity may be indicative of the output power signal. The inverter bridge branches may include three inverter bridge branches.

Abstract: A program control circuit and method thereof selectively controls a supply time of a word line bias voltage depending on the number of program cycles being in progress. Therefore, over-programming of MLCs can be prevented and an overall program time can be shortened.

Abstract: A segmented search line circuit device for content addressable memory is provided. This device includes a content addressable memory and a segmented unit, wherein the content addressable memory has a plurality of cells arranged in an array and a search line connected between each pair of adjacent cells. Moreover, a first segmented unit is connected between the cells to divide the cells into a plurality of segments to search and between a pair of the adjacent segments to cut off the search lines between the pair of the adjacent segments. Because the circuit of this device is divided into a plurality of segments to search, the circuit of the search line driver need not be modified. As a result, this circuit device can diminish the loading capacitance of the search line driver and reduce the power consumption with the segmented search method.

Abstract: A CAM cell is provided that includes: an SRAM cell adapted to store a bit; a data line adapted to provide a corresponding comparand bit; an XOR gate adapted to XOR the stored bit and the comparand bit to provide an XOR output, and a switch adapted to close in response to the XOR output.

Abstract: Disclosed is a semiconductor memory device comprising a memory cell array block, and a circuit region arranged with the memory cell array block along a first direction. The circuit region comprises a first region and a second region arranged with the first region along the first direction. The first region is provided with a first circuit and a second circuit which are aligned in a second direction perpendicular to the first direction. The second region is provided with a plurality of third circuits which are aligned in the second direction.

Abstract: A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time.

Abstract: A nonvolatile ferroelectric memory device having a power control function improves a sensing margin by stably controlling a power applied to a cell capacitor. The sensing margin of a cell can be improved by controlling an operation voltage of the cell depending on an external supply voltage VEXT and applying a power voltage VCC obtained by dropping an external power voltage to adjacent circuits. Additionally, the reliability of a capacitor at a high voltage can be improved by employing a ferroelectric capcitor for stabilizing power to obtain capacitance of high capacity with a small area.

Abstract: An electronic device can include a static-random-access memory cell. The static-random-access memory cell can include a first transistor of a first type and a second transistor of a second type. The first transistor can have a first channel length extending along a first line, and the second transistor can have a second channel length extending along a second line. The first line and the second line can intersect at an angle having a value other than any integer multiple of 22.5°. In a particular embodiment, the first transistor can include a pull-up transistor, and the second transistor can include a pass gate or pull-down transistor. A process can be used to form semiconductor fins and conductive members, which include gate electrode portions, to achieve the electronic device including the first and second transistors.

Abstract: A method and apparatus implementing domino static random access memory (SRAM) leakage current reduction include a local evaluation circuit coupled to true and complement bit lines of a pair of local SRAM cell groups, receives precharge signals and provides an output connected to a global dot line. A sleep input is applied to SRAM sleep logic and a write driver including sleep control. Data true and data complement outputs of the write driver are forced to a respective selected level to discharge the bit lines and global dot lines when the sleep input transitions high. Discharging the bit lines and global dot lines is implemented through gating in the write driver without requiring any additional devices in the local evaluation circuit.

Abstract: A semiconductor memory device includes a memory cell block including a plurality of memory cells connected in series between first node and second node, the memory cells including a magnetoresistive element and a switching transistor, which are connected in parallel, the magnetoresistive element being a spin injection type and including a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction changes, and a non-magnetic layer interposed between the fixed layer and the recording layer, a bit line connected to the first node via a selection transistor, a word line connected to a gate of the switching transistor, and a write line connected to the second node.

Abstract: A magnetoresistive effect element includes a nonmagnetic layer having mutually facing first and second surfaces. A reference layer is provided on the first surface and has a fixed magnetization direction. A magnetization variable layer is provided on the second surface, has variable magnetization direction, and has a planer shape including a rectangular part, a first projected part, and a second projected part. The rectangular part has mutually facing first and second longer sides and mutually facing first and second shorter sides. The first projected part projects from the first longer side at a position shifted from the center toward the first shorter side. The second projected part projects from the second longer side at a position shifted from the center toward the second shorter side.

Abstract: A magnetization direction control method for controlling magnetization directions of first to third ferromagnetic layers (11-13) within a synthetic antiferromagnet structure (10A) having the first to the third ferromagnetic layers (11-13) and first and second non-magnetic layers (21, 22) interposed therebetween, without coupling antiferromagnetic material. The magnetization direction control method is composed of steps of (a) applying an external magnetic field HE to the synthetic antiferromagnet structure (10A) so as to direct the magnetizations of the first to third ferromagnetic layers in the same direction, and (b) reducing the external magnetic field to reverse the magnetization of one or some of the first to third ferromagnetic layers (11-13).

Abstract: Integrated circuit memory devices include a semiconductor substrate and a bit line on the semiconductor substrate. A plurality of memory cells is also provided. Each of these magnetic memory cells includes a magnetic storage element, a magnetic flux focusing layer on the magnetic storage element and an electrically insulating layer extending between the bit line and the magnetic flux focusing layer. This electrically insulating layer may contact an upper surface of the magnetic flux focusing layer and a lower surface of the bit line. The magnetic memory cell further includes a non-ferromagnetic electrically conductive layer extending between the magnetic flux focusing layer and the magnetic storage element. The electrically insulating layer is configured to cause current passing in a first direction (e.g.

Abstract: A memory may be implemented with a stable chalcogenide glass which is defined as a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to 200° C. for 30 minutes or less. Different states may be programmed by changing the threshold voltage of the material. The threshold voltage may be changed with pulses of different amplitude and/or different pulse fall times. Reading may be done using a reference level between the threshold voltages of the two different states. A separate access device is generally not needed.

Abstract: A ferromagnetic memory cell is disclosed. The cell includes a bit (10), made of a ferromagnetic material, having a remnant polarity. The cell also includes a read drive line (20) coupled to a first portion of the bit (10), to feed a current into the bit (10). A sense conductor (30) is coupled to a second portion of the bit (10), to receive the current from the bit (10). The current conducted through the bit (10) is responsive to the polarity of the bit (10). A method is also disclosed for determining the magnetic polarity of a ferromagnetic bit (10). In this method, a bit (10) is provided that is made of ferromagnetic material and has a remnant polarity. An input current (50) is fed into the bit (10) through a read drive line (20) coupled to a first portion of the bit (10). An output current (60) is received from the bit (10) through a sense conductor (30) coupled to a second portion of the bit (10). The current conducted through the bit (10) is responsive to the polarity of the bit (10).

Abstract: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.

Abstract: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

Abstract: A circuit of non-volatile memory which includes a plurality of memory units is disclosed. The memory unit comprises a first switch, a second switch, a data line, a voltage storage component, and a plurality of memory components connected in series. The first terminal of the first switch is coupled to the first voltage. The data line is coupled to the second terminal of the first switch. The first terminal of the voltage storage component is coupled to the data line, and the second terminal of the voltage storage component is coupled to the ground. The first terminal of the second switch is coupled the data line. In addition, the third terminal of each memory component is coupled to the first terminal of the next memory component, and the second terminal of the each memory component is coupled to second voltage.

Abstract: A bandgap engineered SONOS device structure for design with various AND architectures to perform a source side injection programming method. The BE-SONOS device structure comprises a spacer oxide disposed between a control gate overlaying an oxide-nitride-oxide-nitride-oxide stack and a sub-gate overlaying a gate oxide. In a first embodiment, a BE-SONOS sub-gate-AND array architecture is constructed multiple columns of SONONOS devices with sub-gate lines and diffusion bitlines. In a second embodiment, a BE-SONOS sub-gate-inversion-bitline-AND architecture is constructed multiple columns of SONONOS devices with sub-gate inversion bitlines and with no diffusion bitlines.

Abstract: A semiconductor memory device comprises a first pump clock generator configured to generate a first pump clock signal based on a first power supply voltage. The device also comprises a first charge pump configured to generate a first pump output voltage in response to the first pump clock signal. The device also comprises a second pump clock generator configured to generate a second pump clock signal based on the first pump output voltage. The device also comprises a second charge pump configured to generate a second pump output voltage in response to the second pump clock signal. The device also comprises a third pump clock generator configured to generate a third pump clock signal based on the first power supply voltage. The device also comprises a third charge pump configured to generate a third pump output voltage in response to the third pump clock signal.

Abstract: An erase-verify method for a NAND flash memory includes a serial double-step erase verify. A verify operation is performed on cells in the unit connected to even word lines by biasing all the even word lines at the read voltage value used in read mode, and by biasing all the odd word lines at the pass voltage value used in read mode of the selected unit. A verify operation is performed on the cells connected to odd word lines by biasing all the odd word lines at the read voltage value used in read mode and by biasing the all even word lines at the pass voltage value used in read mode of the selected unit. Verifying the odd and even word lines may be performed in either order.

Abstract: A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.

Abstract: An electrically erasable and programmable memory in which control gate transistors have been suppressed includes memory cells each with an access transistor and a floating gate transistor. A word line decoder is connected to word lines of the memory cells by a selection line connected to the gate terminals of the access transistors of the word line, and by a control gate line connected to the control gates of the floating gate transistors of the word line. Thus the voltage applicable to the gate terminals of the floating gate transistors is no longer limited by the voltage susceptible of being obtained on the source terminal of the control gate transistors.

Abstract: A number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behavior by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.

Abstract: A flash memory device, such as a NAND flash, having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A voltage source to supply programming voltages to control gates of the floating gate transistor memory cells is provided. The voltage source supplies a pre-charge voltage to the control gates of the floating gate transistor memory cells located in the first addressable block when data is programmed in memory cells of the second addressable block. Methods for pre-charging word lines in unselected array blocks are included.

Abstract: Methods and apparatus that may help reduce standby current in memory devices are provided. By separating equalizing and precharging functions into separate circuit structures, current paths between a source of precharge voltage and a defective wordline (e.g., having an inadvertent short to a bitline due to a manufacturing defect) may be eliminated.

Abstract: An internal voltage generator maintains stable level of an internal voltage without increasing physical area. The internal voltage generator includes an active level detector for detecting a level of an internal voltage by comparing the level of the internal voltage and a level of a reference voltage to thereby output a first active driving signal, a first active driver for providing the internal voltage in response to the first active driving signal, a driving time controller for generating a time driving signal activated for a predetermined time, an active driving controller for activating a second active driving signal while the time driving signal is activated and for outputting the first active driving signal as the second active driving signal while the time driving signal is inactivated, and a second active driver for providing the internal voltage in response to the second active driving signal.

Abstract: Provided is a semiconductor memory device including an internal power supply with low current consumption, which includes: an active interval security block for generating active interval security signals with operation intervals by a row active signal and a column active signal; an active driving signal generating block for generating an active driving signal, responsive to the active interval security signals; a standby driving block for holding the level of an internal voltage; and an active driving block, which is additionally driven based on the active driving signal to hold the internal voltage.

Abstract: A synchronous DRAM (SDRAM) terminates a write operation in response to detecting deactivation of a data strobe signal applied to it during the write operation. In one example, the SDRAM comprises a buffer circuit and an early write termination circuit. The buffer circuit is configured to sample input data responsive to a data strobe signal applied to the SDRAM during a write operation and direct the input data to one or more memory cells of the SDRAM for storing the input data. The early write termination circuit is configured to terminate the write operation at less than a programmed burst length by disabling access to one or more of the memory cells after storage of the sampled input data responsive to detecting deactivation of the data strobe signal.

Abstract: Methods and systems consistent with this invention comprise a control circuit for reading data from a memory comprising a plurality of data channels. Such control circuits comprise at least one multiplexer, wherein the at least one multiplexer is configured to route a data strobe signal to a first number of the plurality of data channels for reading the data from the memory when the at least one multiplexer is in a first selected state, and wherein the at least one multiplexer is configured to route the data strobe signal to a second number of the plurality of data channels, wherein the second number is greater than the first number, for reading the data from the memory when the at least one multiplexer is in a second selected state. Such methods and systems may also comprise a clock for generating a data strobe signal, and a flip-flop for latching the data from the memory into the control circuit with the data strobe signal, wherein the data strobe signal does not leave the control circuit.

Abstract: A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.

Abstract: A semiconductor memory device, including a plurality of programmable memory cells each one adapted to be brought into one among at least a first status and a second status, said plurality of memory cells including memory cells intended to store data, and means for accessing the memory cells for reading/modifying their status. At least one memory cell in said plurality is used as detector memory cell, and control means operatively associated with the at least one detector memory cell are provided, said control means being adapted to establishing a potential loss of the data stored in the memory cells of said plurality based on a detected first status of the at least one detector memory cell.

Abstract: A nonvolatile semiconductor memory device includes a memory cell having a MIS transistor configured to experience an irreversible change in transistor characteristics thereof to store data as the irreversible change, the MIS transistor having a gate node coupled to a word selecting line and a source/drain node coupled to a bit line, and the MIS transistor becoming conductive in response to a first state of the word selecting line and becoming nonconductive in response to a second state of the word selecting line, and a test circuit coupled to the bit line to sense a current running through the MIS transistor, the test circuit configured to indicate error in response to either a detection of presence of the current when the word selecting line is in the second state or a detection of absence of the current when the word selecting line is in the first state.

Abstract: A method for storage cell design evaluation provides accurate information about state changes in static storage cells. A wordline select pulse is propagated along the wordline select path of the test row to an output driver circuit, in order to test the clock and/or address timing of the row, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. An access detection cell holds the input of the output driver circuit until a simulated access operation activated by the wordline select pulse is complete. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.