Abstract: A method of fabricating a p-i-n type light emitting diode using p-type ZnO, and particularly, a technique for fabricating a p-type ZnO thin film doped with copper, a light emitting diode manufactured using the same, and its application to electrical and magnetic devices. The method of fabricating a p-i-n type light emitting diode using p-type ZnO includes depositing a low-temperature ZnO buffer layer on a sapphire single-crystal substrate, depositing an n-type gallium doped ZnO layer on the deposited low-temperature ZnO buffer layer, depositing an intrinsic ZnO thin film on the deposited n-type gallium doped ZnO layer, forming a p-type ZnO thin film layer on the deposited intrinsic ZnO thin film, forming a MESA structure on the p-type ZnO thin film layer through wet etching to obtain a diode structure, and subjecting the diode structure to post-heat treatment.

Abstract: A light emitting diode (LED) is made. The LED had a LiAlO2 substrate and a GaN layer. Between them, there is a zinc oxide (ZnO) layer. Because GaN and ZnO have a similar. Wurtzite structure, GaN can easily grow on ZnO. By using the ZnO layer, the GaN layer is successfully grown as a single crystal thin film on the LiAlO2 substrate. Thus, GaN defect density is reduced and lattice match is obtained to have a good crystal interface quality and an enhanced light emitting efficiency of a device thus made.

Abstract: A method to fabricate a device including a micro-electro-mechanical system structure and a monolithic integrated circuit comprises using a first wafer as a first substrate, fabricating the micro-electro-mechanical system structure on the first substrate, and forming a first oxide layer over the micro-electro-mechanical system structure. The method further comprises using a second wafer as a second substrate, fabricating the monolithic integrated circuit on the second substrate, and forming a second oxide layer over the monolithic integrated circuit. The first wafer and the second wafer are arranged so that the first oxide layer opposes the second oxide layer. The micro-electro-mechanical system structure is aligned with the monolithic integrated circuit, the first oxide layer is contacted with the second oxide layer; and bonded with the second oxide layer.

Abstract: The present invention is an etching mask used for fabricating of the MEMS resonator including an oscillator which both edges are fixed to a base substance and vibrates to a vibrating direction, and an electrode which is fixed to a base substance by vibration is impossible in parallel for the oscillator, and is placed every one or more at the both sides of the oscillator. The etching mask includes a mask pattern 36 for oscillators which covers an oscillator formation scheduled region 34 on a conductive film 30 formed all over a sacrificial film which covers a region of the principal surface except both edges of the oscillator, and a mask pattern 40 for electrodes which covers an electrode formation scheduled region 38 on a conductive film.

Abstract: A method for fabricating an image sensor includes forming an insulation layer over a substrate in a logic circuit region and a pixel region, forming a photoresist over the insulation layer, patterning the photoresist to form a photoresist pattern where the insulation layer in the pixel region is exposed and the insulation layer in the logic circuit region is not exposed, wherein a thickness of the photoresist pattern is gradually decreased in an interfacial region between the pixel region and the logic circuit region in a direction of the logic circuit region to the pixel region, and performing an etch back process over the insulation layer and the photoresist pattern in conditions that an etch rate of the photoresist pattern are substantially the same as that of the insulation layer.

Abstract: Provided is a method of fabricating a nano-wire array, including the steps of: depositing a nano-wire solution, which contains nano-wires, on a substrate; forming a first etch region in a stripe shape on the substrate and then patterning the nano-wires; forming drain and source electrode lines parallel to each other with the patterned nano-wires interposed therebetween; forming a plurality of drain electrodes which have one end connected to the drain electrode line and contact at least one of the nano-wires, and forming a plurality of source electrodes, which have one end connected to the source electrode line and contact the nano-wires that contact the drain electrodes; forming a second etch region between pairs of the drain and source electrodes so as to prevent electrical contacts between the pairs of the drain and source electrodes; forming an insulating layer on the substrate; and forming a gate electrode between the drain and source electrodes contacting the nano-wires on the insulating layer.

Abstract: An integrated circuit device with embedded passive component by flip-chip connection is provided which includes a flip chip and a dummy chip. The dummy chip includes at least an embedded passive component, a plurality of redistribution traces and a plurality of flip-chip pads. The flip chip is smaller than the dummy chip and is mounted on a surface of the dummy chip with the flip-chip pads. The embedded passive component is electrically connected to the flip chip via the redistribution traces and the flip-chip pads. A plurality of solder balls are placed at the peripheral region of the surface of the dummy chip.

Abstract: Two semiconductor substrates are first bonded together by means of a metal bump, while respective one-side surfaces on which device patterns are formed are faced each other, and a resin is then filled into a gap between the respective one-side surfaces and thereafter each of the semiconductor substrates is polished and thinned to a prescribed thickness. Furthermore, a via hole and an insulating film are formed; part of a portion in contact with the metal bump, of the insulating film, is opened; the inside of the via hole is filled with a conductor; and an electrode pad is formed on the conductor, to thereby form structures. Finally, a required number of structures are electrically connected with each other through the electrode pad and stacked to thereby obtain a semiconductor device.

Abstract: A method for manufacturing a semiconductor device having a substrate on which conductor wiring is disposed, electrodes provided to the conductor wiring, a semiconductor element connected to the electrodes, and a sealing member that covers the semiconductor element, comprises; mounting a plurality of semiconductor elements on the substrate in the X-axial direction and the Y-axial direction, forming marks in the X-axial direction, supplying the sealing material onto the substrate to continuously-covering the plurality of semiconductor elements arranged in the X-axial direction along the marks, dicing the sealing member and the substrate in the Y-axial direction to form cut planes of the sealing member and the substrate in substantially one plane and being a pair of cut planes opposite one another.

Abstract: A semiconductor package and method for making a semiconductor package are disclosed. The semiconductor package has a top surface and a mounting surface and includes a die, a conducting connecting material, a plating material and an insulating material. The die has a processed surface facing towards the mounting surface of the semiconductor package. Exposed metal connections are at the processed surface of the die. The conducting connecting material is disposed on the exposed metal connections. The plating material is in contact with the conducting connecting material. The insulating material is formed around the conducting connecting material, and the plating material extends to the exterior of the insulating material.

Abstract: Semiconductor device assembly die attach apparatus and methods are disclosed for improvements in attaching a semiconductor die to a die pad. Preferred methods of the invention include steps for positioning a semiconductor die on a bearing surface of a collet and retaining the die on the bearing surface of the collet using a vacuum force. A pushing force is also exerted on the die adjacent to the applied vacuum force. The pushing force opposes flexion of the die in the direction of the vacuum force. In further steps, the die is placed on a die pad, and die attach adhesive is interposed between the die and the die pad. A preferred method includes applying a pushing force to bow the central region of the die toward the die pad. In a preferred apparatus of the invention, a collet has a body including a bearing surface for receiving a die and a vacuum for holding it. A chamber encompassed by the bearing surface is adapted for applying the force of expelled gas against a die borne on the bearing surface.

Abstract: A semiconductor structure comprising a substrate including a first layer comprising a first material having a first modulus of elasticity; a first structure comprising a conductor and formed within the substrate, the first structure having an upper surface; and a stress diverting structure proximate the first structure and within the first layer, the stress diverting structure providing a low mechanical stress region at the upper surface of the first structure when a physical load is applied to the first structure, wherein said low mechanical stress region comprises stress values below the stress values in areas not protected by the stress diverting structure. The stress diverting structure comprises a second material having a second modulus of elasticity less than the first modulus of elasticity, the second material selectively formed over the upper surface of the first structure for diverting mechanical stress created by the physical load applied to the first structure.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a core portion of a TIM, wherein the core portion comprises a high thermal conductivity and does not comprise indium, and forming an outer portion of the TIM on the core portion.

Abstract: A process for producing a pre-plated leadframe that has enhanced adhesion by molding compound is provided, wherein a base leadframe material is first plated with multiple layers of metallic material. Thereafter, the plated base leadframe material is covered with a mask, so as to expose selected surfaces thereof at unmasked areas where enhanced adhesion of molding compound is desired. The said unmasked areas are plated with a layer of copper before removing the mask. Optionally, the layer of copper may further be oxidized to form a layer of specially controlled copper oxide.

Abstract: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, at least two leads, and at least two bond wires. Each of the leads may have a reduced-thickness inner length adjacent terminals of the microelectronic component and a body having an outer surface spaced farther from the microelectronic component than a bond surface of the inner length. Each of the bond wires couples the microelectronic component to one of the leads and has a maximum height outwardly from the microelectronic component that is no greater than the height of the outer surface of the lead.

Abstract: In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. A method of manufacture of a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for SRAM, DRAM, and NVM devices.

Abstract: An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at least a portion of the diode and at least a portion of the NMOS device collectively form an ESD protection device.

Abstract: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

Abstract: A method of fabricating a bipolar transistor in a first trench (11) is disclosed wherein only one photolithographic mask is applied which forms a first trench (11) and a second trench (12). A collector region (21) is formed self-aligned in the first trench (11) and the second trench (12). A base region (31) is formed self-aligned on a portion of the collector region (21), which is in the first trench (11). An emitter region (41) is formed self-aligned on a portion of the base region (31). A contact to the collector region (21) is formed in the second trench (12) and a contact to the base region (31) is formed in the first trench (11). The fabrication of the bipolar transistor may be integrated in a standard CMOS process.

Abstract: The invention relates to a method for forming a uniform silicide film using a crystalline semiconductor film in which orientation of crystal planes is controlled, and a method for manufacturing a thin film transistor with less variation in electric characteristics, which is formed over an insulating substrate using the silicide film. A semiconductor film over which a cap film is formed is irradiated with a laser to be crystallized under the predetermined condition, so that a crystalline semiconductor film including large grain crystals in which orientation of crystal planes is controlled in one direction is formed. The crystalline semiconductor film is used for silicide, whereby a uniform silicide film can be formed.

Abstract: A method for selectively forming a dielectric layer. An embodiment comprises forming a dielectric layer, such as an oxide layer, on a semiconductor substrate, depositing a silicon layer on the dielectric layer, and treating the silicon layer with nitrogen, thereby converting the silicon layer into a silicon nitride layer. This method allows for a protective silicon nitride layer to be formed, while also preventing and/or reducing the nitrogen itself from penetrating far enough to contaminate the substrate. In another embodiment the treating with nitrogen is continued to form not only a silicon nitride, but to also diffuse a small portion of nitrogen into the dielectric layer to nitridized a portion of the dielectric layer. Optionally, an anneal could be performed to repair any damage that has been done by the treatment process.

Abstract: A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer.

Abstract: Method and system for forming gate structure with controllable oxide. The method includes a step for providing a semiconductor substrate and defining a source region and a drain region within the semiconductor substrate. Furthermore, the method includes a step for defining a gate region positioned between the source region and the drain region. Moreover, the method provides a step for forming a first layer overlaying the gate region. The first layer includes silicon nitride and/or silicon oxynitride material. Also, the method includes a step for forming a second layer by subjecting the semiconductor substrate to at least oxygen at a predetermined temperature range for a period of time. The second layer has a thickness less than 20 Angstroms.

Abstract: A complementary metal-oxide semiconductor (CMOS) device includes an NMOS thin body channel including a silicon epitaxial layer. An NMOS insulating layer is formed on a surface of the NMOS thin body channel and surrounds the NMOS thin body channel. An NMOS metal gate is formed on the NMOS insulating layer. The CMOS device further includes a p-channel metal-oxide semiconductor (PMOS) transistor including a PMOS thin body channel including a silicon epitaxial layer. A PMOS insulating layer is formed on a surface of and surrounds the PMOS thin body channel. A PMOS metal gate is formed on the PMOS insulating layer. The NMOS insulating layer includes a silicon oxide layer and the PMOS insulating layer includes an electron-trapping layer, the NMOS insulating layer includes a hole trapping dielectric layer and the PMOS insulating layer includes a silicon oxide layer, or the NMOS insulating layer includes a hole-trapping dielectric layer and the PMOS insulating layer includes an electron-trapping dielectric layer.

Abstract: A CMOS device includes high k gate dielectric materials. A PMOS device includes a gate that is implanted with an n-type dopant. The NMOS device may be doped with either an n-type or a p-type dopant. The work function of the CMOS device is set by the material selection of the gate dielectric materials. A polysilicon depletion effect is reduced or avoided.

Abstract: A method of manufacturing a CMOS semiconductor comprising, forming shallow trench isolation regions in a workpiece, depositing a gate oxide layer on top of the workpiece, depositing a polysilicon layer on top of the gate oxide, performing VTN patterning, performing first series of adjusted implantations, performing post implantation cleaning, performing VTP patterning, performing a second series of adjusted implantations, performing the post implantation cleaning, performing a well implant damage anneal; patterning gate, etching gate, and performing back end of line processing.

Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

Abstract: One embodiment of the present invention relates to a method of fabricating a multi-gate transistor. During the method a second gate electrode material is selectively removed from a semiconductor structure from which the multi-gate transistor is formed, thereby exposing at least one surface of a first gate electrode material. The exposed surface of the first gate electrode material is deglazed. Subsequently, the first gate electrode material is removed. Other methods and devices are also disclosed.

Abstract: A semiconductor device comprises a semiconductor substrate, a MOSFET including a double gate structure provided on the semiconductor substrate, and an isolation region for isolating the MOSFET from other elements comprising a trench provided on the surface of the semiconductor substrate and an insulator provided in the trench, a part of the isolation region in the trench around the MOSFET having a bottom deeper than other part of the isolation region.

Abstract: A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate.

Abstract: The invention includes semiconductor processing methods in which openings are formed to extend into a semiconductor substrate, and the substrate is then annealed around the openings to form cavities. The substrate is etched to expose the cavities, and the cavities are substantially filled with insulative material. The semiconductor substrate having the filled cavities therein can be utilized as a semiconductor-on-insulator-type structure, and transistor devices can be formed to be supported by the semiconductor material and to be over the cavities. In some aspects, the transistor devices have channel regions over the filled cavities, and in other aspects the transistor devices have source/drain regions over the filled cavities. The transistor devices can be incorporated into dynamic random access memory, and can be utilized in electronic systems.

Abstract: Integrated circuit devices include an integrated circuit substrate having a channel region therein. A gate pattern is disposed on a top surface of the channel region. A depletion barrier layer covers a surface of the integrated circuit substrate adjacent opposite sides of the gate pattern and extending along a portion of a lateral face of the channel region. A source/drain layer is disposed on the depletion barrier layer and electrically contacting the lateral face of the channel region in a region not covered by the depletion barrier layer. The channel region may protrude from a surface of the substrate. The depletion barrier layer may be an L-shaped depletion barrier layer and the device may further include a device isolation layer disposed at a predetermined portion of the substrate through the source/drain layer and the depletion barrier layer. The depletion barrier layer and the device isolation layer may be formed of the same material.

Abstract: One embodiment of the present invention relates to a method of processing a semiconductor device. During the method an amorphization implant is performed to amorphize a selected region of a semiconductor structure. The amorphized selected region is then removed by performing a recess etch that is selective thereto. Other methods and systems are also disclosed.

Abstract: An electronic device and method for forming same. The electronic device includes a source and drain region. Each region has an uppermost portion comprised of a first silicide where the first silicide is overlaid with a first dielectric layer. The electronic device further includes a gate region having an uppermost portion comprised of a second silicide. The second silicide is both thicker than the first silicide and has a lower resistivity than the first silicide with at least a portion of the second silicide being formed in an opening in the first dielectric layer.

Abstract: A resistor capacitor structure and a method of fabrication. A resistor capacitor structure provides a capacitance between at least two nodes within a microelectronic circuit. A bottom plate of the resistor capacitor structure comprises a resistance layer, which in turn provides a resistance path between an additional node within the circuit. The resistor capacitor structure may be formed on top or within interlevel dielectric layers. The resistance layer, alternatively, may be used to fill a cavity located between interlevel dielectric layers and accordingly provide a resistance path between the interlevel dielectric layers.

Abstract: A method for selectively forming an electric conductor, the method including disposing a processing target and a metal compound in an atmosphere including a supercritical fluid, the processing target having formed thereon at least one recess for providing an electric conductor, the metal compound including a metal serving as a main component of the electric conductor, and dissolving at least part of the metal compound in the supercritical fluid, selectively introducing the metal compound dissolved in the supercritical fluid into the recess in contact with a surface of the processing target, and coagulating in the recess the metal compound introduced into the recess to precipitate the metal from the metal compound, and coagulating the metal precipitated in the recess, thereby providing the electric conductor in the recess.

Abstract: A dynamic random access memory (DRAM) is provided. The dynamic random access memory includes a deep trench capacitor disposed in a first trench of a substrate, a conductive layer disposed in a second trench of the substrate, a gate structure, and a conductive layer disposed on the surface of the substrate at two sides of the gate structure. The depth of the second trench is smaller than the depth of the first trench, and the second trench partially overlaps with the first trench. The conductive layer disposed in the second trench is electrically connected with the conductive layer of the deep trench capacitor. The gate structure is disposed on the substrate. The conductive layer at one side of the gate structure is electrically connected with the conductive layer disposed in the second trench.

Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.

Abstract: A method for manufacturing a semiconductor device includes: forming a first semiconductor layer and a second semiconductor layer sequentially on a semiconductor substrate; forming a first groove penetrating the first semiconductor layer and the second semiconductor layer by partially etching the first semiconductor layer and the second semiconductor layer; forming a support covering the second semiconductor layer from inside of the first groove to a surface of the second semiconductor layer so as to support the second semiconductor layer; etching a sidewall formed in the first groove of the support so as to render the sidewall thin; forming a second groove exposing the first semiconductor layer by sequentially etching a part of the second semiconductor layer and a part of the first semiconductor layer; forming a cavity between the semiconductor substrate and the second semiconductor layer by etching the first semiconductor layer through the second groove under an etching condition in which the first semicondu

Abstract: A method for removing a material from a trench in a semiconductor. The method includes placing the semiconductor in a vacuum chamber, admitting a reactant into the chamber at a pressure to form a film of the reactant on a surface of the material, controlling the composition and residence time of the film on the surface of the material to etch at least a portion of the material, and removing any unwanted reactant and reaction product from the chamber or the surface of the material.

Abstract: A method for forming a single die includes forming at least one first active device over a first substrate and at least one first metallic layer coupled to the first active device. At least one second metallic layer is formed over a second substrate, wherein the second substrate does not include any active device The at least one fist metallic layer is bonded with the at least one second metallic layer such that the first substrate and the second substrate constitute a single die.

Abstract: A manufacturing method for devices including a wafer supporting step of mounting an adhesive film to the lower surface of a wafer and attaching the wafer through the adhesive film to the upper surface of a dicing tape mounted on an annular frame, a laser processing step of applying a pulsed laser beam having an absorption wavelength to the wafer along separation lines formed on the upper surface of the wafer after mounting the adhesive film to the dicing tape, thereby separating the wafer into the individual devices and cutting the adhesive film, and a pickup step of expanding the dicing tape after performing the laser processing step to thereby increase the spacing between any adjacent ones of the individual devices, and peeling off to pick up each of the individual devices from the dicing tape in the condition where the adhesive film is mounted on the lower surface of each device.

Abstract: A method of manufacturing a device includes the steps of forming dividing grooves with a predetermined depth along planned dividing lines of a wafer, then grinding the backside surface of the wafer to expose the dividing grooves on the back side and to divide the wafer into individual devices, mounting a UV-curing adhesive film to the backside surface of the wafer divided into the individual devices, adhering the adhesive film side of the wafer to a dicing tape attached to an annular frame, radiating UV rays from the face side of the wafer to cure the regions of the adhesive film which correspond to the dividing grooves, expanding the dicing tape to exert tensile forces on the adhesive film, so as to split the adhesive film into the individual devices, with the cured regions of the adhesive film as starting points of splitting, and releasing the device from the dicing tape and thereby picking up the device.

Abstract: A break pattern is formed on a silicon wafer using an anisotropic etching process. The break pattern includes a plurality of through holes, each of having a first plane perpendicular to a plane defined by the silicon wafer, a second plane opposite to the first plane, a third plane that is perpendicular to the plane of the silicon wafer and intersects the first plane at an acute angle, and a fourth plane that is opposite to the third plane, is perpendicular to the plane of the silicon wafer, and intersects the second plane at an acute angle. The anisotropic etching is performed using a mask pattern having a predetermined shape to form, around the break pattern, a thin portion that has a smaller thickness than other portions of the silicon wafer. The silicon wafer is then divided into a plurality of silicon substrates along the break pattern.

Abstract: An object of the present invention is to provide a method for fabricating a semiconductor device to fabricate a semiconductor device. To achieve such an object, the present invention relates to a method for fabricating a semiconductor device composed of a hetero-junction substrate formed of a semiconductor substrate, and a heterogeneous substrate made of a material other than semiconductor bonded to a surface of the semiconductor substrate. A dicing step of cutting the hetero-junction substrate into semiconductor chips comprises a first dicing step of forming grooves having a depth of at least the thickness of the semiconductor substrate on the surface of the semiconductor substrate; and a second dicing step of cutting the entire hetero-junction substrate along the grooves to divide the hetero-junction substrate into a plurality of semiconductor chips.

Abstract: A system for the laser scribing of semiconductor devices includes a laser light source operable to selectably deliver laser illumination at a first wavelength and at a second wavelength which is shorter than the first wavelength. The system further includes a support for a semiconductor device and an optical system which is operative to direct the laser illumination from the light source to the semiconductor device. The optical system includes optical elements which are compatible with the laser illumination of the first wavelength and the laser illumination of the second wavelength. In specific instances, the first wavelength is long wavelength illumination such as illumination of at least 1000 nanometers, and the second wavelength is short wavelength illumination which in specific instances is 300 nanometers or shorter. By the use of the differing wavelengths, specific layers of the semiconductor device may be scribed without damage to subjacent layers. Also disclosed are specific scribing processes.

Abstract: The principal objects of the present invention are to provide structure of a semiconductor device capable of reducing a bowing of a wafer, and a method for fabricating the semiconductor device. The present invention is applied to a semiconductor device, which is fabricated with a semiconductor substrate having a silicon carbide (SiC) film. The method includes the steps of: forming the SiC film on a semiconductor wafer; discriminating a deformation condition of the semiconductor wafer; and forming grooves in the SiC film, the grooves having a shape determined in accordance with the deformation condition of the semiconductor wafer.

Abstract: An SOI wafer which does not generate slip dislocation even if laser annealing is performed for no more than 0.1 seconds at a maximum temperature of 1200° C. or more is provided. This wafer is an SOI wafer used for a process of manufacturing a semiconductor device, in which laser annealing is conducted for no more than 0.1 seconds at a maximum temperature of 1200° C. or more, which includes an active layer, a support layer of a monocrystaline silicon, and an insulated oxide film layer between the active layer and the support layer, wherein light-scattering defect density measured by a 90° light scattering method at the depth region of 260 ?m toward the support layer side from an interface between the insulated oxide film layer and the support layer is 2×108/cm3 or less.

Abstract: A method of fabricating a semiconductor device includes providing a substrate, forming an amorphous silicon layer over the substrate, forming a patterned heat retaining layer over the amorphous silicon layer, doping the amorphous silicon layer to form a pair of doped regions in the amorphous silicon layer by using the patterned heat retaining layer as a mask, and irradiating the amorphous silicon layer to activate the pair of doped regions, forming a pair of activated regions, and form a crystallized region between the pair of activated regions.

Abstract: The present invention relates to a method for manufacturing a polycrystalline semiconductor film that can be used for a semiconductor device. In the method, an amorphous semiconductor film is irradiated with a femtosecond laser to be crystallized. By laser irradiation using a femtosecond laser, when an amorphous semiconductor film over which a cap film is formed is crystallized with a laser, it becomes possible to perform crystallization of the semiconductor film and removal of the cap film at the same time. Therefore, a step of removing the cap film in a later step can be omitted.