Abstract: A method of making a solar grade silicon wafer is disclosed. In at least some embodiments of this invention, the method includes the follow steps: providing a slurry including a liquid that essentially prevents the oxidation of silicon powder and a silicon powder that is essentially free of oxides; providing a solar grade wafer mold defining an interior for receiving the slurry; introducing the slurry into the solar grade wafer mold; precipitating the silicon powder from the slurry to form a preform of the solar grade silicon wafer; and crystallizing the preform to make the solar grade silicon wafer.

Abstract: There is provided a method for preparing an AlGaN crystal layer having an excellent surface flatness. A buffer layer effective in stress relaxation is formed on a template substrate having a surface layer that is flat at a substantially atomic level and to which in-plane compressive stress is applied, and an AlGaN layer is formed on the buffer layer, so that an AlGaN layer can be formed that is flat at a substantially atomic level. Particularly when the surface layer of the template substrate includes a first AlN layer, a second AlN layer may be formed thereon at a temperature of 600° C. or lower, while a mixed gas of TMA and TMG is supplied in a TMG/TMA mixing ratio of 3/17 or more to 6/17 or less, so that a buffer layer effective in stress relaxation the can be formed in a preferred manner.

Abstract: A method of forming a selective area semiconductor compound epitaxy layer is provided. The method includes the step of using two silicon-containing precursors as gas source for implementing a process of manufacturing the selective area semiconductor compound epitaxy layer, so as to form a semiconductor compound epitaxy layer on an exposed monocrystalline silicon region of a substrate.

Abstract: There are provided a plasma doping method and an apparatus which have excellent reproducibility of the concentration of impurities implanted into the surfaces of samples. In a vacuum container, in a state where gas is ejected toward a substrate placed on a sample electrode through gas ejection holes provided in a counter electrode, gas is exhausted from the vacuum container through a turbo molecular pump as an exhaust device, and the inside of the vacuum container is maintained at a predetermined pressure through a pressure adjustment valve, the distance between the counter electrode and the sample electrode is set to be sufficiently small with respect to the area of the counter electrode to prevent plasma from being diffused outward, and capacitive-coupled plasma is generated between the counter electrode and the sample electrode to perform plasma doping. The gas used herein is a gas with a low concentration which contains impurities such as diborane or phosphine.

Abstract: A method, process and system for the recycling of electrochemical-mechanical planarization slurries/electrolytes as they are used in the back end of line of the semiconductor wafer manufacturing process is disclosed. The method, process and system includes with the removal of metal ions from slurries using ion exchange media and/or electrochemical deposition.

Abstract: Semiconductor material strips are secured to substrates in such a way as to stress the semiconductor material. The strips of semiconductor material may be compressively stressed, subjected to tensile stress, or some strips may be compressively stressed while other strips are tensilely stressed. Stress may be induced by forming non-planarities on the surface of the substrate to which the strips are to be secured. The non-planarities may be configured to stress strips of semiconductor material as the strips are secured thereover and over an intervening surface of the substrate, or to stress strips as the non-planarities are removed from beneath the strips. The strain that ultimately results from stressing the strips improves carrier mobility (i.e., electron mobility, electron hole pair, or “hole,” mobility) relative to the carrier mobilities of unstrained semiconductor materials. The strained strips of semiconductor material may be used in the fabrication of semiconductor device structures such as transistors.

Abstract: A method for manufacturing a semiconductor device includes forming a gate conductive layer, a first mask layer, a second mask layer, and a third mask layer over a semiconductor substrate that includes a cell region and a peripheral region. The method also includes forming a second mask pattern and a third mask pattern using a gate mask. The method further includes trimming the second mask pattern in the peripheral region to form a fourth mask pattern having a size smaller than that of the second mask pattern. Still further, the method includes removing the third mask pattern, and patterning the first mask layer and the gate conductive layer using the fourth mask pattern as a mask.

Abstract: Disclosed is a method for manufacturing a semiconductor device. More specifically, in the invention, a gate pattern is formed and then an interlayer insulating pattern burying the space between the gate patterns is formed to ensure the region into which a landing plug contact hole has to be opened, thereby avoiding a problem in that the landing plug contact hole is not opened when forming the landing plug contact hole in a subsequent process. As a result, a failure that may occur in a subsequent test process can be avoided and further a current drivability of a gate, a tWR feature and a timing margin are ensured and thereby improve the device features.

Abstract: Provided is a manufacturing method of a semiconductor device which has the following steps of forming a plurality of layered patterns obtained by stacking an insulating film, a conductor film for forming a floating gate electrode and another insulating film over a semiconductor substrate in the order of mention, forming sidewalls over the side surfaces of the plurality of layered patterns, removing a damage layer of the semiconductor substrate between any two adjacent layered patterns by dry etching, forming an insulating film over the semiconductor substrate between two adjacent layered patterns, and forming a plurality of assist gate electrodes over the insulating film between two adjacent layered patterns in self alignment therewith. According to the present invention, a semiconductor device having a flash memory has improved reliability.

Abstract: A method of forming a fine pattern in a semiconductor device includes forming an target layer, a hard mask layer and first sacrificial patterns on a semiconductor substrate; forming an insulating layer and a second sacrificial layer on the hard mask layer and the first sacrificial patterns; performing the first etch process so as to allow the second sacrificial layer remain on the insulating layer between the first sacrificial patterns for forming second sacrificial patterns; removing the insulating layer placed on the first sacrificial patterns and between the first and second sacrificial patterns; etch the hard mask layer through the second etch process utilizing the first and second sacrificial patterns as the etch mask to form a mask pattern; and etch the target layer through the third etch process utilizing the hard mask pattern as the etch mask.

Abstract: A method for fabricating a semiconductor device includes providing a substrate where a cell region and a peripheral region are defined, stacking a conductive layer, a hard mask layer, a metal-based hard mask layer, and an amorphous carbon (C) pattern over the substrate etching the metal-based hard mask layer using the amorphous C pattern as an etch mask, thereby forming a resultant structure, forming a photoresist pattern covering the resultant structure in the cell region while exposing the resultant structure in the peripheral region, decreasing a width of the etched metal-based hard mask layer in the peripheral region, removing the photoresist pattern and the amorphous C pattern, and forming a conductive pattern by etching the hard mask layer and the conductive layer using the etched metal-based hard mask layer as an etch mask.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.

Abstract: A method of placing wires for placing a shield wire with respect to a shield subject wire placed on a chip, a method includes setting a plurality of wire tracks on the chip, dividing the chip into at least a first area and a second area according to a division boundary, confirming whether the shield subject wire exists around the division boundary in the second area when the division boundary is not laid on top of the wire track, and determining whether to place the shield wire on a wire track being adjacent to division boundary in the first area based on the confirming.

Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate, forming a trench in the first insulating film, forming a metal interconnect in the trench, exposing the surface of the metal interconnect to a silicon-containing gas, performing a plasma treatment of the surface of the metal interconnect after exposing to the silicon-containing gas, and forming a second insulating film over the metal interconnect.

Abstract: An etching method for semiconductor element is provided. The etching method includes the following procedure. First, a to-be-etched substrate is provided. Then, a silicon-rich silicon oxide (SRO) layer is formed on the to-be-etched substrate. Afterwards, an anti-reflective layer is formed on the SRO layer. Then, a patterned photo resist layer is formed on the anti-reflective layer. Afterwards, the anti-reflective layer, the SRO layer and the to-be-etched substrate is etched so as to form an opening.

Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

Abstract: A method of manufacturing an integrated circuit (IC) chip is provided. The method includes the following steps. First, a substrate is provided. The substrate is divided into an internal region and an external region by a die seal ring region. A number of circuit units are then formed in the internal region on the substrate. Thereafter, a dielectric layer is formed over the substrate, interconnects are formed in the dielectric layer within the internal region, and a number of bonding pad structures are formed in the dielectric layer within the external region. Finally, a cutting process is performed along a number of scribed lines on the substrate to form a number of chips. The bonding pad structures are exposed at the sides of each chip.

Abstract: A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is conformally deposited over the contact points, and a second material layer is deposited. A photoresist layer is applied and patterned to leave remaining portions. The remaining portions are trimmed to produce trimmed remaining portions which overlie eventual contact holes to the contact points. Using the trimmed remaining portions as an etch mask, exposed portions the second material layer are etched away to leave sacrificial plugs. The sacrificial plugs are etched away to form contact holes that reach portions the first material layers. Another etching step is performed to extend the contact holes to produce final contact holes that extend to the contact points.

Abstract: A method for fabricating a conductive layer is provided. First, a substrate is provided and a patterned adhesion layer is formed on the substrate. Next, a chemical plating process is performed to form a first metal layer on the patterned adhesion layer by placing the substrate in an electroplating solution and the electroplating solution is shocked. Thereafter, a second metal layer is formed on the first metal layer by performing a plating process.

Abstract: The present invention relates to a method for producing electrical bushings through non-conductive or semiconductive substrates, which are particularly suitable for electrical applications. The method is characterized in that a semiconductor substrate or a non-conductive substrate (13) whose front side has an electrically conductive contact point (6) at least one location is provided with a recess (7) from its rear side such that the recess (1) on the front side of the substrate ends under that location or one of the locations at which the electrically conductive contact point or one of the electrically conductive contact points is situated and is completely covered by the latter, to which an electrically conductive structure (9) which establishes a conductive connection between the respective contact point and the rear-side surface (10, 11, 12) of the substrate through the recess or at least one of the recesses is applied from the rear side of the substrate.

Abstract: A technique for making a bulk isolated PN diode is disclosed. In one embodiment, a method may include providing a substrate having a doped region and disposing a dielectric material over the doped region. The method may also include forming first and second holes in the dielectric material exposing the doped region, and forming respective first and second polysilicon plugs within the first and second holes over the doped region. In one embodiment, the first and second polysilicon plugs are doped opposite one another such that a PN junction is formed between the first or second polysilicon plug and the doped region of the substrate, and has a cross-sectional area generally defined by the first or second hole adjacent the PN junction. Various devices, systems, and other methods are also disclosed.

Abstract: A contact hole is formed in an interlayer insulating layer disposed on a semiconductor substrate. The semiconductor substrate is loaded into a reaction chamber. A reaction gas including an aluminum precursor is injected into the reaction chamber. Reaction energy is supplied to the reaction chamber so as to allow thermal decomposition of the aluminum precursor. The injecting of the reaction gas and the supplying of the reaction energy are periodically repeated to deposit a first aluminum layer on the semiconductor substrate. A second aluminum layer is deposited to fill the contact hole.

Abstract: Disclosed are embodiments of a semiconductor structure with a partially selfaligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole.

Abstract: Switches having an in situ grown carbon nanotube as an element thereof, and methods of fabricating such switches. A carbon nanotube is grown in situ in mechanical connection with a conductive substrate, such as a heavily doped silicon wafer or an SOI wafer. The carbon nanotube is electrically connected at one location to a terminal. At another location of the carbon nanotube there is situated a pull electrode that can be used to electrostatically displace the carbon nanotube so that it selectively makes contact with either the pull electrode or with a contact electrode. Connection to the pull electrode is sufficient to operate the device as a simple switch, while connection to a contact electrode is useful to operate the device in a manner analogous to a relay. In various embodiments, the devices disclosed are useful as at least switches for various signals, multi-state memory, computational devices, and multiplexers.

Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.

Abstract: A method for manufacturing MOS transistor with hybrid hard mask includes providing a substrate having a dielectric layer and a polysilicon layer thereon, forming a hybrid hard mask having a middle hard mask and a spacer hard mask covering sidewalls of the middle hard mask on the polysilicon layer, performing a first etching process to etch the polysilicon layer and the dielectric layer through the hybrid hard mask to form a gate structure, performing a second etching process to form recesses in the substrate at two sides of the gate structure, and performing a SEG process to form epitaxial silicon layers in each recess.

Abstract: In one aspect, there us provided a method of manufacturing a semiconductor device that comprises placing an oxide layer over a gate electrode and sidewall spacers located adjacent thereto, placing a protective layer over the oxide layer, conducting a plasma etch to remove portions of the protective layer and the first oxide layer that are located over the gate electrode and expose a surface of the gate electrode, wherein the plasma etch is selective to polysilicon. A soft etch is conducted subsequent to the plasma etch. The soft etch includes an inorganic-based fluorine containing gas and an inert gas, wherein the plasma etch leaves a film on the gate electrode that inhibits silicidation of the gate electrode and wherein the soft etch removes the film. The gate electrode is silicided with a metal subsequent to conducting the soft etch.

Abstract: A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the layer of material. The resist mask does not cover the trench. The layer of material is isotropically etched. An etch depth may be determined from a characteristic of etching of the material underneath the mask. Such a method may be used for forming SGT structures. The wafer may comprise a layer of material disposed on at least a portion of a surface of semiconductor wafer; a resist mask comprising an angle-shaped test portion disposed over a portion of the layer of material; and a ruler marking on the surface of the substrate proximate the test portion.

Abstract: Methods and apparatuses for removing polysilicon material from a semiconductor workpiece are disclosed. A particular method includes contacting a polishing pad with a semiconductor workpiece having a surface polysilicon material. The method also includes disposing a polishing liquid between the polysilicon material and the polishing pad. The polishing liquid contains an oxidizer that does not include metal elements. The method further includes moving at least one of the semiconductor workpiece and the polishing pad relative to the other while the semiconductor workpiece contacts the polishing pad and the polishing liquid. At least some of the polysilicon material is removed while the polysilicon material contacts the oxidizer in the polishing liquid, as at least one of the semiconductor workpiece and the polishing pad moves relative to the other.

Abstract: A method for forming fine patterns in a semiconductor device includes forming a first hard mask layer over an etch target layer, forming first etch mask patterns having negative slopes over the first hard mask layer, thereby forming a resultant structure, forming a first material layer for a second etch mask over the resultant structure, performing a planarization process until the first etch mask patterns are exposed to form second etch mask patterns filled in spaces between the spacers, removing the spacers, and etching the first hard mask layer and the etch target layer using the first etch mask patterns and the second etch mask patterns.

Abstract: Methods of uniformly delayering an IC chip are disclosed. One embodiment includes: performing an ash on the wafer including an Al layer thereof and etching the Al layer; polishing an edge of the wafer using a slurry including an approximately 30 ?m polishing particles; removing the aluminum layer and at least one metal layer by polishing using a slurry including approximately 9 ?m diamond polishing particles and a non-abrasive backside of a polishing sheet; removing any remaining metal layers to a first metal layer by polishing using a slurry including approximately 3 ?m diamond polishing particles and the non-abrasive backside of a polishing sheet; removing any scratches by polishing using a slurry including approximately 1 ?m diamond polishing particles and the non-abrasive backside of a polishing sheet; and removing the first metal layer to a polyconductor layer by polishing using a colloidal slurry including approximately 0.25 ?m diamond polishing particles.

Abstract: Provided is a method for manufacturing a floating structure of a MEMS. The method for manufacturing a floating structure of a microelectromechanical system (MEMS), comprising the steps of: a) forming a sacrificial layer including a thin layer pattern doped with impurities on a substrate; b) forming a support layer on the sacrificial layer; c) forming a structure to be floated on the support layer by using a subsequent process; d) forming an etch hole exposing both side portions of the thin layer pattern; and e) removing the sacrificial layer through the etch hole to form an air gap between the support layer and the substrate.

Abstract: A method of manufacturing a semiconductor device has polishing a film, and cleaning a polished surface by carrying out a first exposing the polished surface to an acidic first cleaning fluid having an effect of etching at least a partial region of the polished surface, and a second exposing the polished surface to an alkaline second cleaning fluid after the first exposing.

Abstract: A substrate peripheral film-removing apparatus which is capable of removing a film from a substrate periphery without complicating the construction of the apparatus. A wafer chamber receives a wafer having an SiO2 film formed on a periphery thereof. In a beveled portion-receiving chamber, film-removing chemical processing is carried out on at least part of the beveled portion of the wafer, using a process gas.

Abstract: A method of removing and/or reducing undesirable contaminants removes residues including graphitic layers, fluorinate layers, calcium sulfate (CaSO4) particles, tin oxides and organotin, from a chip passivation layer surface. The method uses a plasma process with an argon and oxygen mixture with optimized plasma parameters to remove both the graphitic and fluorinated layers and to reduce the level of the inorganic/tin oxides/organotin residue from an integrated circuit wafer while keeping the re-deposition of metallic compounds is negligible. This invention discloses the plasma processes that organics are not re-deposited from polymers to solder ball surfaces and tin oxide thickness does not increase on solder balls. The ratio of argon/oxygen is from about 50% to about 99% Ar and about 1% to about 50% O2 by volume. Incoming wafers, after treatment, are then diced to form individual chips that are employed to produce flip chip plastic ball grid array packages.

Abstract: In a semiconductor device manufacturing apparatus that processing a substrate by applying a voltage to a gas to create a plasma, positively charged particles are trapped or guided at the instant that the cathode voltage is stopped, by an electrode to which is imparted a negative voltage, so as to prevent particles reaching the substrate.

Abstract: A plasma processing method for processing a target substrate uses a plasma processing apparatus which includes a vacuum evacuable processing vessel for accommodating the target substrate therein, a first electrode disposed in the processing vessel and connected to a first RF power supply for plasma generation and a second electrode disposed to face the first electrode. The method includes exciting a processing gas containing fluorocarbon in the processing vessel to generate a plasma while applying a negative DC voltage having an absolute value ranging from about 100 V to 1500 V or an RF power of a frequency lower than about 4 MHz to the second electrode. The target layer is etched by the plasma, thus forming recesses on the etching target layer based on the pattern of the resist layer.

Abstract: A method for forming a trench includes providing a substrate, and forming the trench in the substrate using a gas containing chlorine (Cl2) gas as a main etch gas and SiFX gas as an additive gas, wherein a sidewall of the trench has a substantially vertical profile by virtue of reaction of the Cl2 gas and the SiFX gas.

Abstract: Methods of selectively etching BPSG over TEOS are disclosed. In one embodiment, a TEOS layer may be used to prevent contamination of other components in a semiconductor device by the boron and phosphorous in a layer of BPSG deposited over the TEOS layer. An etchant of the present invention may be used to etch desired areas in the BPSG layer, wherein the high selectivity for BPSG to TEOS of etchant would result in the TEOS layer acting as an etch stop. A second etchant may be utilized to etch the TEOS layer. The second etchant may be less aggressive and, thus, not damage the components underlying the TEOS layer.

Abstract: The present invention relates in general terms to the treatment or processing of substrate surfaces. In particular, the invention relates to processes for modifying the surface of silicon wafers.

Abstract: An object of the present invention is to provide a fabrication method of a semiconductor integrated circuit device capable of improving the throughput, reducing the cost of a cleaning gas and prolonging the life of a process kit by automatically detecting the end point of cleaning in a chamber. A cleaning gas converted into plasma in a plasma gas generator is introduced into a chamber to remove an unnecessary film deposited over the interior wall of the chamber or electrode. By an RF power source adjusted to low output from the film formation time, a high frequency voltage is applied to a lower electrode and an upper electrode. This voltage is detected by an RF sensor and amplified by an electronic module. The voltage thus amplified by the electronic module is input to a termination controller. The termination controller automatically judges the termination of cleaning when the voltage thus input becomes substantially constant at a predetermined voltage or greater.

Abstract: A method of manufacturing a semiconductor device includes forming a high dielectric insulating layer. An amorphous high dielectric insulating layer having a high density is formed by using a precursor which can be deposited through the atomic layer deposition method at a temperature above 400° C. A resulting insulating exhibits a reduced crystallization during a subsequent annealing process. The capacitance equivalent thickness (CET) characteristic and the leakage current characteristic are improved.

Abstract: In a method of achieving uniform lengths of Carbon NanoTubes (CNTs) and a method of manufacturing a Field Emission Device (FED) using such CNTs, an organic film is coated to cover CNTs formed on a predetermined material layer. The organic film is etched to a predetermined depth to remove projected portions of the CNTs. After that, the organic film is removed.

Abstract: A method of forming a gate insulation film 4 comprising a hafnium silicate material with a SiO2 equivalent oxide thickness of 1.45 nm or less on a silicon substrate 1 is disclosed. The method includes the steps of: cleaning a surface of the silicon substrate 1 to establish thereon a clean surface on which substantially no oxygen is present; forming a hafnium silicate film 2 on the clean surface of the silicon substrate 1 by a CVD process using an amide type organic hafnium compound and a silicon-containing raw material; applying an oxidation treatment to the hafnium silicate film 2, and applying a nitriding treatment to the hafnium silicate film 2 after applying the oxidation treatment. According to the method, a gate insulation film with favorable surface roughness can be obtained even if the film thickness is thin.

Abstract: A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a substrate, providing an etch stop layer on the substrate, providing an oxygen-rich dielectric pre-layer on the etch stop layer and providing a major dielectric layer on the oxygen-rich dielectric pre-layer. Metal interconnects are then formed in the dielectric layers. The oxygen-rich dielectric pre-layer between the etch stop layer and the upper dielectric layer prevents or minimizes peeling and cracking of the layers induced by stresses that are caused by chemical mechanical planarization of metal layers and/or chip packaging.

Abstract: An ashing method of a target substrate is applied after plasma-etching a part of a low-k film by using a patterned resist film as a mask in a vacuum processing chamber. The method includes a process of removing the resist film in the vacuum processing chamber, and a pre-ashing process, performed prior to the main ashing process, for ashing the target substrate for a time period while maintaining the target substrate at a temperature in a range of from about 80 to 150° C.

Abstract: A bulb socket is provided with a rubber socket into which a bulb is mounted and a resin cover which is mounted on the rubber socket by being put over the rubber socket. A projection which protrudes outward is formed on the resin cover. The resin cover is put over the rubber socket, inserted into a housing, rotated to engage the projection with an engaging part in the housing, and thereby mounted on the housing. At this time, the rubber socket comes into close contact with a socket mounting slot and thereby stops the socket mounting slot water-tightly.

Abstract: An electromechanical connection includes a first conductor disposed in a first non-conductive array and a second conductor disposed in a second non-conductive array capable of mating with the first non-conductive array. The second conductor is capable of mating with the first conductor when the first non-conductive array and the second non-conductive array are mated. A processor associated with the first non-conductive array determines if an electrical connection is formed between the first conductor and the second conductor. The processor can assign a function to the electrical connection.

Abstract: There is disclosed apparatus for routing signals between at least one PCB within a test head and a socket card assembly. In an embodiment, the apparatus may include at least one flexible circuit electrically connecting first and second sides of the PCB and the socket card assembly with one another, and the flexible circuit having a defined shape configured to interface with the socket card assembly and the PCB along substantially perpendicular planes. Methods of routing signals between at least one PCB within a test head and a socket card assembly are disclosed. In one embodiment, a method may include electrically connecting first and second sides of the PCB and the socket card assembly with one another with at least one flexible circuit having a defined shape configured to interface with the socket card assembly and the PCB along substantially perpendicular planes. Other embodiments are also disclosed.