Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a first switched capacitor comparator to be charged to a first reference voltage and to compare an input signal to the first reference voltage and to generate a first output signal when the input signal reaches the first reference voltage. A second switched capacitor comparator to be charged to a second reference voltage and to compare the input signal to the second reference voltage and to generate a second output signal when the input signal reaches the second reference voltage. Time between the first output signal and the second output signal is slew rate of the input signal.

Abstract: In general, in one aspect, the disclosure describes an apparatus that included a reference generator to receive a differential input signal and generate reference voltages having same common mode as the differential input signal. A replica bias generator is used to generate a bias signal based on the reference voltages. A comparator is used to compare the input signals to threshold voltages that are based at least in part on the bias signal.

Abstract: The invention includes a novel scan chain structure for LSSD or GSD IC operation. The scan chain structure includes a first flip-flop (L1) and a second flip-flop (L2) configured to operate the first flip-flop (L1) in normal mode operation, in scan mode operation, in initialization mode and in low leakage power mode operation, wherein each flip-flop within a long scan chain of latches includes a data input, data output, a clock input, a scan-in input and a scan-out output, arranged for normal mode operation. A buffer circuit is electrically connected between the scan-out output of the second flip-flop (L2) and the scan-in input of the first flip-flop (L1) for the next latch in the scan chain, the buffer circuit including a control element that controls the operation the first flip-flop (L1) to scan mode or low power leakage mode. The first flip-flop (L1) is set to a data output value upon exit from low power leakage mode that is the same value that it is set to at initialization during normal mode operation.

Abstract: A frequency synthesizer includes a voltage-controlled oscillator to output an oscillation signal of a oscillating frequency in correspondence with a oscillation controlling voltage that is input to the oscillator, a first frequency-divider to subject the oscillation signal to frequency-division and output a first frequency signal, a second frequency-divider to subject the first frequency signal to frequency-division and output a second frequency signal, a controlling voltage generator to generate the oscillation controlling voltage corresponding to a phase difference between a reference clock signal and the second frequency signal, a frequency detector to detect a frequency difference between the second frequency signal and the reference clock signal, and a controller which controls a free-running frequency of the first frequency divider to minimize the frequency difference.

Abstract: A current mode receiver is provided. The current mode receiver includes a first current mirror duplicating an input current to output a first output current, a second current mirror duplicating the first output current to output a second output current, a third current mirror duplicating a reference current to output a third output current, and means for pulling high or low an output voltage based on the second output current and the third output current. The first through third current mirrors are respectively inputted and outputting through gain boost circuits to increase the input and output impedance thereof.

Abstract: An operational amplifier includes a differential amplifier connected between an input and an output port of the operational amplifier, a phase compensator capacitance connected between the differential amplifier and the output port, a switching transistor for controlling the connection between the phase compensator capacitance and the differential amplifier, a detection transistor responsive to a potential difference between the input and output ports to be rendered conductive, and a control transistor responsive to the detection transistor for controlling the switching transistor. The operational amplifier has its slew rate improved without detracting from stability against oscillation and continuity of the output waveform.

Abstract: A clock generator includes a delta sigma modulator, a counter and a first phase lock loop. The delta sigma modulator sequentially generates a plurality of variable parameters according to a predetermined value and a first input clock signal. The counter, which is connected to the delta sigma modulator, is used to generate an output clock signal in accordance with a counting value and a second input clock signal. The counting value is relevant to the variable parameters. The first phase lock loop, which is connected to the output of the counter, is used to generate an objective clock signal in accordance with the output clock signal.

Abstract: A power-on-reset circuit (POR) for integrated circuits that detects the minimum power levels needed to operate the most critical circuit(s) reliably. The circuit is implemented in a customized POR built into a custom IC, and emulates the critical circuit transistors in the custom IC using mimicking counterparts which are similarly affected by changes in temperature and process variations as the main circuit components. The mimicking counterparts may have smaller dimensions, to draw less current but still emulate the characteristics of the main working circuit components. Each critical sub-circuit of the main circuit may have a mimicking POR, and the multiple PORs may have their outputs combined by logic so that subtle failure modes can be modeled in the POR. The POR allows operation of the main circuit to continue at the lowest possible voltage levels while reducing the risk of unexpected results or undetected non-catastrophic failures.

Abstract: A power-up signal generating circuit that prevents repeatedly generating a power-up signal even when there is noise on an external voltage. The power-up signal generating circuit includes a level detector, a level comparator, and a reentry protector. The level detector is configured to deactivate a first level detection signal when a level of an external voltage increases above a upper limit reference voltage. The level comparator is configured to deactivate a second level detection signal when the level of the external voltage increases above a lower limit reference voltage. The reentry protector is configured to activate the power-up signal in response to the second level detection signal and deactivate the power-up signal in response to a deactivation of the first level detection signal.

Abstract: An initialization signal generating circuit includes a voltage distributor, a first initialization signal generator, a second initialization signal, and a controller. The voltage distributor outputs a voltage signal in response to an external voltage. The first initialization signal generator outputs a first initialization signal in response to the voltage signal output from the voltage distributor. The second initialization signal generator outputs a second initialization signal in response to the voltage signal output from the voltage distributor. The controller blocks the external voltage supplied to the voltage distributor and the first and second initialization signal generators, in response to the first and second initialization signals.

Abstract: A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.

Abstract: In general, in one aspect, the disclosure describes an apparatus that includes an inductive capacitive voltage controlled oscillator (LC VCO) to generate an output clock. A voltage to current converter is used to receive a forwarded clock and to inject the forwarded clock to the LC VCO. The output clock is a deskewed version of the forwarded clock.

Abstract: A phase locked loop includes a first clock divider configured to divide a first input clock to generate a second input clock; a clock selector configured to selectively output one of the first input clock and the second input clock in response to a test signal; a phase/frequency detector configured to detect phase and frequency differences between the selected output clock of the clock selector and a feedback clock to generate a detection signal corresponding to the detected phase and frequency differences; a control voltage generator configured to generate a control voltage having a voltage level corresponding to the detection signal; a voltage controlled oscillator configured to generate an internal clock having a frequency corresponding to the control voltage; and a second clock divider configured to divide the internal clock to generate the feedback clock.

Abstract: Circuits and methods for an automatic coarse tuning in a phase locked loop (PLL) include observing a variation in a control voltage to disable a fine loop and to enable a coarse loop as the control voltage departs from a specified range. The circuit includes the fine loop, the coarse loop, and a control circuit. The fine loop includes a phase frequency detector (PFD), a charge pump, a loop filter, a VCO and a divider. The coarse loop includes a frequency detector, an up counter, a down counter, and an LC VCO. The control circuit includes a bandgap module, a comparator and other circuits such as a lock detect circuit. The control circuit is used to switch between the coarse loop and the fine loop.

Abstract: A semiconductor memory device is capable of performing a modulation of output clock signals in order to prevent EMI characteristics of a system having the semiconductor memory device from being degraded. The semiconductor memory device includes a modulation clock signal generator, a clock input unit, a first modulation unit, a delay locked loop circuit, and a second modulation unit. The modulation clock signal generator generates a modulation clock signal. The clock input unit generates a reference clock signal from a system clock signal. The first modulation unit generates a modulated clock signal by modulating the reference clock signal with the modulation clock signal. The delay locked loop circuit performs a delay locking operation on the modulated clock signal to generate a delay locked clock signal. The second modulation unit modulates the delayed locked clock signal with the modulation clock signal.

Abstract: A semiconductor memory device includes a phase comparator, a delay chain, a delay controller, a fine delay chain, a delay model, a locking state detector, and a fine delay controller. The phase comparator compares a phase of a reference clock with that of a feedback clock. The delay chain delays and outputs the reference clock. The delay controller controls a delay value of the delay chain in response to the comparison result of the phase comparator. The fine delay chain outputs a delay value of a clock outputted from the delay chain. The delay model delays a clock to a modeled delay value to provide a delayed clock as the feedback clock. The locking state detector generates a locking variation signal corresponding to a phase difference between the reference clock and the feedback clock. The fine delay controller controls a fine adjustment value of the fine delay chain.

Abstract: An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time-delayed clock signal. The first frequency divider receives an input signal from an internal clock of the PLL and outputs a clock signal having the same frequency or a lower frequency than that of the time-delayed clock signal. The digital logic circuit that receives the first frequency divider output signal and the first time-delayed clock signal and outputs a signal indicating the loss of the input clock signal if there is no first time-delayed clock signal for a cycle of the first frequency divider output signal.

Abstract: A duty cycle bounding circuit for restoring the unbounded duty cycle of a periodic signal such as a forwarded clock signal. The duty cycle bounding circuit comprises a state holding logic element, such as a C-element, and a delay line. The delay line feeds back an inverted version of the output of the state holding logic element to an input of the state holding logic element. The periodic signal is applied to another input of the state holding logic element.

Abstract: In general, in one aspect, the disclosure describes an apparatus comprising a low leakage latch to store a state of a circuit during inactive periods. The state is transferred to the low leakage latch upon receipt of an inactive pulse. A buffer is used to receive the state from an output of the low leakage latch and to isolate the state. State restore circuitry is used to restore the state to the circuit when the circuit returns to an active mode. The state restore circuitry is used to receive the isolated state and to restore the state upon receipt of an active pulse.

Abstract: A terminal state of a terminal 15 of a vehicle is enabled to be maintained for a minimum period of time even after a drop in the voltage supply. At the same time other loads are to have no effect on the holding time. A control device for controls access to a vehicle and has a voltage source, a voltage supply terminal to which a supply voltage can be applied, and a holding circuit to which the voltage source and the voltage supply terminal are connected in a common circuit point for the purpose of holding an On state for as long as the voltage at the voltage source does not fall below a predetermined value. A switching element that is connected into the circuit between the voltage supply terminal and the common circuit point serves to separate the common circuit point from the supply voltage. The holding time is thus decoupled from the VCC currents drawn by other loads.

Abstract: A circuit for data alignment includes a first latch unit and a second latch unit. The first latch unit latches serial input data by using a plurality of first clocks with different phases and the same frequency to output latched data. The second latch unit latches the data from the first latch unit by using a plurality of second clocks with a lower frequency than the first clocks and more diverse phases to thereby output parallel data.

Abstract: A hysteresis circuit including a comparator and capacitive voltage divider circuit. The capacitive voltage divider circuit includes a first capacitor coupled between an input terminal and a positive comparator input, a second capacitor coupled between ground and the positive comparator input, and a third capacitor coupled between the comparator output and positive comparator input. A reference voltage is applied to the negative comparator input. The comparator is powered by the input signal provided on the input terminal. When the voltage on the positive comparator input is less than the reference voltage, the third capacitor is effectively coupled in parallel with the first capacitor. When the voltage on the positive comparator input is greater than the reference voltage, the third capacitor is effectively coupled in parallel with the second capacitor.

Abstract: A level-converted and clock-gated latch includes a pulse generator, a level converting unit, and a latch circuit. The pulse generator is provided with a first power-supply voltage and generates a pulse signal having a first voltage level, in response to a clock signal. The level converting unit is provided with a second power-supply voltage and generates an intermediate clock signal having a second voltage level, in response to an inverted clock signal, the clock signal and an enable signal. The latch circuit is provided with the second power-supply voltage, latches the intermediate clock signal, and provides a gated clock signal having the second voltage level. An activation interval of the gated clock signal is controlled based on the enable signal.

Abstract: A signal generation apparatus includes a signal generation portion and a phase compensator. The phase compensator generates a phase error control signal that maintains a phase difference between the in-phase and quadrature-phase signals generated by the signal generation portion. The phase compensator includes an offset compensator and a delay compensator. The offset compensator is set to compensate for an offset voltage through the phase compensator. The delay compensator is set to compensate for a difference of delays through paths for the in-phase and quadrature-phase signals within the phase compensator.

Abstract: A programmable timing interpolator circuit includes low output impedance buffer circuitry driving a node having a capacitance that varies in response to a programmed delay to be introduced by the interpolator. The low output impedance buffer circuitry receives a subset of course delay signals and, after buffering, provides the buffered course delay signals to fine delay circuitry. The buffer may include two source follower stages coupled to each other. The first source follower stage shifts the level of the received signal down. The second source follower stage shifts the level of the signal from the first source follower stage up. The first and second source follower stages are implemented using NMOS and PMOS technology.

Abstract: An oscillator circuit includes a capacitance element; an inverter outputting an inverted voltage at a first terminal of the capacitance element; a voltage source including a resistor and an NMOS transistor connected in series between a first high-potential power supply and a ground power supply and outputting a voltage from a node to which the resistor and the NMOS transistor are connected; a switch circuit connecting a second terminal of the capacitance element to the voltage source or the ground power supply in accordance with the voltage output from the inverter; and a constant-current source connected to a second high-potential power supply and allowing, regardless of changes in the voltage and temperature of the second high-potential power supply within certain ranges, flow of a constant current into or out of the first terminal of the capacitance element in accordance with the voltage output from the inverter.

Abstract: According to some embodiments, a process, voltage, and temperature compensated clock generator is disclosed. The clock generator may be a charge-charge clock generator including a first load capacitive element and a second load capacitive element. A process, voltage, and temperature compensated current source is coupled to the charge-charge clock generator, and is used to charge the first load capacitive element and the second load capacitive element.

Abstract: Integrate circuit systems and semiconductor devices for generating, transmitting, receiving, and manipulating clock and/or data signals. A semiconductor device including a clock circuit having field effect transistors and a clock driver circuit having bipolar junction transistors is disclosed. The clock circuit may provide a first clock output having a first voltage swing. The clock driver circuit may receive the first clock output and provide a second clock output having a second voltage swing substantially less than the first voltage swing. The field effect transistors can be junction field effect transistors or insulated gate field effect transistors, or the like. The system/devices further including a translator circuit, for translating signals with a lower voltage swing into signals with a higher voltage swing, and a circuit block, for operating at such higher voltage swing.

Abstract: A power electronic module includes: a switch module including a desaturation detection diode and a power semiconductor switch, and wherein the desaturation detection diode is coupled to a switching connection of the power semiconductor switch; and a driver module coupled to the switch module, wherein the driver module is configured for obtaining a voltage signal across the desaturation detection diode and the power semiconductor switch and configured for turning off the power semiconductor switch upon the voltage signal exceeding a threshold. In one example, the driver module is discrete from the switch module. In another example, the switch module and driver modules are configured to respectively provide and receive a voltage signal of less than or equal to seventy volts.

Abstract: A low differential output voltage circuit having a voltage generator and a differential output unit is provided. The voltage generator includes a first PMOS transistor, a first amplifier circuit, a unit gain stage, a first NMOS transistor, a second NMOS transistor. The differential output unit includes a first controlled current source, a second controlled current source, a common voltage circuit, a first switch, a second switch, a third switch, and a fourth switch. Due to the voltage generator directly provides a common mode voltage to the differential output unit, and the first amplifier circuit and the unit gain stage could overcome a channel modulation effect of MOS transistors and enhance the driving ability of the common mode voltage respectively. Thus, a response time of the invention is decreased, and an output current of the differential output unit is in a proportion to the reference current received by the voltage generator.

Abstract: Level shift circuits are disclosed for level shifting an input signal corresponding to a first voltage domain, to generate a pair of complementary output signals corresponding to a second, higher-voltage domain. Snap-back sensitive devices in a discharge circuit for a high voltage output node are protected, irrespective of the loading on the output node, and without requiring precise transistor sizing as a function of the output loading. The snap-back sensitive devices are protected by a voltage shifter circuit in series with the sensitive devices, to limit the voltage across the sensitive devices, even for a high capacitance output node at its highest output voltage. The voltage shifter circuit is then bypassed to provide for an output low level that fully reaches the lower power supply rail.

Abstract: Level shift circuits are disclosed for level shifting an input signal corresponding to a first voltage domain, to generate a pair of complementary output signals corresponding to a second, higher-voltage domain. Snap-back sensitive devices in a discharge circuit for a high voltage output node are protected, irrespective of the loading on the output node, and without requiring precise transistor sizing as a function of the output loading. The snap-back sensitive devices are protected by a voltage shifter circuit in series with the sensitive devices, to limit the voltage across the sensitive devices, even for a high capacitance output node at its highest output voltage. The voltage shifter circuit is then bypassed to provide for an output low level that fully reaches the lower power supply rail.

Abstract: A driving circuit is provided by the present invention. The driving circuit includes a level shifter, a buffer and a switch. The switch is coupled between the level shifter and the buffer. While the level shifter is transiting, the switch is turned off, and the switch is turned on after the level shifter completes the transition. Therefore, the transition time of the level shifter is different from the transition time of the buffer so as to avoid simultaneously conducting large currents to adversely affect the transition capability of the level shifter.

Abstract: The invention relates to a level shifter comprising an input stage having a parasitic capacitance and a first input terminal for applying an input signal, a limiter stage having a second input terminal for applying a switching signal, wherein said input stage is coupled between a first supply terminal and said limiter stage, an output stage being coupled between a second supply terminal and said limiter stage and providing an output signal which is a level shifted version of said input signal, and a current source being adapted for injecting a current pulse into said parasitic capacitance dependent on variations of said switching signal over time.

Abstract: The present invention relates to a switching circuit and a method of controlling a threshold voltage of a semiconductor switching element of the switching circuit, wherein a bulk voltage of the semiconductor switching element (Mi) is selected in response to a control signal derived from an output signal of the semiconductor switching element (Mi). Thereby, a fast switching circuit with hysteresis, smaller cross current and precisely adjustable threshold voltages can be provided.

Abstract: A switching device for bi-directionally equalizing charge between energy accumulators, particularly between capacitive energy accumulators in a motor vehicle electric system, includes: an integrated starter generator; a first connection coupled to the integrated starter generator; a second connection coupled to an energy source; a controllable transfer gate having a first load current-conducting path connected between the first and second connection, and a controllable switching controller having a second load current-conducting path connected between the first and second connection in parallel to the first load current-conducting path. There is also provided a motor vehicle electric system with such a switching device, and the implementation and use of a switching controller in a transfer gate for such a switching device.

Abstract: In some embodiments a power circuit includes a driver output, a MOSFET, and circuitry to ensure a full and fast positive drive to a gate of the MOSFET when the driver output goes to a high signal level, and to ensure a full and fast low negative drive to the gate of the MOSFET when the driver output goes to a low signal level. Other embodiments are described and claimed.

Abstract: A PWM signal generation circuit in an IPM includes an amplification circuit amplifying a voltage across terminals of a temperature sensor, a comparison circuit generating a PWM signal based on a triangular wave signal and an output signal of the amplification circuit, and a correction circuit setting an amplification ratio of the amplification circuit such that a pulse width of the PWM signal is set to a reference pulse width in an adjustment mode in which a switching element is caused to have a reference temperature. Consequently, characteristic variations in the temperature sensor, the amplification circuit, and the like can be corrected, and the temperature of the switching element can be detected with high accuracy.

Abstract: An input transistor unit includes a first transistor having a control electrode to which a reference voltage is supplied. An output transistor unit includes a diode-connected second transistor. At least one of the input transistor unit and the output transistor unit further includes a third transistor that is diode-connected and connected in series with the corresponding first transistor or the second transistor and outputs a current in the same direction as the corresponding transistor does. The number of transistors included in the input transistor unit and the number of transistors included in output transistor unit are different from each other. The size of transistors included in the input transistor unit differs from that of transistors included in the output transistor unit.

Abstract: A coupling system may include an rf-SQUID having a loop of superconducting material interrupted by a compound Josephson junction; and a first magnetic flux inductor configured to selectively provide a mutual inductance coupling the first magnetic flux inductor to the compound Josephson junction, wherein the loop of superconducting material positioned with respect to a first and second qubits to provide respective mutual inductance coupling therebetween. The coupling system may further include a second magnetic flux inductor configured to selectively provide a second magnetic flux inductor mutual inductance coupling the second magnetic flux inductor to the compound Josephson junction. A superconducting processor may include the coupling system and two or more qubits. A method may include providing the first, the second and the third mutual inductances.

Abstract: With an ultrasound pulser suitable for application to a medical ultrasound system, and so forth, a high voltage power supply of a transducer drive circuitry, on both high potential and low potential sides, is rendered variable in a range of 0 V on the order of ±200 V, thereby implementing a semiconductor integrated circuit wherein a plurality of the ultrasound pulsers corresponding to a plurality of channels, respectively, are integrally formed on a small area.

Abstract: A semiconductor device capable of stabilizing power supply by suppressing power consumption as much as possible. The semiconductor device of the invention includes a central processing unit having a plurality of units and a control circuit, and an antenna. The control circuit includes a means for outputting, based on a power supply signal including data on power supply from an antenna (through an antenna) or a load signal obtained by an event signal supplied from each of the units, one or more of a first control signal for stopping power supply to one or more of the units, a second control signal for varying a power supply potential supplied to one or more of the units, and a third control signal for stopping supplying a clock signal to one or more of the units.

Abstract: The disclosure relates to phase shifting in Delay Locked Loops (DLLs) and Phase-Locked Loops (PLLs). A charge pump in the DLL or PLL includes a capacitor connected in parallel to an output node. A primary current switching circuit charges the capacitor with a source current and discharges the capacitor with a sink current. A supplemental source circuit sources a positive phase shift producing current which has a range of magnitudes. A magnitude of the positive phase shift producing current is determined by at least one source selection signal. A supplemental sink circuit for sources a negative phase shift producing current which has a range of magnitudes. A magnitude of the negative phase shift producing current is determined by at least one sink selection signal.

Abstract: An unnecessary through current is suppressed and insufficiency of an output electric potential and increase in power consumption are suppressed in a power supply circuit using a charge pump method. In order to suppress a reduction in an output electric potential VPP as well as suppressing transient through currents I1 and I2 when a clock DCCLK is inverted, resistances R1 of a wiring 11, R2 of a wiring 12 and R4 of a wiring 14 are set so as to satisfy relations R4>R1 and R4>R2. That is, the through currents I1 and I2 can be suppressed by reducing the resistances R1 and R2 so that electric potentials V1 and V2 are quickly inverted when the clock DCCLK is inverted. Also, the through current I1 can be suppressed to suppress the reduction in the positive output electric potential VPP by setting the resistance R4 to be larger than either of the resistances R1 and R2.

Abstract: A supply voltage generating circuit that enables a reduction in chip area includes: a booster for outputting a boosted voltage upon generating the boosted voltage by charge pumping of a capacitor element; a power-supply step-down unit for stepping down voltage of an external power supply to a voltage within a breakdown-voltage range of the capacitor element, and applying the stepped-down voltage to the power supply of the booster; and a switch element for switching between application of the external power supply to the power supply of the booster directly or via the power-supply step-down unit. The booster comprises multiple stages of booster circuits. The thicknesses of gate oxide films of capacitor elements constituted by MOS transistors included in respective ones of the booster circuits are the same and are made smaller than the thickness of a gate oxide film of a MOS transistor included in a load circuit having the output of the booster at its power supply.

Abstract: Systems and methods for reducing driver noise in a MicroElectro-Mechanical Systems (MEMS) gyroscope system are disclosed. An example system includes motor drivers, two proof masses, two substrate electrodes, two motor drive capacitors, and two stationary capacitors. The motor drivers drive the proof masses through the motor driver capacitors. The stationary capacitors output a signal based on the drive signal from the motor drivers. A differential amplifier receives a sense signal from the proof masses and a noise signal from the stationary capacitors, and subtracts the noise signal from the rate sense signal, thereby producing a sense signal with reduced driver noise.

Abstract: A receiving device includes a mixer, an AC coupling circuit, a post-stage circuit, and a DC offset calibration circuit. The mixer is utilized for mixing an input signal with a local oscillating (LO) signal from an oscillator to generate a converted signal. The AC coupling circuit is coupled to the mixer and utilized for reducing at least one portion of DC offset of the converted signal to generate a filtered signal. The post-stage circuit is coupled to the AC coupling circuit and utilized for processing the filtered signal to generate an output signal. The DC offset calibration circuit is coupled to the post-stage circuit and utilized for providing at least a compensation current for the post-stage circuit to reduce DC offset of the output signal.

Abstract: Operational amplifier circuitry drives a device which may be run with a combination of output signals fewer in number than the output signals delivered from plural output circuits. Each output circuit adjusts the gain of an input signal supplied to its operational amplifier. An output selector selects and outputs output signals from the output circuits necessary for driving the device. A decision circuit compares an output signal not selected with a reference signal to adjust the gain of the output circuits to thereby cancel the offset of the operational amplifier. The operational amplifier has sets of feedback elements different in number between the sets formed by capacitances. Switching is made from one set to another until the decision circuit makes an acceptable decision. Offset may thus be canceled during the operational amplification even in case capacitive or resistance element is connected in circuit outside the operational amplifier.

Abstract: A power amplifier with noise shaping is disclosed. The power amplifier with noise shaping is able to minimize the noise interference a regular power amplifier encounters. The power amplifier includes a differential-mode integrator, a driving unit, and a low pass filter and integration unit. The differential-mode integrator receives a differential-mode input signal and a differential-mode feedback signal and performs integration operations to output a differential-mode intermediate signal. The driving unit outputs a differential-mode output signal and drives a load according to the differential-mode intermediate signal. The low pass filter and integration unit performs a filtering operation on the differential-mode output signal and integration operations to output the differential-mode feedback signal to the differential-mode integrator.

Abstract: An exemplary amplifier circuit includes a first group of spatially distributed final amplifier stages having a first configuration, and a second group of spatially distributed final amplifier stages having a second configuration different than the first configuration. Both groups share the same control node for their respective final amplifier stages, and both groups share the same amplifier output node. Each group is typically enabled at a time that the other is disabled. In certain embodiments incorporating a memory array, only one critical analog node must be routed throughout the memory array.