Abstract: A differential signaling system, wherein a first wiring and a second wiring are coupled between a sending end and a receiving end as a differential signal line. A termination resistor is coupled between the first wiring and the second wiring in the receiving end side. A test circuit is coupled to the termination resistor in parallel, and amplifies and detects a variation of a differential impedance due to the differential signal line. The test circuit includes: a differential test amplifier for amplifying a variation in the differential impedance of the first wiring or the second wiring; a switching unit installed at an input terminal of the differential test amplifier for controlling an operation of the differential test amplifier; and a peak detector for converting an output signal of the differential test amplifier into a direct current component; and a phase detector for detecting a skew, a time delay, and/or a phase difference of a signal inputted to the differential signal line.

Abstract: A differential signaling system, wherein a first wiring and a second wiring are coupled between a sending end and a receiving end as a differential signal line. A termination resistor is coupled between the first wiring and the second wiring in the receiving end side. A test circuit is coupled to the termination resistor in parallel, and amplifies and detects a variation of a differential impedance due to the differential signal line. The test circuit includes: a differential test amplifier for amplifying a variation in the differential impedance of the first wiring or the second wiring; a switching unit installed at an input terminal of the differential test amplifier for controlling an operation of the differential test amplifier; and a peak detector for converting an output signal of the differential test amplifier into a direct current component.

Abstract: A capacitive proximity switch has an electrically conductive sensor surface, which is covered by an electrically non-conductive covering plate and which serves as a part of a capacitor having a capacitance that varies with proximity. The sensor surface is connected to a control input of a semiconductor switch that has a signal input with a clock signal and a signal output. A household appliance is equipped with the capacitive proximity switch. The signal output of the semiconductor switch has an output signal, which follows the clock signal and which has signal portions that are proportional to the capacitance of the capacitor formed with the sensor surface.

Abstract: A measuring device is used to measure the state of oils or fats. Said measuring device comprises a housing, a hollow connecting element which is secured therein and a carrier which is applied to the opposite end of the connecting element, said carrier being used to receive a sensor which can be used to measure the electric property of the product which is to be measured, in addition to a sensor which can be used to measure the temperature of the product which is to be measured. The two sensors are in contact with the evaluation system by means of at least one electric line, which is arranged in the region of the housing and/or on the end of the connecting element oriented towards the housing. The temperature sensor is arranged at a pronounced distance from the connecting element and the sensor in order to measure the electric property of the product which is to be measured.

Abstract: A microelectromechanical (MEM) device per the present invention comprises a semiconductor wafer—typically an SOI wafer, a substrate, and a high temperature bond which bonds the wafer to the substrate to form a composite structure. Portions of the composite structure are patterned and etched to define stationary and movable MEM elements, with the movable elements being mechanically coupled to the stationary elements. The high temperature bond is preferably a mechanical bond, with the wafer and substrate having respective bonding pads which are aligned and mechanically connected to form a thermocompression bond to effect the bonding. A metallization layer is typically deposited on the composite structure and patterned to provide electrical interconnections for the device. The metallization layer preferably comprises a conductive refractory material such as platinum to withstand high temperature environments.

Abstract: In one embodiment, a method for determining capacitive signature validity of a powered device (PD) attached to power sourcing equipment (PSE) having (i) an isolated side with a primary coil and (ii) a line side with a secondary coil connected to the PD. The method includes determining, on the isolated side, a first time T1 and a corresponding first voltage V1 across the PD. Then generating, on the isolated side, a switching signal used to generate an electrical current through the primary coil. Then determining, on the isolated side, a second time T2 and a corresponding second voltage V2 across the PD, wherein a difference between V2 and V1 is related to the electrical current provided to the primary coil. Then determining the capacitive-signature validity of the PD based on T1, T2, V1, V2, and a resistive signature of the PD.

Abstract: A percussion instrument data generating system can include a plurality of capacitance sensors coupled to the at least a first surface. A controller section can includes a plurality of switches for selectively connecting each capacitance sensor to a sense node. A capacitance sense circuit can be coupled to the common sense node and can measures a capacitance presented at the common sense node. An encoder section that generates a position value for a sensed input event based that varies according to which capacitance sensor detects the input event.

Abstract: A fluid sensor detects property of fluid by dipping the sensor in the fluid. The sensor includes: a semiconductor substrate; and a comb-teeth electrode made of a first diffusion layer and disposed on a first surface of the substrate. Although the comb-teeth electrode is capable of directly contacting the fluid without a protection film, corrosion resistance of the sensor against the fluid is improved. Further, since the sensor has no protection film, the sensor can detect the property accurately.

Abstract: An object of the present invention is to provide a quality inspection method for obtaining a specifying factor which can more reliably indicate powder characteristics of a core material for an electrophotographic ferrite carrier. To achieve the object, a method for inspecting the quality of a core material for an electrophotographic ferrite carrier adopts a method characterized in that the impedance of the core material for the electrophotographic ferrite carrier is measured by using an AC-resistance measurement method to obtain a Nyquist diagram (Cole-Cole plot) in which a real number impedance (Z?) is arranged in an X-axis and an imaginary number impedance (Z?) is arranged in a Y-axis and then the characteristics of the particles of the core material for the electrophotographic ferrite carrier is evaluated by using the Nyquist diagram (Cole-Cole plot).

Abstract: A parametric test system is for testing devices in dice in a semiconductor wafer, each die having a plurality of pads for electrically connecting to the device in the die. A tester of the system has a plurality of input/output lines for providing and receiving electrical signals during a device test. Multiplexer circuitry of the test system includes a plurality of networks of automated switches. The multiplexer circuitry is configured to receive electrical signals on the input lines from the tester and to provide the electrical signals to a wafer prober, wherein the multiplexer circuitry is configured to restrict how the electrical signals can be provided to the networks of automated switches. As a result of the multiplexer being configured to restrict how the electrical signals can be provided to the networks of automated switches, the configuration of the networks of automated switches can be simplified.

Abstract: Embodiments of the present invention improve probes and probe assemblies. In one embodiment the present invention includes a micro probe comprising a lower contact end including a lower tip, an upper contact end, and a curved intermediate region between the upper contact end and lower contact end.

Abstract: A testline structure made for integrated circuit tests is presented. The structure includes an array of testline pads formed in the scribe line area or integrated circuit die area on a semiconductor substrate, a plurality of test devices formed under the pads area, and a select circuit selectively connecting one of the test devices. The testline structure of this invention enables access to a large number of test devices through the same number of pads as on a conventional testline and can be employed to conduct parametric, reliability, and functional tests on the same. A source measurement unit (SMU) in a conventional integrated circuit tester is employed to sense and force predetermined test conditions on the test device terminals and conduct accurate Kelvin tests on the selected device. A method of using this testline structure is also presented.

Abstract: A split-type probe is used to contact with an object under test to detect an electrical characteristic thereof. The probe provided by the present invention has a contact head used to contact with the object under test, and a first needle body and a second needle body. The first needle body is connected to the contact head to transmit a testing signal to the object under test for performing detection. In addition, the second needle body is also connected to the contact head to transmit a response signal generated by the object under test due to the testing signal to obtain the electrical characteristic of the object under test.

Abstract: A probing method measures electrical characteristics of an object to be inspected by bringing a probe needle to make a contact with an electrode pad of the object, the probe needle formed to be vertically pointing the object. The method includes the steps of: mounting the object on a mounting table; aligning the object and the probe needle; thereafter, contacting the probe needle with the electrode pad by moving the mounting table upwards, and then moving the mounting table vertically upwards while moving same horizontally to rend an oxide film formed on a surface of the electrode pad, so that a tip of the probe needle is stuck into the electrode pad and the probe needle and the electrode pad to conduct with each other.

Abstract: A semiconductor inspection apparatus includes a force probe applying voltage to a semiconductor device, and a sense probe detecting voltage of the semiconductor device, in which the force probe is contacted with an electrode pad of the semiconductor device and the force probe and the sense probe are contacted with each other to measure electric characteristics of the semiconductor device, and the force probe and the sense probe are arranged substantially on the same line when seen from a vertical direction with respect to an electrode surface (principal surface) of the semiconductor device.

Abstract: Disclosed is a fault isolation and measurement system that provides multiple near-field scanning isolation techniques on a common platform. The system incorporates the use of a specialized holder to supply electrical bias to internal circuit structures located within an area of a device or material. The system further uses a multi-probe assembly. Each probe is mounted to a support structure around a common reference point and is a component of a different measurement or fault isolation tool. The assembly moves such that each probe can obtain measurements from the same fixed location on the device or material. The relative positioning of the support structure and/or the holder can be changed in order to obtain measurements from multiple same fixed locations within the area. Additionally, the system uses a processor for providing layered images associated with each signal and for precisely aligning those images with design data in order to characterize, or isolate fault locations within the device or material.

Abstract: A probe card apparatus is configured to have a desired overall amount of compliance. The compliance of the probes of the probe card apparatus is determined, and an additional, predetermined amount of compliance is designed into the probe card apparatus so that the sum of the additional compliance and the compliance of the probes total the overall desired compliance of the probe card apparatus.

Abstract: A testing apparatus includes a circuit board and a first probe. The circuit board has a first testing point and a second testing point. The first testing point is electrically connected to an integrated circuit, and the second testing point is electrically connected to the first testing point. The first probe is used for electrically contacting with the first testing point and transmitting a signal to the integrated circuit through the first testing point. The second testing point is used for detecting if the first probe electrically contacts with the first measuring point. A testing method is also disclosed herein.

Abstract: Methods and apparatus to provide accurate alignment for semiconductor sockets are described. In one embodiment, a carrier is utilized to align a device under test with a test socket. In some embodiments, alignment features on a carrier, a device under test, and/or a test socket are used to align the devices relative to each other.

Abstract: Efficient automated testing systems and methods are presented. In one embodiment, an automated testing system includes a plurality of bucket modules, and a device under test transition interface. The plurality of bucket modules have similar external connection form factors for a variety of instruments. The interface is for transitioning connections from the plurality of bucket modules to a device under test.

Abstract: A test device for semiconductor devices is disclosed. One embodiment provides a probe card, having at least one contact test body for contacting a semiconductor device. The probe card includes self-alignment devices and/or a penetration restriction device, or parts thereof. A semiconductor device is provided having at least one contact field adapted to be contacted by contact test bodies of a test device. The semiconductor device includes self-alignment devices and/or a penetration restriction device, or parts thereof, for the contact test body in the region of the contact field.

Abstract: A probe apparatus for sequentially testing electrical characteristics of chips includes an imaging unit for capturing images of the electrode pads of the inspection substrate, and a unit for calculating contact positions at which the probes are expected to contact with the electrode pads. The probe apparatus further includes a storage unit for storing correction data in which reference points on a reference substrate are associated with correction amounts corresponding to differences between actual and calculated contact positions of the reference points, and a unit for obtaining actual contact positions for the electrode pads by measuring relative positions of the electrode pads with respect to the reference points and correcting the calculated contact positions of the electrode pads based on the relative positions and the correction data.

Abstract: A system and method of mitigating the effects of component deflections in a probe card analyzer system may implement three-dimensional comparative optical metrology techniques to model deflection characteristics. An exemplary system and method combine non-bussed electrical planarity measurements with fast optical planarity measurements to produce “effectively loaded” planarity measurements.

Abstract: A burn-in system enabling the temperatures of a large number of electronic devices differing in amount of self generated heat to be simultaneously reliably adjusted to a predetermined temperature, that is, a burn-in system bringing heater blocks having heaters, cooling blocks formed with channels able to carry a coolant, and sensor blocks having temperature sensors into contact with a plurality of DUTs mounted on a burn-in board and simultaneously performing a burn-in test on the plurality of DUTs, wherein each cooling block is formed with a first accommodating space and second accommodating space, each heater block is accommodated in a first accommodating space in a state maintaining clearance from the inside wall surfaces, and each sensor block is accommodated in a second accommodating space in a state maintaining clearance from the inside wall surfaces.

Abstract: An apparatus is provided which preferably combines temperature sensing and prediction for more accurate temperature control of integrated circuits. An IC temperature sensing and prediction device includes a current sensing device that measures current passing through an IC, and a temperature control apparatus that measures a surface temperature of the IC. The device further includes an electronic controller that calculates the power consumed by the IC according to the measured current and adjusts the temperature of a heater or cooler responsive to the measured surface temperature and power consumption.

Abstract: Embodiments of reinforced resilient elements and methods for fabricating same are provided herein. In one embodiment, a reinforced resilient element includes a resilient element configured to electrically probe an unpackaged semiconductor device to be tested, the resilient element having a first end and an opposing second end; and a reinforcement member having a first end affixed to the resilient element at the first end thereof or at a point disposed between the first and the second ends of the resilient element, an opposing second end disposed in a direction towards the second end of the resilient element, and a resilient portion disposed between the first and second ends, wherein the resilient portion is not affixed to the resilient element.

Abstract: In a method or apparatus such as an integrated circuit (IC) chip including a plurality of circuits for executing a plurality of testmodes, a testmode entry code specifying one of the plurality of testmodes and one of an unrestricted private testmode category and a restricted public testmode category is received. Execution of only a public testmode of the plurality of testmodes is enabled when the testmode entry code specifies the restricted public testmode category. Execution of all of the plurality of testmodes is enabled when the testmode entry code specifies the unrestricted private testmode category.

Abstract: To provide a semiconductor module and a semiconductor device enabling more accurate testing of the connection state of the internal wiring between the semiconductor devices. The semiconductor device has switches SW11 through SW13 that connect a test terminal TT to one end side of wires to be tested, and transistors M21 through M23 that supply a ground potential VSS to the other end side of the wires to be tested. When a power source potential VDD is supplied to one end of the wires to be tested and a ground potential VSS is supplied to the other end of the wires to be tested, a current path can be formed including the wires to be tested. If a power source potential VDD is supplied to the wires to be tested and a ground potential VSS is supplied to the wires which are not to be tested, a difference in potential can be generated between the wires to be tested and the rest of the wires, which makes it possible to detect a short circuit failure.

Abstract: Operation methods of test handler are disclosed. The pick-and-place apparatus picks up semiconductor devices from first loading compartments arrayed in a matrix on a first loading element, moves, and places onto second loading compartments arrayed in a matrix on a second loading element. Pickers of the pick-and-place apparatus pick up the semiconductor devices from the first loading compartments and place them selectively onto a plurality of adjacent odd rows or a plurality of adjacent even rows of the second loading compartments during one operation. The pick-and-place apparatus includes a relatively large number of the pickers, preferably arrayed in a matrix, and thus performs loading and unloading of semiconductor devices at a relatively high speed.

Abstract: A method of electrically inspecting semiconductors display device, which is capable of inspecting whether a signal is normally input to the pixels and whether an electric charge is normally held by the holding capacitors without using the video signal line as a passage for reading the electric charge and without separately providing an inspection-dedicated circuit. Power source lines which are used as passages for supplying the power source voltage are used as passages for reading the electric charge. Namely, the power source lines that can be connected to the signal lines are used as passages for inputting an inspection signal to the holding capacitors in the pixels and for reading the electric charge from the holding capacitors in the pixels.

Abstract: A semiconductor integrated circuit device uses two keeper cells per configuration and/or enable bit as dual redundant storage with error detection thereof. One of the two keeper cells stores a logic level and the other keeper cell stores the inverse of that logic level before the integrated circuit device goes into a low power mode. An exclusive OR (XOR) is performed on the outputs of the two keeper cells (a keeper cell pair) such that if the two keeper cells of the keeper cell pair do not have opposite logic levels stored therein, then the respective XOR outputs an error signal for that keeper cell pair and the error signal is used to force the integrated circuit device out of the low power mode, depending on software control, with or without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered.

Abstract: A push-pull pulse register circuit. The push-pull pulse register circuit includes a first logic inverter having first-inverter input and first-inverter output, a second logic inverter having second-inverter input and second-inverter output, a third logic inverter having third-inverter input and third-inverter output and configured to receive logic input data at the third-inverter input, a first logic gate having first-gate input, first-gate output, and first-gate control input, and a second logic gate having second-gate input, second-gate output, and second-gate control input.

Abstract: A booster circuit for reducing the nominal latency of a logic gate. The booster circuit includes a charge sharing mechanism to transfer a stored charge to the output of the logic gate in response to a logic state transition on the input of the logic gate. The transfer of stored charge also reduces the charge drawn from the supply during the output transition.

Abstract: Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions.

Abstract: Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch.

Abstract: An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

Abstract: Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT output signals. The LUT comprises a plurality of input signals, an array of programmable impedance devices operably coupled to the input signals, and the LUT output signals. Each programmable impedance device in the array includes a first electrode operably coupled to one of the input signal, a second electrode disposed to form a junction wherein the second electrode at least partially overlaps the first electrode, and a programmable material disposed between the first electrode and the second electrode. The programmable material operably couples the first electrode and the second electrode such that each programmable impedance device exhibits a non-volatile programmable impedance. The array may be configured as a one-dimensional or two-dimensional array.

Abstract: A reversible sequential element comprises a first logic gate and a second logic gate. The first logic gate includes a first input terminal, a second input terminal, a third input terminal, a first output terminal coupled to the first input terminal, a second output terminal and a third output terminal. The second logic gate includes a first input line, a second input line, a first output line and a second output line. When the first input terminal is set to a first state, the second input terminal is coupled to the third output terminal and the third input terminal is coupled to the second output terminal; otherwise, the second input terminal is coupled to the second output terminal and the third input terminal is coupled to the third output terminal. The third output terminal, second input line and second output line are coupled to each other. The input signal carried on the first input line is set as 0 so that the second output line and the first output line have the same output.

Abstract: A reversible sequential apparatus comprises a first logic gate and a second logic gate. The first logic gate includes first, second and third input terminals and first, second and third output terminals. The second logic gate includes first and second input lines and first and second output lines. The first input terminal for carrying a clock signal is coupled to the first output terminal and the second input terminal for carrying an input signal is coupled to the second output terminal. When the first input terminal and the second input terminal are simultaneously set to a first state, the level of the third output terminal is inverse to the level of the third input terminal; otherwise, the level of the third output terminal is identical to the level of the third input terminal. The third output terminal, second input line and second output line are coupled to each other.

Abstract: In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes W3 and W4 exceed the voltage of the low-voltage supply VDD, reverse current flow from the nodes W3 and W4 via parasitic diodes within the inverters into the low-voltage supply VDD is prevented. A protection circuit, composed of N-type transistor whose respective gates are fixed to the low-voltage supply VDD, is disposed between the two N-type high-voltage transistors N5, N6 and two N-type low-voltage transistors N1, N2 for receiving the complementary signals IN and XIN, thereby preventing the breakdown of those N-type complementary-signal-receiving transistors.

Abstract: disclosed herein are embodiments of a swing compensation scheme for compensating errors in a transmitter driver.

Abstract: Delay in a clocked logic circuit is reduced by partially determining a next state of the clocked logic circuit based on a current state of the clocked logic circuit during a first portion of a clock cycle. The partially determined next state of the clocked logic circuit is prevented from affecting the current state of the clocked logic circuit during the first portion of the clock cycle. The next state of the clocked logic circuit is completely determined based on a previous state of the clocked logic circuit and the partially determined next state of the clocked logic circuit during a second portion of the clock cycle.

Abstract: A Local Clock Buffer (LCB), an IC chip including registers, some of which may include master/slave latches, locally clocked by the LCB, e.g., providing a launch clock and a capture clock each with an identified critical edge. The LCB includes asymmetrically inductively peaked series connected logic gates (e.g., inverters and/or NAND gates), each with an inductor between gate devices and supply (Vdd) or ground. The series connected gates alternate between having the inductor located between gate devices and the supply and located between gate devices and ground, providing asymmetric inductive peaking to maintain the sharpness of the critical edges. Optionally, corresponding logic gates in multiple LCBs may share the same inductor. Asymmetric inductive peaking allows reducing LCB power without degrading performance.

Abstract: A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.

Abstract: A semiconductor integrated circuit design method includes a step (L) of providing layout information for laying out elements making up a logical circuit on a semiconductor substrate; a step (P) of providing logical circuit information; a step (a) of classifying logical circuits in response to the logical circuit propagation route of a signal based on the logical circuit information and a step (b) of isolating the logical circuits forming the route obtained in the classifying step (a) for each number of stages; a step (c) of classifying the elements making up the logical circuit according to substrate voltage for each number of stages of the logical circuit; and a layout correction step (d) of correcting the layout information so that each element with the larger stage number of the logical circuit is placed at a point closer to a substrate contact.

Abstract: A duty cycle comparator is described for comparing the duty cycles of two digital signals. The duty cycle comparator comprises a first controllable current source, a second controllable current source and a charge accumulation device. The comparator provides an output signal that is representative of the difference between the duty cycles independent of the frequency of the two digital signals.

Abstract: Methods and apparatus for power monitoring with sequencing and supervision are disclosed. An example method disclosed herein comprises supervising a first power rail and a second power rail, sequencing a first enable signal associated with the first power rail and a second enable signal associated with the second power rail, and determining whether the first power rail is enabled based on regulation information determined while supervising the first power rail.

Abstract: The present invention relates to a detector arrangement and a charge pump circuit for a recovery circuit recovering timing information for random data. The detector arrangement comprises first latch means for sampling a quadrature component of a reference signal based on an input signal, to generate a first binary signal, a second latch means for sampling an in-phase component of the reference signal based on the input signal, to generate a second binary signal, and a third latch means for sampling the first binary signal based on the second binary signal, to generate a frequency error signal. Thus, a simple and fast detection circuitry can be achieved based on a digital implementation. Furthermore, the charge pump circuit comprises a differential input circuit and control means for controlling a tail current of the differential input circuit in response to a frequency-locked state of frequency detector arrangement.

Abstract: A semiconductor device includes a control unit for outputting an oscillation enable signal in synchronization with transitions of an input clock and buffering the input clock to output a comparison clock corresponding to an activation timing of the oscillation enable signal. A reference frequency generating unit outputs a reference clock having a predetermined frequency based on the oscillation enable signal. First and second counting units count clocking numbers of the reference clock and the comparison clock respectively until a preset count value. A comparing unit compares the clocking number of the reference clock with that of the comparison clock to generate a comparison signal.

Abstract: An interface circuit includes a reference voltage generation circuit to generate a reference voltage, a differential voltage signal generation circuit to convert send data input in sending data into a pair of differential voltage signals and output the pair of differential voltage signals based on the reference voltage generated by the reference voltage generation circuit, a receiver to convert a pair of differential voltage signals input in receiving data and output received data, and a receiver test circuit to perform a sensitivity test of the receiver, the receiver test circuit having a resistance circuit to generate a pair of differential voltage signals having a potential difference being necessary for the sensitivity test of the receiver.