Abstract: A technique that unfolds the nMOS-tree multiplexer to improve the propagation delay and/or active power consumption is provided. The main idea is to replicate the nMOS element of the downstream buffer, where each replica is driven by a signal that originates from earlier stages of the nMOS-tree multiplexer. This way, when passing high logic values, signals from earlier stages directly drive the downstream buffer improving the delay or the slope of the transition edge (with beneficial effects for power consumption). The passing of low logic values is still performed in the original way by the nMOS tree and the pMOS element of the downstream buffer.

Abstract: An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between logical cells and accessibility to the hierarchical routing network. A second layer of routing network lines provides connectability between different first layers of routing network lines. Additional layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as the prior cell count in the array increases while the length of the routing lines and the number of routing lines also increases. Switching networks are used to provide connectability among same and different layers of routing network lines, each switching network composed primarily of program controlled passgates and, when needed, drivers.

Abstract: An interface circuit and an electronic device are used for expanding an output port of a micro processing unit. The interface circuit includes an input port electrically connected to the output port of the micro processing unit for receiving a control signals, and a plurality of output ports selectively driven to control external circuits by inputting different values of the control signal at the input port.

Abstract: An interface circuit according to one aspect of the present invention may includes a receiving circuit operating on a supply voltage lower than a high-level voltage value of an input binary signal, an input level determination circuit generating an input level determination signal having a frequency higher than a frequency of the binary signal and controls whether to output the input level determination signal or not, based on a voltage level of the binary signal, and an AC coupling element connected between an output terminal of the input level determination circuit and an input terminal of the receiving circuit.

Abstract: A driving circuit comprising an input voltage source set, a reference voltage source, a voltage level shift unit, a logic unit, a safety unit, and an output voltage terminal. The input voltage source set provides an input voltage set. The reference voltage source provides a reference voltage. The voltage level shift unit raises one of levels of the input voltage set to a level of the reference voltage. The logic unit receives the reference voltage and the input voltage set and outputs a control voltage. The safety unit conducts the control voltage to a ground. The output voltage terminal receives the control voltage and outputs an output voltage.

Abstract: A differential amplifier includes a first differential pair, a second differential pair, a load circuit, connected in common to the first and second differential pairs, and first and second current sources for supplying the current to the first and second differential pairs, and amplifies a signal responsive to a common output signal of the first and second differential pairs. One of differential inputs of the first differential pair is connected to a reference voltage. A data output period includes a first period and a second period. During the first period, voltages of first and second input terminals are input through first and fourth switches in the on-state to differential inputs of the second differential pair. The other of the differential inputs of the first differential pair is connected through a third switch in the on-state to an output terminal. An output voltage is stored in a capacitor C connected to the other differential input of the first differential pair.

Abstract: Disclosed is a line driving circuit which includes two NMOS transistors in series between a supply voltage and a ground voltage. The output of the line driving circuit is applied to an interior circuit through a transmission line, and a repeater is used when the transmission line is long.

Abstract: In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.

Abstract: Phase frequency detectors with limited output pulse width and related methods are provided. On exemplary phase frequency detector includes a first edge detector, a second edge detector, and a pulse reshaping controller. The first edge detector is for detecting first-type edges of a first signal to generate a first detection signal. The second edge detector is for detecting the first-type edges of a second signal to generate a second detection signal. The pulse reshaping controller is for receiving the first detection signal and the second detection signal, and for generating a first control signal to the first edge detector and generating a second control signal to the second edge detector. In addition, the pulse reshaping controller further generates a first output signal and a second output signal, wherein a pulse width of the first output signal is limited by the pulse reshaping controller.

Abstract: An electric circuit (30) for generating a clock-sampling signal (CLK) for a sampling device (31) comprises a clock generator (1, 40, 50, 60) for generating a plurality of clock signals (21-24, 51-54, 61-64), a correlation device (L) for correlating a characteristic signal section (LE) of a digital signal (DS) with the plurality of clock signals (21, 22, 23, 24, 51-56, 61-64), and a selecting device (MX) for selecting one of the clock signals (21, 22, 23, 24, 51-55, 61-64) as the clock-sampling signal (CLK) for the sampling device (31) on the basis of the correlation by the correlation device (L). The clock signals (21-24, 51-54, 61-64) have the same cycle duration (T) and are phase-shifted with respect to each other. The sampling device (31) subsequently samples the digital signal (DS) with the clock-sampling signal (CLK).

Abstract: A current mirror circuit includes a pair of first and second transistors having bases connected together and emitters connected to a power line, a resistor connected between the bases of the first and second transistors and the power line, a third transistor for providing base currents of the first and second transistors and a resistor current flowing through the resistor, and a current compensation circuit that adds a compensation current to an input current to the first transistor. The amount of the compensation current is approximately equal to that of the resistor current divided by a current gain of the third transistor. Thus, the compensation current compensates the difference between a collector current of the first transistor and the input current.

Abstract: A semiconductor device includes a differential circuit for receiving a differential signal at an input terminal and a detection circuit for outputting a detection signal when a predetermined signal is inputted to the input terminal. The detection circuit detects whether the differential signal becomes outside an electric input standard and outputs the detection signal.

Abstract: A CMOS driving circuit, wherein an output buffer stage with a transistor switch is added to the final buffer stage of a conventional CMOS driving circuit to drive a power transistor. The output buffer stage has two input terminals for DC input voltage, and uses the high voltage of a voltage converting circuit in a multi-voltage system as one DC input voltage. The driving load capacity of the CMOS driving circuit is improved by converting the higher of the two DC input voltages to a modulated driving voltage and outputting it via an output terminal, so that the on-resistance of a power transistor connected with the output buffer stage is lowered, the power consumption of the power transistor is reduced, the output capacity is improved, and the area of the power transistor is lowered with the same output power.

Abstract: One embodiment of the invention includes a driver circuit. The driver circuit comprises a high-side switch that is activated in response to a positive driver input signal to provide a positive output signal at a driver output. The driver circuit also comprises a low-side switch that is activated in response to a negative driver input signal to provide a negative output signal at the driver output. The positive and negative driver input and output signals can be relative to respective cross-over magnitudes. The driver circuit further comprises at least one impedance-matching device configured to activate the low-side switch in response to a positive signal reflection at the driver output and to activate the high-side switch in response to a negative signal reflection at the driver output.

Abstract: One embodiment of the invention includes a driver circuit. The driver circuit comprises an output transistor that is biased to provide an output signal in response to an input signal. The driver circuit also comprises at least one programmable variable resistor configured to provide a bias magnitude of the output transistor that sets a power of the driver circuit to be commensurate with a data-rate of the input signal.

Abstract: A circuit arrangement with a gate driver circuit for a power transistor is disclosed which is suitable for low voltage applications, permitting a rail-to-rail output without a loss in speed/bandwidth, which is very simple, low cost, low current and area efficient. The gate driver circuit comprises a drain follower with a MOS driver transistor having the gate connected to an interconnection node of a capacitive divider. A first capacitor of the capacitive divider is connected between the drain and the gate and a second capacitor is connected between the gate and an input of the gate driver circuit. The gate driver has the required low impedance for driving the gate of the power transistor.

Abstract: A frequency divider comprising, a first latch circuit (10) and a second latch circuit (10), the second latch circuit (10?) being crossed-coupled to the first latch circuit (10). Each latch (10; 10?) comprises a respective sense amplifier coupled to a respective latch (11). The sense amplifiers comprise a first clock input for receiving a first clock signal (f, f) and 5 respective complementary first clock signal having a first frequency. The latches (11) comprise a second clock input (2f; 2f) for receiving a second clock signal and respective complementary second clock signal having a second frequency, the second frequency being substantially double the first frequency.

Abstract: A system and method for generating a reduced transition time ramp waveform signal are disclosed. Two offset, synchronized ramp waveform signals are generated. Each ramp waveform signal has a repeating sequence including a linear development segment, an upper transition segment, a return segment, and a lower transition segment. The ramp waveform signals are offset synchronized such that the linear development segment of each ramp waveform signal begins before the linear development segment of the other ramp waveform signal ends. Each ramp waveform signal is sampled during its linear development segment to generate a reduced transition time ramp waveform signal.

Abstract: An integrated circuit comprises a system clock and an interface clock. A synchronizing circuit is provided for synchronizing a control signal associated with a predetermined command, for example a PENABLE signal associated with a WRITE command, when the system clock of the integrated circuit is present and bypassing the synchronization circuitry when the system clock is not present. Thus, whenever the system clock of the integrated circuit is active, all the control interface write operations are synchronized to the system clock, and hence there are no timing issues due to different clock domains. If the system clock is not present, the asynchronous writes cannot cause any timing problems, and the synchronization circuit is therefore bypassed.

Abstract: Input circuits connected to an external input terminal PAD via resistor elements are activated in response to the level transition of the clock signals supplied thereto for accepting input signals. In order to input signals applied to the external input terminal PAD clock signals having different phases are supplied to the respective input circuits. The cycle time of each one input circuit can be made longer by sequentially assigning the serial data supplied to the external input terminals in response to the clock signals having different clock signals. Since the input circuits are isolated from each other by means of the resistor elements, the influence of the kick back signal which occurs at first stage of each the input circuit upon the other input circuit can be made very small.

Abstract: A phase detector which provides a dynamic output signal and which automatically resets if a reference clock signal and a feedback clock signal align after an output pulse is generated. With the phase detector in accordance with the present invention, when there is a difference between the positive clock edges of the reference clock signal and the feedback clock signal, the phase detector generates output pulse. The output is used to correct the feedback clock signal. In the next cycle, if the feedback signal is corrected so that both the reference clock signal and feedback clock signal are aligned, then the output signals are reset to zero. The ability to reset advantageously prevents an unexpected correction that can occur in certain phase detector designs.

Abstract: A method for reducing noise in a device that includes at least one phase locked loop (PLL), the method includes: adjusting at least one adjustable component of a PLL such as to determine a time shift; modulating a frequency divider such as to generate a modulation noise within a modulation noise period and to provide a frequency divided signal; introducing the time shift between the modulation noise period and a measurement period; and measuring, during a measurement period a difference between a reference signal and the frequency divided signal. A device that includes a phased locked loop.

Abstract: Disclosed is a PLL circuit in which an output signal of a frequency oscillator (VCO or ICO), an oscillation frequency of which is controlled by an electrical signal, is supplied via a high pass filter (HPF) to one of input terminals of a phase detector, the other input terminal of which receives a reference frequency. An output signal of the phase detector is supplied to a loop filter which then outputs a DC component of the signal that controls the frequency oscillator as the electrical signal.

Abstract: A system and method for generating a pulse stream are disclosed. A ramp signal is generated. The ramp signal is compared with a Time of Transition signal to produce a result indicative of the comparison. Responsive to the result of the comparison, the pulse stream signal is output. The result of the comparison instructs the selector whether to maintain the current output pulse stream signal or replace the current output pulse stream signal with a Polarity signal.

Abstract: In a semiconductor device capable of radio communication, a stable clock signal is generated even if a reference clock signal for generating a clock signal has varied frequencies in each cycle. A clock signal generation circuit includes an edge detection circuit that detects an edge of an input signal and generates a synchronization signal, a reference clock signal generation circuit that generates a clock signal which functions as reference, a counter circuit that counts the number of edges of rise of the reference clock signal in accordance with the synchronization signal, a duty ratio selection circuit that selects a duty ratio of a clock signal from a count value, and a frequency division circuit that generates the clock signal having the selected duty ratio.

Abstract: A circuit has a master latch having an input for receiving an input data signal, and an output. A slave latch has a first input coupled to the output of the master latch, and an output for providing an output data signal. A non-volatile storage element stores a predetermined value. The non-volatile storage element has an output coupled to the first input of the slave latch. The output data signal corresponds to one of either the input data signal or the predetermined value stored by the non-volatile storage element in response to a control signal.

Abstract: The invention relates to a phase shifter which has at least two cascaded delay stages (1, 2), each including a first differential pair of bipolar transistors (Q1, Q1?) and a second differential pair of bipolar transistors (Q2, Q2?). The bases of the first differential pair (Q1, Q1?) serve as input nodes for the delay stage. The emitters of the first differential pair are coupled to a first current source (CS1), and their collectors are coupled to respective loads (D1, D1?; R1, R1?) to provide differential output nodes (OUT1, OUT1?) of the delay stage. The bases of the second differential pair (Q2, Q2?) are coupled to respective output nodes of the first differential pair (Q1, Q1?) of a delay stage, and their emitters are coupled to a variable current source (CS21, CS22, . . . ) for selectively adjusting the current (IA, IB, . . . ) through the second differential pair (Q2, Q2?). The input nodes of each following delay stage (2, . . .

Abstract: In an example embodiments, a single signal-to-differential signal converter includes a first inverter for receiving and inverting a single input signal and outputting an inverted single input signal to a first node, and a first differential signal generating portion for generating a first signal and an inverted first signal which have the opposite phases to each other to second and third nodes in response to the single input signal.

Abstract: The invention relates to an electronic module (10) having organic components. The electronic module has a clock generator (2) having n organic switching elements (21) which are connected in series and are each constructed from organic components. The output of the nth organic switching element of the clock generator (2) is connected to the input of the first organic switching element of the clock generator (2).

Abstract: An integrated circuit including a first circuit block having a power supply terminal for receiving a first power supply voltage and an output terminal for providing a first data signal is provided. The integrated circuit further includes a second circuit block having a power supply voltage terminal for receiving a second power supply voltage and an input terminal coupled to the output terminal of the first circuit block for receiving the first data signal. The integrated circuit further includes a first programmable delay block for adding a first delay time to the first data signal when one or both of the first or second power supply voltages is changed.

Abstract: A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK1) having a first clock frequency to generate a second clock signal (CLK20) having a second clock frequency which is an integer multiple of the first clock frequency. A shift register (SH) receives the second clock signal as a data input signal, and comprises a plurality flip-flops having clock inputs coupled to receive the first clock signal (CLK1), and further coupled so that the data output of a preceding flip-flop is coupled to be the data input of a following flip-flop. The second clock signal is shifted through the shift register (SH) in response to the first clock signal (CLK1) to generate a plurality of shifted clock signals (CLK 21, . . . , CLK32) at respective data outputs of the plurality of flip-flops.

Abstract: A clock frequency diffusing device including a multiphase clock signal generator, a random number generator, signal selectors, and a clock signal generator. The multiphase clock signal generator receives an input clock signal and produces a plurality of delayed clock signals that are delayed relative to the input clock signal by various amounts of time. The clock signal selector randomly chooses one of the delayed signals based upon random numbers generated by the random number generator and produces a selector output signal based on its chosen delayed clock signal. A clock signal generator receives the selector output signal and produces an output clock signal.

Abstract: The invention relates to a receiver for a differential bus with a switch control logic (151), with two branches with resistive elements (7, 61 . . . 70, 8 and 5, 11 . . . 20, 6) and with switches (3, 80) for switching the resistive elements, in which the switch control logic sets the switches—in a first routine for determining the absolute level of signals on the bus by applying a common mode voltage to the bus, by comparing the voltage on a first resistive branch with a reference voltage, by selecting the correct switch settings, and by writing these settings to an internal storage device, —and in a second routine for minimizing the mismatch between the two resistive branches by applying a common mode voltage to the bus, by comparing the voltage of the second resistive branch with that of the already trimmed first resistive branch, by selecting the correct switch settings for the second branch, and by writing these settings to an internal storage device.

Abstract: A voltage level shifter with an input transistor pair, a cross-coupled load chain transistor pair and a pair of current sources, effects reduced power consumption through the use of the cross-coupled load chain transistor pair to minimize the DC current component present in known voltage level shifters. In specific embodiments, feedback elements may be used to minimize delays in signal transitions. A reference voltage that corresponds to a current capability of the input transistor pair may be used to regulate the current sources in the load chain. Changes in a swing of the input signal voltage received by the input transistor pair may be reflected in corresponding changes to the reference voltage. The voltage level shifter may be of particular use in a buffer.

Abstract: A voltage level shift circuit has a plurality of input voltage sources, a reference voltage source, a voltage level shift unit, a stabilizing unit, a first output voltage terminal, and a second output voltage terminal. The input voltage sources provide a plurality of input voltages. The reference voltage source provides a reference voltage. The voltage level shift unit raises the input voltages to a level of the reference voltage. The stabilizing unit prevents power leakage and resulting abnormal voltage levels in the voltage level shift unit. The first output voltage terminal provides a first output voltage. The second output voltage terminal provides a second output voltage inverse to the first output voltage.

Abstract: An output circuit includes a high-side transistor, a low-side transistor, a gate protection circuit, a level shift circuit, and a pre-driver circuit. The level shift circuit interrupts a current path from an output terminal to the level shift circuit after a predetermined time has passed since the high-side transistor was switched OFF.

Abstract: A receiver circuit includes first and second constant current sources respectively connected to a pair of first and second receiving terminals to receive complementary current signals, a first NMOS transistor connected at a source thereof to the first receiving terminal and the first constant current source and connected at a drain thereof to a first power supply via a first output terminal and first load means, and a second NMOS transistor connected at a source thereof to the second receiving terminal and the second constant current source and connected at a drain thereof to the first power supply via a second output terminal and second load means.

Abstract: Methods and corresponding computer systems for characterizing signals and applications thereof are provided that use a functional depending on signal waveforms.

Abstract: A method for controlling a vertical type MOSFET in a bridge circuit is provided to reduce diode power loss and improve a reverse recovery characteristic. The method includes controlling a forward voltage of a built-in diode of the vertical type MOSFET to be a first forward voltage by setting a gate voltage of the vertical MOSFET to a first gate voltage, so that the vertical type MOSFET is switched into a first off mode; and controlling the forward voltage of the built-in diode of the vertical type MOSFET to be a second forward voltage by setting the gate voltage of the vertical MOSFET to a second gate voltage, so that the vertical type MOSFET is switched into a second off mode.

Abstract: A computer apparatus includes a switch, a signal generating part which generates a signal corresponding to a position of the switch, a system part which receives the generated signal and operates, and a controller to control the signal generating part so that the signal generated in the signal generating part can be prevented from being applied to the system part for a predetermined period of time, if the switch moves from a first position to a second position.

Abstract: A high isolation electronic multiple pole multiple throw (MPNT) switching device is formed as a ring circuit that includes plural poles, plural throws, plural series switches and plural means for shunting. Each series switch receives a control signal, and each means for shunting receives shunt control signals. In one aspect, the shunt control signals include control signals received by distant series switches. In another aspect, the shunt control signals include control signals received by adjacent series switches. In another aspect, the shunt control signals include signals complementary to signals received by adjacent series switches. In another aspect, the shunt control signals include pole DC potentials or throw DC potentials. In another aspect, a switching device may operate in multiple transmission mode or multiple input multiple output (MIMO) mode. The MPNT switching device provides low insertion loss and high isolation at a wide range of frequencies.

Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.

Abstract: A control apparatus comprises a voltage source, a controlling unit and an enabling unit. The controlling unit is coupled to the voltage source for receiving an input signal and generating an output signal. The enabling unit is coupled to the voltage source, the controlling unit and a ground terminal for controlling whether the controlling unit generates the output signal or not according to an enabling signal. The enabling unit comprises a first switch, a second resistor, a third resistor and a third transistor. The first switch is used for selectively turning on or off according to the enabling signal. A first terminal of the second resistor is coupled to the first switch. A first terminal of the third resistor is coupled to a second terminal of the second resistor and a second terminal of the third resistor is coupled to the ground terminal. A source of the third transistor is coupled to the ground terminal and a gate of the third transistor is coupled between the second and the third resistor.

Abstract: A gate drive circuit for a wide bandgap semiconductor junction gated transistor includes a gate current limit resistor. The gate current limit resistor is coupled to a gate input of the wide bandgap semiconductor junction gated transistor when in use and limits a gate current provided to the gate input of the junction gated transistor. An AC-coupled charging capacitor is also included in the gate drive circuit. The AC-coupled charging capacitor is coupled to the gate input of the wide bandgap semiconductor junction gated transistor when in use and is positioned parallel to the gate current limit resistor. A diode is coupled to the gate current limit resistor and the AC-coupled charging capacitor on one end and an output of a gate drive chip on the other end When in use, the diode lowers a gate voltage output from the gate drive chip applied to the gate input of the wide bandgap semiconductor junction gated transistor through the gate current limit resistor.

Abstract: The present invention relates to controlling switches in a series connection of electrical devices, in particular to a circuit arrangement, and method of operating same, in which a transistor switch (44, 54) is used to control operation of the devices (12, 14). Because the transistor switches need a gate-source voltage difference, but on the other hand are connected with their source (s) and drain (d) to the main circuit branch, this voltage difference is built up by providing a control current (Ii, I2) over e.g. a resistor (42, 52). This control current (Ii, I2) enters the main current (I), which would influence the operation of the devices, e.g. LEDs (12, 14). In order to correct this, the control current (I2) is corrected for the values of one or more upstream control currents (I2), e.g. through adapting the pulse width in pulse width modulation.

Abstract: Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.

Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the method includes: comprising: (a) measuring the performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of the first set of FETs having a designed first threshold voltage; (b) measuring the performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of the second set of FETs having a designed second threshold voltage, the second threshold voltage different from the first threshold voltage; and (c) applying a bias voltage to wells of the FETs of the second set of FETs based on comparing a measured performance of the first and second monitor circuits to specified performances of the first and second monitor circuits.

Abstract: A power supply device is described comprising a DC voltage supply, a power section connected to the DC supply for supplying DC power from the DC voltage supply to first and second outlet ports for connection to a remote device via a cable connection, a voltage boosting circuit for generating a voltage above that of the DC supply, an energy absorbing circuit connected between an output of the voltage boosting circuit and a ground potential, and a diode connection means between the first outlet port and the energy absorbing circuit. The major components of the power supply device may be implemented as an integrated circuit.

Abstract: A signal processing circuit comprising one or more ion sensitive field effect transistors, ISFETs, and a biasing circuit for biasing the or each ion sensitive field effect transistor to operate in the weak inversion region.

Abstract: A high-speed receiver suitable for applications that desire a common-mode voltage range from approximately 0.7V to approximately 0.9V is arranged by coupling first and second differential pair circuit architectures based on first and second current-steering schemes into the same path to generate an output signal. The high-speed receiver includes first and second differential pair circuits. The first differential pair circuit is coupled to a first current-steering path via a first port and a second current-steering path via a second port. The second differential pair circuit is coupled to the first current-steering path via a third port and the second current-steering path via a fourth port. A bridge circuit is interposed between the first and second differential pair circuits. The bridge circuit integrates the first and second current-steering paths in a single-stage of the high-speed receiver assembly.