Abstract: A semiconductor package includes a substrate or leadframe structure. A plurality of interconnected dies, each incorporating a plurality of through-hole vias (THVs) disposed along peripheral surfaces of the plurality of dies, are disposed over the substrate or leadframe structure. The plurality of THVs are coupled to a plurality of bond pads through a plurality of a metal traces. A top surface of a first THV is coupled to a bottom surface of a second THV. An encapsulant is formed over a portion of the substrate or leadframe structure and the plurality of dies.

Abstract: An electro-optical device includes an electro-optical panel having a substrate; a plurality of input terminals that are arranged in a first direction on the substrate; and a semiconductor device provided with a plurality of input bumps electrically connected to the input terminals through conductive organic members. The input terminals connected to the input bumps that are positioned substantially at the center of the semiconductor device in the first direction have allowable connection resistance values smaller than those of the other input terminals.

Abstract: A thin semiconductor device difficult to cause breakage of a semiconductor chip is disclosed.

Abstract: The present invention provides an optical device (2) including: a substrate (1) having a resin base (11) provided with an opening, a plurality of conductors (13) embedded in the resin base (11) such that at least parts of the plurality of conductors (13) are exposed on a lower face of the resin base (11) as electrode terminals, and a transparent member (12) fitted into the opening of the resin base (11); and an optical element (31) having an optical region (32) on an upper face thereof and which is mounted to a lower face of the substrate (11) so that the optical region (32) opposes the opening of the resin base (11), wherein the substrate (11) has a rectangular tabular shape whose thickness is substantially even.

Abstract: An apparatus for implementing integrated circuit cooling during testing and image-based analysis thereof includes a lid configured to define a cavity surrounding an integrated circuit die, the die mounted to a module substrate. One or more fluid passages are defined within the lid, wherein the passages facilitate the flow of a cooling liquid through said cavity and over the integrated circuit die, and a transparent window is formed within the lid so as to facilitate viewing of the integrated circuit die.

Abstract: A die package (72) for a semiconductor die (20). A plurality of the die packages (72) are formed on a single carrier (10) by applying a body (55) of molding compound across a carrier (10) with an air cavity (70) defined in the molding compound about each of a plurality of device regions (12) of the carrier (10). After a semiconductor die (20) is attached inside the air cavity (70) of each device region (12) and electrically connected with at least one contact pad (14, 16, 18), a cover (68) is applied to close all of the air cavities (70). Following singulation, each semiconductor die (20) is located inside the sealed air cavity (70) of one die package (72). The molding compound of each die package (72) may be locked against movement relative to the device region (12) of the carrier (10) by locking features (30, 38, 48, 50).

Abstract: A semiconductor device is manufactured by, first, providing a wafer designated with a saw street guide. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A plurality of via holes is formed in the organic material. Each of the plurality of via holes is patterned to each of a plurality of bond pad locations on the plurality of dies. A conductive material is deposited in each of the plurality of via holes.

Abstract: A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure. An encapsulant is formed over a portion of the first die and the first semiconductor package.

Abstract: Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through respective transistors. The transistors connected to the first bonding pads of an upper die are made conductive while the transistors connected to the second bonding pads of the upper die are made non-conductive. The transistors connected to the second bonding pads of a lower die are made conductive while the transistors connected to the first bonding pads of the lower die are made non-conductive. The second bonding pads of the upper die are connected to the second bonding pads of the lower die through wafer interconnects extending through the upper die. Signals are routed to and from the circuits on the first and second dies through the first and second bonding pads, respectively.

Abstract: An integrated circuit package system is provided including connecting an integrated circuit die with an external interconnect, forming a first encapsulation having a device cavity with the integrated circuit die therein, mounting a device in the device cavity over the integrated circuit die, and forming a cover over the device and the first encapsulation.

Abstract: An LGA (Land Grid Array) semiconductor package mainly comprises a substrate, a chip, a soldering layer and a foot stand. The chip is disposed on a top surface of the substrate and is electrically connected to a plurality of metal pads formed on a bottom surface of the substrate. The soldering layer is disposed on the metal pads with a first thickness slightly protruded from the bottom surface of the substrate. Additionally, the foot stand is disposed under the substrate with a second thickness protruded from the bottom surface of the substrate, wherein the second thickness is greater than the first thickness. Therefore, the soldering layer of the LGA semiconductor package is free from scratches and damages during shipping and handling processes. Moreover, the LGA semiconductor package can be surface-mounted to a printed circuit board with pre-applied solder or pre-mounted solder balls to increase the implementations of LGA semiconductor packages.

Abstract: An electrically conductive pin comprising a pin stem and a pin head attached to the pin stem. The pin head is adapted to be mounted onto a surface of a microelectronic substrate to support the pin stem. The pin head defines at least one slot therein, the at least one slot being configured to allow gases to escape therethrough from a region at an underside of the pin head.

Abstract: An IC package that employs top-side conduction cooling. The IC package has a low thermal resistance between a substrate housed within the package and the lid of the package. Thermal resistance is decreased by increasing the conduction cross-sections laterally through the package and lid and vertically from the package into the lid. The lid may also be modified with an extended mesa portion that reduces the gap between the lid and the IC. A thermally conductive spacer may also be interposed between the IC and the lid. Also, the package housing body and lid may be made from high thermal conductivity materials having thermal conductivities of 50 W/mK or greater with matching CTE between the lid and the package.

Abstract: An assembly includes a semiconductor die disposed between an upper substrate and a lower substrate. A circuit board that defines a through hole is spaced axially below the upper substrate to define a gap between the upper substrate and the circuit board. An upper heat sink is thermally connected to the upper substrate by an upper thermal interface material to transfer heat in a first dissipation path to the upper heat sink. A lower heat sink is thermally connected to the lower substrate by a lower thermal interface material to transfer heat in a second dissipation path to the lower heat sink. A plurality of first interconnectors are disposed in the gap to solder the upper substrate to the circuit board. The assembly is distinguished by a plurality of second interconnectors that are disposed between the upper substrate and the lower substrate to position the lower substrate in the through hole of the circuit board.

Abstract: A stacked array of channeled semiconductor chips defining a power electronic circuit is mounted in a sealed container provided with inlet and outlet passages for liquid coolant. Leadframe terminals supported by the container engage selected terminals of the semiconductor chips and form leads for mounting the container on a circuit board having electrical and fluid interconnects.

Abstract: A plurality of direct die cooled semiconductor power device packages are vertically stacked with both coolant and electrical interfacing to form a liquid cooled power electronic circuit. The packages are individually identical, and selectively oriented prior to stacking in order to form the desired circuit connections and laterally stagger the package leads.

Abstract: A chip package structure includes a carrier, an interposer, a plurality of electrically conductive elements, a first sealant, a chip, and a second sealant. The interposer is disposed on the carrier. The electrically conductive elements electrically connect the interposer and the carrier. The first sealant seals the electrically conductive elements. A plurality of bumps of the chip is connected to the interposer. The second sealant seals the bumps. A first glass transition temperature of the first sealant is higher than a second glass transition temperature of the second sealant. Since glass transition temperatures of the first sealant and the second sealant are different, and the first glass transition temperature of the first sealant is higher than the second glass transition temperature of the second sealant, the inner stress will be lowered and the yield is promoted.

Abstract: A wire bond system including providing an integrated circuit die with a bond pad thereon, forming a soft bump on the bond pad, and wire bonding a hard-metal wire on the soft bump.

Abstract: A semiconductor device according to the present invention includes a semiconductor chip having a functional surface formed with a functional element, an electrode pad provided directly on the functional element on the functional surface of the semiconductor chip, a protective resin layer laminated on the functional surface of the semiconductor chip, an external connection terminal provided on the protective resin layer in opposed relation to the electrode pad, and a post extending through the protective resin layer in a direction in which the electrode pad and the external connection terminal are opposed to each other for connection between the electrode pad and the external connection terminal.

Abstract: A semiconductor chip substrate with solder pad includes: a core layer and at least one conductive structure formed on the surface of the core layer; an insulation layer with at least one patterned opening covering the conductive structure, wherein the patterned opening has a center portion and a plurality of wing portions on the peripheral edge of the center portion to define the exposed area of the conductive structure as the solder pad. The solder pad with wing will improve the adhesion effect between the solder pad and the solder ball.

Abstract: A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a first plug filled in a portion of the contact hole, a diffusion barrier layer formed above the first plug and in a bottom portion and on sidewalls of a remaining portion of the contact hole, a second plug formed on the diffusion barrier layer and filled in the contact hole, and a storage node coupled to and formed on the second plug.

Abstract: A technology that improves the reliability of a semiconductor device and realizes a high performance by a laminated structure that has enough barrier properties against copper, reduces the wire delay time by lowering the capacitance between wirings and improves the adhesion between wirings is provided. There is a semiconductor device having: a first copper wiring layer, a first barrier layer on the first copper wiring layer, a silicon oxide series porous insulating layer on the first barrier layer, a second barrier layer on the silicon oxide series porous insulating layer, and a second copper wiring layer on the second barrier layer, wherein at least one of the first barrier layer and the second barrier layer consists of an amorphous carbon film, wherein a silicon oxide series insulating layer is directly connected between the amorphous carbon film and any of the first copper wiring layer or the second copper wiring layer.

Abstract: An electronic device can include conductive regions. A void can extend between different portions of an insulating layer. Different openings can intersect the void. A liner layer can substantially block the void, substantially preventing subsequently forming an electrical leakage path along the void. In one aspect, a stressor layer can be deposited over the conductive regions prior to forming the insulating layer. The liner layer can be formed over the stressor layer within the different openings through the insulating layer. In another aspect, an etch-stop layer can be formed over a silicide layer prior to forming the insulating layer. After removing a portion of the liner layer, a portion of the etch-stop layer can be removed to expose the silicide layer within the different openings. In yet another aspect, a nitride layer can lie between a substrate and the insulating layer and include a section of the openings.

Abstract: A semiconductor device is disclosed. The device includes a substrate, a first porous SiCOH dielectric layer, a second porous SiCOH dielectric layer, and an oxide layer. The first porous SiCOH dielectric layer overlies the substrate. The second porous SiCOH dielectric layer overlies the first porous SiCOH dielectric layer. The oxide layer overlies the second porous SiCOH dielectric layer. The atomic percentage of carbon in the second porous SiCOH dielectric layer is between 16% and 22% of that in the first porous SiCOH dielectric layer.

Abstract: A semiconductor device is provided, including: a first barrier metal film provided by a PVD process in a recess formed in at least one insulating film, and containing at least one metal element belonging to any of the groups 4-A, 5-A, and 6-A; a second barrier metal film continuously provided by at least one of CVD and ALD processes on the first barrier metal film without being opened to atmosphere, and containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A; a third barrier metal film continuously provided by the PVD process on the second barrier metal film without being opened to the atmosphere, and containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A; and a first Cu film continuously provided on the third barrier metal film without being opened to the atmosphere and thereafter heated.

Abstract: Provided is a semiconductor device including high-frequency interconnect and dummy conductor patterns (second dummy conductor patterns). The dummy conductor patterns are disposed in a interconnect layer different from a interconnect layer in which the high-frequency interconnect is disposed. The dummy conductor patterns are disposed so as to keep away from a region overlapping the high-frequency interconnect in plan view. The semiconductor device further includes dummy conductor patterns (first dummy conductor patterns) in the interconnect layer in which the high-frequency interconnect is disposed.

Abstract: Described herein is an electronic device in which one or more planar interconnect structure are interposed between two substrates each incorporating a hybrid circuit. The planar interconnect structure has a plurality of conductive traces formed on one of its faces for electrically connecting sets of interconnection points of each of the hybrid circuits.

Abstract: Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods are also disclosed.

Abstract: A method for fabricating a semiconductor device. A preferred embodiment comprises forming a via in a semiconductor substrate, filling the via with a disposable material such as amorphous carbon, forming a dielectric layer on the substrate covering the via, performing a back side etch to expose the disposable material in the via. A back side dielectric layer is then depositing, covering the exposed via. A small opening is then formed, and the disposable material is removed, for example by an isotropic etch process. The via may now be filled with a metal and used as a conductor or a dielectric material. The via may also be left unfilled to be used as an air gap.

Abstract: A through-wafer via interconnect region is in a circuit portion of a wafer, the circuit portion including at least one electrically conducting metal layer and configured for use, after dicing of the wafer, as one of a plurality of layers stacked vertically to form a three dimensional integrated circuit. Within the metal layer in the circuit portion, the metal is removably distributed such that the ratio of metal to nonmetal area, within the via region, varies by less than a predetermined amount from the ratio of metal to nonmetal area outside the via region.

Abstract: A semiconductor device according to the present invention has a semiconductor chip provided with an insulating layer formed so as to be thinner in a first secondary-wire-free area than in a first secondary-wire-containing area. Further, the semiconductor chip has an edge extending further outward than a side wall, which severs as an edge of an upper insulating layer, in an extending direction of a circuit-forming surface of the semiconductor chip on which electrode pads are provided. This makes it possible to provide a semiconductor device capable of suppressing electromagnetic interference between a secondary wire and an electronic circuit of a semiconductor chip and the curvature of a wafer even in the case of overlap between the secondary wire and the electronic circuit, and of reducing the risk of occurrence of chipping in a dicing step.

Abstract: A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package.

Abstract: A method for manufacturing a semiconductor module includes: a first process of forming a conductor on one face of an insulating layer; a second process of exposing the conductor from the other face of the insulating layer; a third process of providing a first wiring layer on an exposed area of the conductor and on the other face of the insulating layer; a fourth process of preparing a substrate on which a circuit element is formed, the second wiring being formed on the substrate; and a fifth process of embedding the conductor in the insulating layer by press-bonding the insulating layer and the substrate in a state where the conductor on which the first wiring layer is provided by the third process is disposed counter to the second wiring layer. Wiring is formed without causing damaging to the circuit element.

Abstract: A transfer mold process for encapsulation of a matrix array package of dice on a substrate is proposed wherein the flow of the mold compound between dice is at least partly obstructed. In other words, the flow velocity of the mold compound between dice is constrained with the goal of approximating it to the flow velocity above the dice. It is to be understood that every limitation of the flow velocity between the dice, even if it does not result in equal or uniform velocity throughout the cross-sectional area, will bring about a positive effect in terms of reducing the clustering of filler particles in certain areas of the mold compound. The semiconductor device thus produced is part of the present disclosure.

Abstract: A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.

Abstract: A carburetor includes a base, a Venturi cone assembly, a cam assembly, a horsepower adjustment assembly, and a vacuum horsepower adjustment valve. The Venturi cone assembly is mounted in the base. A supporting portion of a cone collides with a cam of the cam assembly. An oil line rotation wheel of the horsepower adjustment assembly is drawn by an oiling line to drive the fan blade. The amount of displacement of the cone of the Venturi cone assembly under vacuum suction from the engine is controlled by a cam of the cam assembly. The vacuum horsepower adjustment valve automatically supplies enough fuel to the engine. Accordingly, the present invention can make the fuel burn sufficiently, effectively improving efficiency and reducing air pollution.

Abstract: A submerged gas processor in the form of an evaporator or a submerged gas reactor includes a vessel, a gas delivery tube partially disposed within the vessel to deliver a gas into the vessel and a process fluid inlet that provides a process fluid to the vessel at a rate sufficient to maintain a controlled constant level of fluid within the vessel. A weir is disposed within the vessel adjacent the gas delivery tube to form a first fluid circulation path between a first weir end and a wall of the vessel and a second fluid circulation path between a second weir end and an upper end of the vessel. During operation, gas introduced through the tube mixes with the process fluid and the combined gas and fluid flow at a high rate with a high degree of turbulence along the first and second circulation paths defined around the weir, thereby promoting vigorous mixing and intimate contact between the gas and the process fluid.

Abstract: In accordance with the present invention, active carboxylic acid ester groups are coupled on the surfaces of microspheres so as to reduce protocols for microsphere processing, control side reactions, and stably preserve beads containing active carboxylic acid ester groups. Further, microspheres labeled with at least one fluorescent dye cage in the microspheres, and the microspheres are preserved in lower alcohol.

Abstract: The invention relates to a method and a device for producing spherical particles from a melted mass of plastic. According to the invention, said melted mass is transformed into droplets by means of a droplet-forming nozzle (10); after falling a certain distance, the droplets are crystallised at least on the surface thereof; the droplets are then supplied to a crystallisation stage in which they are fully crystallised; and are then supplied to an postcondensation stage wherein solid phase polycondensation takes place. In order to ensure surface crystallisation without the risk of adhesion both among the drops and to parts of the device, the drops fall in a crystallisation stage (45) having a cloth element or a sheet metal element comprising openings or a fluidised bed chamber through which gas flows in order to swirl the drops.

Abstract: An insert molding machine for manufacturing electronic parts, is equipped with an automatic hoop feeder system for intermittently feeding the metal components of a molded product by way of a hoop formed of a thin carrier strip on which a plurality of metal components are carried at regular intervals in a row. A pair of hoop conveying means are installed adjacently to one of the opposed inlet and outlet sides of the mold of an injection molding machine, and a pair of carriages supported by the respective hoop conveying means are interconnected mechanically to each other through a coupling connector so that the both carriages are moved forward and backward in complete synchronism with each other when one of the carriages is driven to slide.

Abstract: A traditional steam chest molding apparatus for the manufacture of products from expanded plastic materials requires excessive amounts of steam to properly expand and fuse pellets of plastic together A molding apparatus is provided wherein a pair of complementary molds (100, 300) are provided with a steam manifold (110) to introduce steam into the mold cavity by way of steam lines (160, 162, 164, 166) The steam manifold (110) allows for direct injection of steam into the manifold and hence a reduction in the total steam required for a molding operation The amount of steam necessary for the production of a particular article is predetermined in dependence upon a geometry and a size of the article to be produced Thus if desired, the amount of steam provided to the mold cavity is measured prior to injection

Abstract: Load-bearing articles are manufactured from shape defining compressible cores and thermoplastic shells. The manufacture of these articles requires specific methods and tools. Articles that can be manufactured using these methods include relatively lightweight pallets with high load-bearing capacity.

Abstract: Method and apparatus for making fastener products (117) having molded projections (110) or other molded features carried on a surface (130) feature a transfer device (135) having an outer surface with at least one transfer area (H) relatively raised with respect to another area (L) of the outer surface of the device.

Abstract: The invention relates to a method for coextrusion of at least two molten material flows having different composition by separating the molten material into at least two molten material flows, admixing additives in at least one of the molten material flows and bringing together the molten material flows by coextrusion in one or more extrusion tools. The method is particularly suitable for the production of PVB films with a color strip for composite glazings.

Abstract: A closure cap and method of making the same wherein an annular or ring-shaped gasket is injection molded onto the inner surface of a cap shell formed of plastic or metal. The annular or ring-shaped gasket includes radially extending tabs integrally formed therewith, one of said tabs being formed at a location wherein the plastic melt is fed to an annular gasket-forming channel in a mold core and another of said tabs being formed at the location wherein plastic melt is discharged from said channel. Preferably, said other tab includes a cold well formation which communicates with the annular gasket through a connecting portion of reduced cross-sectional area with respect to the cross-sectional areas of both the gasket and the cold well formation.

Abstract: A method for forming a closure device for a container is disclosed including providing a first mold component having a first annular groove. The first annular groove is configured to form a skirt of the closure device. A plurality of ejector blades are provided and are positioned within the mold component. The blades include a notch for forming a lug on an inner surface of the skirt. The lug is back-locked relative to the mold component. A moldable material is introduced into a mold cavity to form the closure device. The device is removed from the mold component by moving the blades along a path defined by tracks formed in the mold component that is generally along a vertical axis of the mold component, wherein the path includes a radially outward component, and the moving of the blades relieves the back-lock of the lug formed on the closure device.

Abstract: A stepwise contraction and adsorption nanolithography (SCAN) patterning process can shrink complex microstructures (produced by current microfabrication technology) into the nanometer region. The basis of SCAN is to transfer a pre-engineered microstructure onto a extended elastomer. This extended elastomer is then allowed to relax, reducing the microstructure accordingly. The new miniaturized structure is then used as a stamp to transfer the structure onto another stretched elastomer. Through iterations of this procedure, patterns of materials with pre-designed geometry are miniaturized to the desired dimensions, including sub-100 ran. The simplicity and high throughput capability of SCAN make the platform a competitive alternative to other micro- and nanolithography techniques for potential applications in multiplexed sensors, non-binary optical displays, biochips, nanoelectronics devices, and microfluidic devices.

Abstract: A method of making a compressible elastomeric pad from a preselected polymer material includes the steps of providing a preform including a substantially solid body having a predetermined cross-section disposed normal to a central axis of the preform and a pair of axial ends, each having a substantially flat surface disposed normal to the central axis and a central socket formed within at least one substantially flat surface. Next, providing a pair of forming plates, at least one of the pair of forming plates having a raised annular ring and an axially aligned cavity provided on one surface thereof. Then, positioning the preform between the pair of forming plates and axially aligning the exterior peripheral edge of the annular ring with a peripheral edge of a respective central socket. Finally, forming the pad and removing the pad from engagement with the pair of forming plates.

Abstract: The invention is a method to make compression molded motor vehicle parts from a charge of composite material with resin and fibers, such as sheet molded compound. The parts have voids, such as holes and gaps, that form in the compression mold under heat and pressure and not in secondary processing steps. The resin in the charge is melts in a reservoir in the mold to form resinous material from the charge. A flow front of resinous material is allowed to flow into a flow path around a restriction corresponding to the shape of the void from the reservoir. The flow front carries sufficient reinforcing fibers into the flow path. At least part of a border for the void forms in the flow path. The configuration is allowed to at least partially set.

Abstract: The invention relates to a method for producing a microcircuit card, comprising the following steps: a step for positioning a microcircuit in an open-cavity mould, and a step for depositing a material in the open cavity of the mould, the material being sufficiently poorly viscous for coating at least indirectly at least part of the microcircuit.