Abstract: One embodiment relates to a method for detecting defects in circuitry formed on a semiconductor substrate. A first scan of said circuitry is performed by scanning a primary electron beam in a first scan direction relative to said circuitry, and secondary electrons emitted during the first scan are detected so as to form a first voltage-contrast image. A second scan of said circuitry is performed by scanning the primary electron beam in a second scan direction relative to said circuitry, and secondary electrons emitted during the second scan are detected so as to form a second voltage-contrast image. The second scan direction is non-parallel to the first scan direction. The first and second voltage-contrast images are then compared to detect electrically-active defects. Other embodiments, aspects and features are also disclosed.

Abstract: The board of a probe card of the present invention comprises a first substrate having a first inclined surface at the side surfaces and a second substrate having a second inclined surface. The first substrate and the second substrate are disposed such that the first inclined surface and the second inclined surface are opposed to each other. Between the first inclined surface and the second inclined surface, a stress absorber having electroconductivity is sandwiched.

Abstract: A direct current and a modulation signal are simultaneously applied to contact pads on a device under test, such as a laser diode, with a probe that reduces signal distortion and power dissipation by transmitting a modulated signal through an impedance matching resistor and transmitting of a direct current over a second signal path that avoids the impedance matching resistor.

Abstract: Assemblies include a substrate, such as a printed circuit board, with a first array of contact pads disposed thereon; a guide ring structure disposed on the substrate and at least partially surrounding the first array of contact pads; a translator socket disposed on the first array of contact pads, the translator socket adapted to receive the tester side of a translated wafer; a thermally conductive, conformal, heat spreading cushion adapted to be disposed over the backside of a wafer; a cover plate adapted to fit over the first array of contact pads, align with the guide ring structure, contain within it the various components disposed over the first array of contact pads, and removably attach to the substrate; and a bolster plate adapted to removably attach to a second side of the substrate.

Abstract: A method of using a blade probe for probing a node of a circuit where the node includes a pad surface surrounding a node hole is disclosed. A probe having a longitudinal probe axis, a shaft, and a probe blade is provided. The shaft is generally concentric to the longitudinal probe axis and is made from an electrically conductive material. A probe blade is disposed at a first end of the shaft. The probe blade includes first and second faces positioned about the longitudinal probe axis in facing opposition to each other. The first and second faces converge towards each other and terminate at an edge. The probe is urged in a direction generally parallel to the longitudinal probe axis to create at least one electrical contact point between the edge of the probe blade and one of the solder disposed a pad surface of a node or the solder disposed on a rim of a hole of the node.

Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.

Abstract: A method for testing a batch of semiconductor devices in wafer level is provided. The method includes the following steps: (a) obtaining a breakdown voltage of gate dielectric of each semiconductor device; (b) applying, to the gate dielectric of each semiconductor device, a stress voltage below the breakdown voltage but above a base voltage of gate dielectric of the semiconductor devices; (c) after the step (b), measuring currents of gate dielectric of each semiconductor devices at the base voltage; and (d) obtaining a tailing distribution from the measured currents.

Abstract: An anti-counterfeiting circuit that is incorporated into an authentic integrated circuit (IC) design, which induces a random failure in a counterfeited IC when the counterfeit IC is manufactured from a reverse-engineered authentic IC. The anti-counterfeiting circuit uses two signals of differing frequencies, which activate a disrupt signal when the two signals meet a predetermined failure criteria, for example, equivalent rising edges. The disrupt signal causes a signal gate or similar element within the counterfeited IC to fail, disrupt, or in some way change a designed behavior of the IC. The disrupt signal may be reset so that the failure will occur again when predetermined failure criteria are met. The authentic IC functions according to design because at least one of the elements in the anti-counterfeit circuit is a camouflage circuit, thus, in an authentic IC the anti-counterfeit circuit is not operatively coupled.

Abstract: An integrated circuit includes at least one input and output circuit including: a signal terminal that provides an external contact; a protective circuit coupled to the signal terminal; an input driver and/or an output driver coupled to the signal terminal via the protective circuit; and an additional circuit including a first input coupled to the signal terminal via the protective circuit, and an output that provides a test value for operation of the input and output circuit.

Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.

Abstract: A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments.

Abstract: A dynamically configurable logic gate includes an input summer for receiving a first input signal and a second input signal to generate a summed input signal. Further the dynamically configurable logic gate includes a nonlinear element that applies a nonlinear function to the summed input signal to produce a nonlinear output signal. The dynamically configurable logic gate output signal corresponds to one of a plurality of different logic gates responsive to adjusting the summed input signal and/or the nonlinear function. In another embodiment, the dynamically configurable logic gate includes feedback to one of the inputs. The dynamically configurable logic gate receives the two inputs and operates as one of a plurality of different logic gate types so as to produce an output signal that corresponds to a memory latch according to a selection of the control signal. An array structure of dynamically configurable logic elements is also disclosed.

Abstract: A method of implementing a comparator in a device having programmable logic is described. The method comprises implementing a first comparison function in a first lookup table; implementing a second comparison function in a second lookup table; and using an output associated with the first comparison function to select an output of the comparator. A device having programmable logic comprising a comparator is also described.

Abstract: A switching power-supply circuit generates a predetermined output voltage by controlling a first switching transistor connected to a power supply and a second switching transistor connected between the first switching transistor and the ground. The switching power supply circuit includes a first driver, a second driver, a soft-start voltage generator and an error amplifier. The first driver drives the first switching transistor. The second driver drives the second switching transistor. The soft-start voltage generator generates a soft-start voltage that increases gradually after the time of start. The error amplifier amplifies an error voltage between a feedback voltage based on the predetermined output voltage and the soft-start voltage, and controls the first and second drivers in accordance with an amplified error voltage.

Abstract: A system and method for using one or more clock signals is disclosed. The system includes a clock translator that has a first input to receive a first reference clock signal and a second input to receive a second reference clock signal. The clock translator also includes an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to the frequency of the first reference clock but having a resolution based on at least a portion of the second reference clock signal. The second reference clock has a faster rate than the first reference clock.

Abstract: A transmission circuit, which transmits a differential signal having pulse time larger than a predetermined minimum pulse time, includes: a driving unit for feeding the differential signal as a potential difference between two transmission lines; a driven unit for operating on the basis of the differential signal by receiving the differential signal by the potential difference between the two transmission lines; and a connecting resistor for electrically connecting the two transmission lines. Further, a connecting MOS transistor may be provided near a receiving end of the driven unit.

Abstract: A supply voltage removal detecting circuit, a display device and method for removing a latent image when a supply voltage is disconnected, in which the supply voltage removal detecting circuit includes a voltage controller, a detection signal generator, and an output unit. The voltage controller controls voltages such that when a first supply voltage and a second supply voltage stay at a first level, the voltage at a first node is greater than the voltage at a second node, and when the first supply voltage or the second supply voltage becomes a second level, the voltage at the second node stays at a specific level, and the voltage at the first node is less than the specific level. The detection signal generator generates a detection signal by comparing the voltage at the first node with the voltage at the second node.

Abstract: Circuits that provide a gate boost to address non-linear threshold voltage variation in a CMOS T/H circuit. In embodiments of the invention, a boost capacitor and a feedback amplifier add a signal-dependent threshold voltage to the switch gate over-drive voltage of a switch that controls track and hold circuit sampling. In a modified embodiment, capacitive boost is omitted and the feedback amplifier provides the signal-dependent threshold voltage boost. In another embodiment, a boost capacitor and a diode connected transistor provide the signal-dependent threshold voltage boost. In a modified embodiment, capacitive boost is omitted and the diode connected transistor provides the signal-dependent threshold voltage.

Abstract: This invention relates to a resonant gate drive circuit for a power switching device, such as a MOSFET, that uses a center-tapped transformer to increase the driving gate voltage approximately twice as high as the supply voltage. The gate capacitance of the power switching device is charged and discharged by a constant current source, which increases the switching transition speed of the power switch. The circuit is suitable for driving a pair of low side switches with 50% duty cycle or less, such as in a variable frequency resonant converter, push-pull converter, or the like.

Abstract: The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.

Abstract: A dynamic frequency divider circuit with improved leakage tolerance supports a wide frequency range. During the evaluation phase, (1) the input signals can be prevented from changing states, (2) the leakage can be reduced, or (3) both can be implemented to generate the correct output signals. In a architecture-level approach, two dynamic flip-flops can be coupled together. In a circuit-level approach, the dynamic flip-flop can include (1) two additional clocked PMOS transistor added to the inputs of the dynamic flip-flop, or (2) two additional pull-up PMOS transistors to counteract the subthreshold leakage in the NMOS transistors.

Abstract: A low-voltage detection reset circuit that suppresses a current consumption in a stand-by mode and is reduced in a size is offered. The low-voltage detection reset circuit is provided with a power-on reset circuit that operates only at power-on and outputs a reset pulse and is configured to set a detection level of a detection level setting circuit at a default value using the reset pulse and to activate a programmable low-voltage detection circuit. After the programmable low-voltage detection circuit is activated, a detection level of the programmable low-voltage detection circuit can be modified from the default value by a register.

Abstract: A delay locked loop (DLL) having a charge pump gain independent of the operating frequency of the DLL. A method for providing a constant gain for a charge pump component of a delay locked loop (DLL) is disclosed, and includes: providing a switched capacitor stage responsive to a charge phase for charging a capacitor and a dump phase for dumping the capacitor; and aligning the charge phase and the dump phase such that a control voltage provided by the charge pump is independent of a frequency of a DLL charge and discharge phase.

Abstract: The methods and circuits of the various embodiments of the present invention relate to deskewing a generated clock signal. According to one embodiment, a method of deskewing a clock signal in a circuit having a delay line comprises steps of measuring an intrinsic delay in a delay line; aligning the frequency of a generated clock signal with the frequency of a reference clock signal; and aligning the phase of the generated clock signal and the reference clock signal using the measured intrinsic delay. According to another embodiment, a circuit for deskewing a clock signal in a circuit having a delay line is also described.

Abstract: In one embodiment, a PWM controller is configured to form a control signal that has reduced noise. The control signal is used to adjust a frequency of a clock signal of the PWM controller.

Abstract: Programmable dynamic amplifiers with hysteresis are provided. The hysteretic amplifiers have a first input voltage threshold when the output voltage is at a high voltage and a second input voltage threshold when the output voltage is at a low voltage. A multiplexer controls the hysteretic threshold voltages in response to the output signal of the amplifier. The hysteretic amplifiers can be programmed to have positive or negative hysteresis. When the amplifier is programmed with positive hysteresis, the output voltage transitions after the input voltages have both reached a common voltage value. When the amplifier is programmed with negative hysteresis, the output voltage transitions before the input voltages have both reached a common voltage value.

Abstract: A multi-threshold voltage complementary metal oxide semiconductor (MTCMOS) flip-flop, a circuit including the MTCMOS flip-flop, and a method of forming the MTCMOS flip-flop are disclosed. The MTCMOS flip-flop breaks a leakage current path during a sleep mode to retain an output data signal. The MTCMOS flip-flop typically further uses a data feedback unit to retain the output data signal.

Abstract: The methods and circuits of the various embodiments of the present invention relate to phase shifting of a generated clock signal. According to one embodiment, a method of phase shifting a clock signal using a delay line is described. The method comprises the steps of coupling a first delay line and a second delay line in series; generating a transition edge using the first delay line; generating an opposite transition edge using the second delay line; and outputting a first phase shifted clock signal based upon the transition edge and the opposite transition edge of the clock signal. A circuit for shifting a clock signal is also disclosed.

Abstract: A temperature compensated delay circuit for delaying a signal within an integrated circuit includes a temperature sensor. The temperature sensor is configured to sense a temperature proximal to the integrated circuit and configured to provide a control signal representative of the sensed temperature proximal to the integrated circuit. A delay chain is configured to receive a signal and provide a plurality of output signals. Each output signal has a time delay distinct from other output signals. A multiplexer is configured to receive the plurality of output signals from the delay chain and to receive the control signal from the temperature sensor representative of the sensed temperature. The multiplexer is configured to provide a temperature compensated delayed output signal.

Abstract: A DC-to-DC converter comprises a converter section and a controller section. The converter section comprises a primary section and a secondary section. The primary and secondary section includes MOSFET switches. The controller section is coupled to the converter section and comprises a pulse width modulation (PWM) section and a delay section. The PWM section comprises an error amplifier configured to generate an error signal representative of a variance between an output voltage of the converter section and a reference voltage and a PWM configured to produce a PWM signal based on the error signal. The delay section comprises of delay circuits configured to generate delayed output signals from the PWM signal and power switching device drivers coupled to the delay circuits and configured to receive the delay output signals and generate a controlled signals to control the on/off state of the MOSFET switches.

Abstract: An integrated circuit for generating a clock signal includes a voltage conversion unit, a maximum power determination unit, a clock control unit and a clock generator. The voltage conversion unit converts an external power supply voltage into an internal power supply voltage and detects a variance in current consumption of a functional block to generate a detected voltage wherein the functional block consumes a predetermined current using the internal power supply voltage. The maximum power determination unit determines a maximum current consumption of the functional block and converts the maximum current consumption to a corresponding maximum allowed voltage. The clock control unit generates at least one frequency control signal based on a comparison between the detected voltage and the maximum allowed voltage. The clock generator generates the clock signal whose frequency is adjusted according to the frequency control signal.

Abstract: A voltage level shifting circuit (5) for shifting the common mode voltage of a differential signal to be within the working range of a differential input buffer circuit (3) comprises a first resistive voltage divider circuit (18) coupled between a first input terminal (10) and a voltage reference terminal (15) for receiving a voltage reference to which the common mode voltage of the level shifted differential signal is to be referenced, and a second resistive voltage divider circuit (18) coupled between a second input terminal (11) and the voltage reference terminal (15). The differential signal is applied to the first and second terminals (10,11), and the level shifted differential signal is produced on first and second output taps (17,19) of the first and second resistive voltage divider circuits (16,18) with the common mode of the level shifted differential signal referenced to the voltage reference applied to the voltage reference terminal (15).

Abstract: The invention relates to a pulse shaping circuit for shaping electrical pulses driving an optical transmitter, e.g. a lased diode or an LED, and for providing electrical pulses having independently height and width-adjustable peaking at the edges thereof. The pulse shaping circuit of the present invention includes a high-pass RC filter with a differential output for providing transient electrical pulses from an input differential pulse, an adjustable voltage offset generating circuit, a differential amplifier for adjusting the width of the transient electrical pulses in dependence on the adjustable voltage offset, and a variable-gain current-steering amplifier for producing transient pulses with independently adjustable width and height.

Abstract: A process independent voltage controlled logarithmic attenuator has an attenuator control stage block having a first input coupled to a controlled input and a second input coupled to an offset generator. An attenuator transistor is coupled to the attenuator controlled stage block. An output of the attenuator controlled stage block is both slope and maximum voltage definable for a process independent design.

Abstract: The invention relates to a circuit arrangement having connecting terminals (K1, K2) for application of a supply voltage (V+) and having a load transistor (M) for connecting a load (Z) to the supply voltage, said load transistor having a control terminal (G) and a first and second load terminal (D, S), the control terminal (G) of the load transistor (2) being coupled to a drive terminal (IN) for application of a drive signal (Sin). A voltage limiting circuit (10) is connected between one (D) of the load terminals and the drive terminal (G) of the transistor, a deactivation circuit (20) being provided, which is designed to deactivate the voltage limiting circuit (10) in a manner dependent on the supply voltage (V+).

Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.

Abstract: A switching circuit of the present invention can be advantageously used in an electronic control unit mounted on an automotive vehicle. The switching circuit is constituted by a pair of P-channel MOS-FETs connected in series between an input terminal and an output terminal. Sources of both MOS-FETs are connected to a common source junction and gates thereof are connected to a common gate junction. A Zener diode connected between the common source junction and the common gate junction is used for protecting the MOS-FETs. A resistor is connected in parallel to the Zener diode to bring the switching circuit to a non-conductive state when the gate voltage at the common gate junction becomes indefinite and a high voltage is supplied to the output terminal. In place of the resistor, an additional P-channel MOS-FET may be used in the switching circuit to bring the switching circuit to the non-conductive state when the voltage at the common gate junction becomes indefinite.

Abstract: A method and apparatus compensate for process variations in the fabrication of semiconductor devices. A semiconductor device includes a control circuit that measures a performance parameter of the device, and in response thereto selectively biases one or more well regions of the device to compensate for process variations. For some embodiments, if measurement of the performance parameter indicates that the device does not fall within a specified range of operating parameters, the control circuit biases selected well regions to sufficiently alter the operating characteristics of transistors formed therein so that the device falls within the specified range of operating parameters.

Abstract: A voltage regulator has a first charge circuit, a second charge circuit, and a control circuit. The control circuit has five input terminals and two output terminals. The five input terminals are respectively coupled to a reference voltage, a first voltage source, a second voltage source, an output terminal of the first charge circuit, and an output terminal of the second charge circuit. The control circuit equalizes a voltage difference between the output terminal of the first charge circuit and the first voltage source and a voltage difference between the second voltage source and the output terminal of the second charge circuit.

Abstract: A charge pumping circuit includes a first switch for controlling one of push and pull operations in accordance with a first control signal; a current mirror circuit constructed from transistors each having a different polarity from the first switch; a second switch for controlling current input to the current mirror circuit in accordance with a second control signal, the second switch being constructed from a transistor having the same characteristic as a transistor used for constructing the first switch; a first MOS capacitor one end of which is connected to an input side of the current mirror circuit; a second MOS capacitor receiving, at one end thereof, a current concerned with the push and pull operations; and a voltage buffer connected to the first and second MOS capacitors. The other of the push and pull operations is performed with an output current of the current mirror circuit.

Abstract: A temperature-independent current source is provided, which includes a current source generating a current that is proportional to the temperature and a current source generating a current that is inversely proportional to the temperature. Values of the circuit elements are selected so that the currents of the current sources add up to a substantially temperature-independent current. Related current sources utilize dual-base Darlington bipolar transistors to generate a temperature-independent current.

Abstract: An active load including a current source, a first resistive element, and a switch. The current source is configured to provide a bias current and the first resistive element is configured to receive the bias current and provide a bias voltage. The switch has an input and an output and is configured to receive a drive voltage at the input, receive the bias voltage between the input and the output, provide an output voltage at the output that is sufficiently different than the drive voltage to maintain headroom, and provide an inductive impedance that enhances circuit bandwidth.

Abstract: An amplifier circuit includes a first clock generator and a pulse width modulator. The first clock generator outputs a first clock of which frequency is dependent on the voltage level of a power supply voltage. The pulse width modulator generates a signal having a duration proportional to data based on the first clock.

Abstract: An apparatus and method of reducing a flicker noise of a CMOS amplifier is provided. In the CMOS amplifier, a load circuit is connected to a signal input circuit which includes two pairs of MOSFETs which simultaneously receive differential signals. In this instance, a first MOSFET included in a switch-bias circuit is connected to one pair of MOSFETs which receive the differential signals and functions as a current source in the case of activation of a clock signal Ø1. A second MOSFET included in the switch-bias circuit is connected to another pair of MOSFETs which receive the differential signals and functions as a current source in the case of activation of a clock signal Ø2.

Abstract: An operational amplifier includes a differential amplifier circuit, receiving a low voltage signal, and a current mirror circuit provided on the downstream. The differential amplifier circuit also includes low withstand voltage N-channel transistors, connected to respective input terminals, and high withstand voltage N-channel transistors, connected to the drain electrodes of the low withstand voltage transistors via junction points, respectively. To the gate electrodes of both the high withstand voltage transistors supplied is a bias voltage. The source electrodes of the low withstand voltage transistors are connected to the drain electrode of another low withstand voltage transistor, which has its gate electrode supplied with a bias voltage so as to operate as a current source. Those low withstand voltage transistors are smaller in size than the high withstand voltage transistors.

Abstract: The invention includes methods and systems for providing a multi-path common mode feedback loop in an amplifier system. Embodiments include techniques for dividing a common mode feedback current path to provide a slow common mode feedback current path and a fast common mode feedback current path. The slow and fast paths are configured for controlling common mode feedback current within a small bandwidth.

Abstract: An amplifier comprises a carrier amplifier which performs signal amplification at all times, a peak amplifier which operates only at a time when the high electric power is outputted, a combiner which combines the output from the carrier amplifier and the peak amplifier, and a distributor which distributes an input signal to the carrier amplifier and the peak amplifier. The carrier amplifier and the peak amplifier are included in a single package transistor.

Abstract: An amplifier arrangement is proposed which has an amplifier with adjustable amplification having an output. An impedance transformer circuit is connected to the output. Said circuit is designed for transforming a high output impedance of the adjustable amplifier into a low impedance at its output. The amplifier arrangement contains at least two switchable elements having a reactance, which elements are connected in each case by a first terminal to the output of the impedance transformer circuit, and by a second terminal to a reference potential terminal. The switchable elements are designed for changing the impedance at the output of the impedance transformer circuit depending on a switch position of a switching means. A load impedance at the output of the amplifier is consequently varied by simple means when the output level of the amplifier changes.

Abstract: A transimpedance amplifier (TIA) with negative impedance compensation comprises a TIA element and a negative impedance compensator connected to the output terminal of the TIA element. The major components of the negative impedance compensator are a negative impedance element formed by a positive feedback circuit, and a compensation circuit for the parasitic capacitance at the output terminal. The negative impedance compensator changes the equivalent impedance of the output terminal from low to high with respect to the ground, and compensates the parasitic capacitance at the output terminal. Thus, an increase of both bandwidth and voltage gain is achieved.

Abstract: The present invention provides a circuit, a control system, an IC, a transmitting and receiving apparatus, a control method, and a program which can reduce a phase error and simultaneously suppress a high-frequency jitter component and a low-frequency wander component. A PLL1 unit which is a high-frequency jitter suppression unit, a PLL2 unit which is a low-frequency wander suppression unit, and a PLL3 unit which is a reproduction clock unit are connected to form a multiloop synthesizer configuration.