Abstract: A memory device includes memory cells each having a recordable layer between two metal layers, each memory cell being constructed and designed to change from a first state to a second state upon application of an initialization signal, and change from the second state to a third state upon application of a write signal. For a voltage within a specified range that is applied across the two metal layers, the memory cell has a lower resistance in the first state than in the second state, and has a higher resistance in the second state than in the third state.

Abstract: A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage of the PD SOI device may indicate, among others, how long the PD SOI device has been idling, which indirectly indicates how long data in the data retaining device has not been accessed. As such, the current invention may be used efficiently with, e.g., a cache replacement algorithm in a management of the data retaining device.

Abstract: A voltage reference generator includes multiple closed loop voltage references. Each of the closed loop voltage references uses a flash cell with a variable threshold voltage and a feedback loop to trim a reference voltage. The voltage reference generator includes sample and hold capacitors in output stages to allow reference voltages to be refreshed during a standby mode of operation.

Abstract: Disclosed are an apparatus and a method for reading data. The method for reading data according to example embodiments includes comparing a threshold voltage of a memory cell with a first boundary voltage, comparing the threshold voltage with a second boundary voltage having a higher voltage level than that of the first boundary voltage, and determining data of the memory cell based on the threshold voltage, the first boundary voltage, and the second boundary voltage.

Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes receiving a request to read data stored in a first cell of a first word line, performing a read operation on an adjacent cell of a second word line in response to the request, determining whether the first cell is in a disturbed condition based on the read operation. The method includes reading data stored in the first cell in response to the read request by applying a read reference voltage to the first word line and adjusting a sensing parameter if the first cell is in the disturbed condition.

Abstract: A programming method for programming stored bits in floating gates of a flash memory cell or selected flash memory cells of a flash memory array is utilized for applying SSI injection on said flash memory cell or said selected flash memory cells of a flash memory array is disclosed. Constant charges at the drain regions of said flash memory cell or said selected flash memory cells of the flash memory array is implemented with a capacitor and a related switch for suppressing variant injected-charges-related properties in applying the SSI injection. A constant biasing current, which may be implemented with a constant current source or a current mirror equipped with a constant current source, is applied on source regions of said flash memory cell or said selected flash memory cells of the flash memory array for enhancing the suppression of said variant biasing properties.

Abstract: Provided are a memory cell programming method and a semiconductor device which may be capable of simultaneously writing a bit of data and then another bit of the data to a plurality of memory blocks. The memory programming method, in which M bits of data are written to a plurality of memory blocks, may include a data division operation and a data writing operation where M may be a natural number. In the data division operation, the plurality of memory blocks may be divided into a plurality of memory block groups. In the data writing operation, an ith bit of the data may be simultaneously written to two or more memory block groups from among the plurality memory block groups, and then an i+1th bit of the data may be simultaneously written to the two or more memory block groups from among the plurality memory block groups, where i is a natural number less than M.

Abstract: Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.

Abstract: A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage?the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation.

Abstract: A decoder, a memory system, and a physical position converting method thereof may detect whether an address count of an input address is equal to or greater than a predetermined value. A physical position of a semiconductor memory device corresponding to the input address may be converted if the address count is equal to or greater than the predetermined value.

Abstract: A method of operating a non-volatile memory device included in a memory card can be provided by re-mapping addresses of bad blocks in a first non-volatile MAT in a memory card and re-mapping addresses of bad blocks in a second non-volatile MAT in the memory card, the second non-volatile MAT including blocks that are address mapped with blocks in the first non-volatile MAT. Also a method of scanning a non-volatile memory device for bad blocks can be provided by sequentially scanning blocks in a non-volatile memory device for data indicating that a respective block is a bad block starting at a starting block address that is above a lowermost block address of the non-volatile memory device, wherein the starting block address is based on a yield for the non-volatile memory device.

Abstract: In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.

Abstract: The present invention provides a non-volatile memory string having serially connected dual-gate devices, in which a first gate dielectric layer adjacent a first gate electrode layer in each dual-gate device is charge-storing and in which the second gate electrode adjacent a non-charge storing gate dielectric layer are connected in common. In one implementation, the second gate electrodes of the dual-gate devices in the memory string are provided by a continuous layer of doped polysilicon, tungsten, tantalum nitride, tungsten nitride or any combination of two or more of these conductors.

Abstract: An architecture, circuit and method for providing a very dense, producible, non volatile FLASH memory with SONOS cells. Preferred SONOS memory cells are formed using a uniformly doped channel region. A FinFET embodiment and a planar FD-SOI embodiment cell are disclosed. Because the novel SONOS cells do not rely on diffused regions, the cells may be formed into a three dimensional array of cells without diffusion problems from subsequent thermal processing steps. FLASH memory arrays are formed by forming layers of NAND Flash cells in the local interconnect layers of an integrated circuit, with the metal layers forming the global bit line conductors. The three dimensional non volatile arrays formed of the SONOS cells rely on conventional semiconductor processing and so are easily integrated with other circuitry to form an ASIC or SoC device. P-channel and n-channel devices may be used to form the SONOS non-volatile cells.

Abstract: A threshold voltage distribution of a set of storage elements in a memory device is measured by sweeping a control gate voltage while measuring a characteristic of the set of storage elements as a whole. The characteristic indicates how many of the storage elements meet a given condition, such as being in a conductive state. For example, the characteristic may be a combined current, voltage or capacitance of the set which is measured at a common source of the set. The control gate voltage can be generated internally within a memory die. Similarly, the threshold voltage distribution can be determined internally within the memory die. Optionally, storage elements which become conductive can be locked out, such as by changing a bit line voltage, so they no longer contribute to the characteristic. New read reference voltages are determined based on the threshold voltage distribution to reduce errors in future read operations.

Abstract: Provided are a method of writing/reading data into/from a memory cell and a page buffer using different codes for the writing and reading operations. The method of writing/reading data into/from a memory cell that has a plurality of threshold voltage distributions includes a data writing operation and a data reading operation. In the data writing operation, data having a plurality of bits is written into the memory cell by using a plurality of writing codes corresponding to threshold voltage distributions. In the data reading operation, the data having a plurality of bits is read from the memory cell by using reading codes corresponding to the threshold voltage distributions from among the threshold voltage distributions. In the method of writing/reading data into/from a memory cell, a part of the writing codes is different from a corresponding part of the reading codes.

Abstract: Provided are a memory device, a method of manufacturing the same, and a method of operating the same. The memory device may include a channel region having an upper end where both sides of the upper end are curved, the curved portions of both sides allowing charges to be injected thereinto in a program or erase voltage such that the curved portions into which the charges are injected are separate from a portion which determines a threshold voltage, and a gate structure on the channel region.

Abstract: A self sensing reference system and method are described. The self sensing reference systems and methods facilitate efficient accurate access to information. In one embodiment, a self sensing reference system includes a main cascode component, a self referencing component, and a comparison verification component. The main cascode component receives input on a first current value and a second current value. The self referencing component establishes a plurality of data indications wherein a first data indication is established based upon a comparison of the first current value to the second current value. A comparison verification component verifies a second data indication.

Abstract: A flash memory device includes a cell array and a voltage supplying and selecting portion. The cell array includes multiple word lines, and the voltage supplying and selecting portion is configured to generate at least two different voltages to be supplied to the word lines of the cell array during an erase operation.

Abstract: A semiconductor memory device employs a clamp for preventing latch up. For the purpose, the semiconductor memory device includes a precharging/equalizing unit for precharging and equalizing a pair of bit lines, and a control signal generating unit for producing a control signal which controls enable and disable of the precharging/equalizing unit, wherein the control signal generating unit includes a clamping unit to clamp its source voltage to a voltage level lower than that of its bulk bias.

Abstract: The present invention relates to a semiconductor device, and more precisely to an 1-transistor type DRAM cell implemented using bulk silicon, a DRAM device and a DRAM comprising thereof and a driving method thereof and a manufacturing method thereof. The driving method of an 1-transistor type DRAM comprises: a data hold process biasing a word line at a negative voltage level and biasing a sensing line and a bit line at a first constant voltage level; a data purging process resetting data by biasing the word line at a second constant voltage level and biasing the sensing line and the bit line at the first constant voltage level; and a data write process allowing a write current to be flowed from the bit line to a floating body by raising the bit line to the second constant voltage level and raising the sensing line to the half second constant voltage level, while maintaining the bias of the word line at the second constant voltage level.

Abstract: A device or method for effectively stressing an interconnect in a current path of a semiconductor device. A bidirectional current is established across the current path, which stresses the interconnect therein.

Abstract: A level-shifter circuit is adapted for shift an input voltage into an output voltage that is variable between a negative voltage value up to a preset positive voltage level. The shifter circuit includes a first circuit adapted to shift the input voltage into the preset positive voltage level, a second circuit adapted to transfer the preset voltage level to a third circuit connected to a preset negative voltage value. The third circuit is connected to a further voltage at a positive or nil level and is adapted to supply an output voltage to the preset negative level or to the positive or nil level.

Abstract: A semiconductor memory device of the present invention comprises a memory array and a read circuit that reads data of a selected cell. The memory array includes a plurality of memory cells and a reference cell each having a memory element that stores data based on change in resistance value. The read circuit includes: a voltage comparison unit that compares a value corresponding to a sense current from the selected cell with a value corresponding to a reference current from the reference cell; a first switch; and a second switch. Both of the first and second switches are provided at a subsequent stage of a decoder and at a preceding stage of the voltage comparison unit. The second switch circuit controls input of the value corresponding to the sense current to the voltage comparison unit, while the first switch circuit controls input of the value corresponding to the reference current to the voltage comparison unit.

Abstract: An input/output (I/O) line sense amplifier includes a first sense amplifier configured to amplify a signal of an I/O line in response to a strobe signal, and a second sense amplifier configured to latch and amplify an output signal of the first sense amplifier in response to the strobe signal.

Abstract: A semiconductor memory device has a memory cell having a hierarchical bit line structure for large capacity even in a small cell size. The semiconductor memory device comprises a unit cell configured to read/write data, a cell data sensing unit configured to adjust a current amount of a main bit line depending on a sensing voltage of a sub bit line when data are sensed, and a write control unit configured to store data in the corresponding unit cell depending on a current level applied from the main bit line to the sub bit line.

Abstract: A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory.

Abstract: A data input circuit of a semiconductor memory apparatus includes a plurality of data input sense amplifiers, each of which amplifies input data in response to a data input strobe signal and generates amplified data, and a data selecting block that selectively outputs a plurality of amplified data in response to starting addresses.

Abstract: A memory device for repairing a neighborhood of rows in a memory array using a patch table is disclosed. In one embodiment, circuitry in the memory device is operative to store, in a temporary storage area of the memory device, (i) first data to be stored in row N in the memory array, (ii) second data, if any, stored in row N?1 in the memory array, and (iii) third data, if any, stored in row N+1 in the memory array. The circuitry is operative to write the first data in row N in the memory array, and, in response to an error in writing the first data, to write the first data, the second data, if any, and the third data, if any, in respective rows in a repair area in the memory device. The circuitry is further operative to add the addresses of rows N?1, N, and N+1 to a table stored in the memory device.

Abstract: There is provided a test apparatus that tests a device under test.

Abstract: Techniques for reducing leakage current in memory arrays are described. A memory array has multiple rows and multiple columns of memory cells. Bit lines are coupled to the columns of memory cells, and word lines are coupled to the rows of memory cells. The bit lines have disconnected paths to a power supply and float during a sleep mode for the memory array. The bit lines may be coupled to (i) precharge circuits used to precharge the bit lines prior to each read or write operation, (ii) pass transistors used to couple the bit lines to sense amplifiers for read operations, and (iii) pull-up transistors in drivers used to drive the bit lines for write operations. The precharge circuits, pass transistors, and pull-up transistors are turned off during the sleep mode. The word lines are set to a predetermined logic level to disconnect the memory cells from the bit lines during the sleep mode.

Abstract: A method for erasing and recovering a memory array is disclosed. The memory array includes a plurality of sectors of memory cells. After erasing a sector of the memory array, all of the memory cells of the memory array are checked to find programmed memory cells in the other un-erased sectors of the memory array. If a programmed memory cell is found, the programmed memory cell will be programmed and verified until the threshold voltage of the programmed memory cell reaches a program verify voltage.

Abstract: A system and method for erasing a block of data in a plurality of memory cells includes clamping one of a digit line and an I/O line in a sensing circuit of a memory device to a fixed logic level. The memory cells of the block of memory cells are selected and refreshed to the fixed logic level. A sense amplifier includes a clamping circuit adapted to connect one of a digit line and an I/O line to a fixed logic level in response to an erase signal during a refresh of the selected block of memory cells.

Abstract: An access control unit performs an access operation and a refresh operation of a memory block in response to an access request and a refresh request. The access control unit operates respective memory blocks in a single-cell mode or a twin-cell mode according to cell mode information in a mode setting unit. A refresh control unit disables the refresh operation of the memory block the nonperformance of which is set in the mode setting unit. By operating only the memory block requiring high reliability in the twin-cell mode and selectively disabling the refresh operation of the memory block, a semiconductor memory can be operated optimally according to a specification of a system, enabling a reduction in power consumption.

Abstract: A circuit provides the widest possible window for capturing data and preventing run-through in a FIFO register. The FIFO register includes two registers per I/O. Two FIFO input clocks are used, one for each FIFO register. When one FIFO clock is active, the other is automatically disabled. Initially, the circuit is reset such that one clock is active, and the other disabled. Upon receiving a valid READ command, a shift chain attached to the FICLK that is currently low begins counting the clock cycles. This eventually determines when the FICLK that is currently low can be enabled. The final enable is dependent upon the turning off the FICLK that is currently high. The FICLK that is enabled during the reset turns off a fixed delay after the falling edge of the YCLK associated with the READ command.

Abstract: A multi-port volatile memory device can include a first port that is configured for data transfer to/from an external host system and the device. A volatile main memory core is configured to store data received thereat and read requested stored data thereform. A volatile sub memory core can be configured to store data received thereat and read requested stored data therefrom. A main interface circuit can be coupled to the first port and can be configured to provide data to/from the volatile main memory core and the first port in a master mode and can be configured to provide data to/from the volatile sub memory core and the first port in a slave mode. A second port can be configured for data transfer to/from an external non-volatile memory device and the device and a sub interface circuit can be coupled to the second port and configured to provide data to/from the volatile sub memory core and the second port in the slave mode.

Abstract: An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal.

Abstract: A semiconductor memory device includes: a first address buffer configured to be used in a test mode and a normal mode and to receive more addresses in the test mode than in the normal mode; and a second address buffer configured to be used in the normal mode and disabled in the test mode.

Abstract: A module includes a semiconductor device, a phase adjustment circuit generating a second clock so that a phase adjustment signal output from the semiconductor device and a first clock have a predetermined phase relationship, and an output circuit that is provided in the semiconductor device and generates the phase adjustment signal from the second clock.

Abstract: A mixer having multiple gas inlets of the type consisting of comprising a water discharge chamber composed of two concentrical tubular parts of the same length but having different diameters, defining an internal discharge chamber having a ring-shaped transversal section in the equipment. The discharge chamber is provided with two tangential points, an upper inlet point for the pressurized water and another lower outlet point for the solubilized water, in such a way that an area (for the injection of gases is defined between said points by a spread box provided in its external wall with a plurality of inlets interconnected to reservoirs of gases that pass through external compressors.

Abstract: The present invention relates to a wet-type recirculation system for particle size analysis of sample including coarse particles (hundreds to thousands ?m). According to the wet-type recirculation system of the present invention, the mixture liquid is recirculated using not a single recirculation line but two recirculation lines between the mixer and the particle size analyzer and the recirculation lines are connected with the mixer at the upper inputting part side of the mixer to discharge the mixture liquid. Further, the rotatable baffle is attached to the inside of the mixer to generate vortex in a horizontal direction as well as a vertical direction within the reservoir of the mixer and the baffle is rotated by a pressure of the mixture liquid discharged from the two recirculation lines to form vortex.

Abstract: A homogenizer device, is for the preparation of homogenized samples of food substances the bacterial flora content of which is to be analyzed includes a cup-like container (4) for receiving the sample to be homogenized and a lid (16) for the closure of the cup-like container. The homogenizer device (40, 42) includes a shaft (40) having a proximal end (44) provided with an engagement (44) for connection to a drive and a distal end (46) connected to an abrasive homogenizer member (42), the shaft (40) being mounted rotatably in an opening (24) of the lid (22, 16) and being provided with a tapered proximal portion (56) having a diameter which increases towards the proximal end (44) and which opposes forward movement of the shaft towards the sample by dimensional interference with the opening (24).

Abstract: An apparatus for collecting geophysical information may include a geophysical information station disposed along a seismic communication cable. A bypass circuit responsive to a command signal is in communication with a switching circuit that is operable to route electrical power, commands, data or a combination to bypass the geophysical information station in response to the command signal. An exemplary method for bypassing a geophysical information station in a geophysical information collection system includes sending a command signal to a bypass circuit and activating one or more switching circuits using the bypass circuit to route electrical power, commands, data or a combination to bypass the geophysical information station in response to the command signal.

Abstract: A seismic streamer and a method for positioning a group of hydrophones in a seismic streamer. The hydrophones in a group are spaced irregularly along the length of the streamer to reduce the influence of bulge-wave noise and flow noise on the hydrophone group response. The irregular spacing may be produced as pseudorandom deviations of the actual positions of the hydrophones from a nominal uniform spacing of hydrophones.

Abstract: A technique for use in marine seismic surveying includes a method and an apparatus. In one aspect, the method includes towing a seismic spread including a source multiple streamers on a generally curved advancing path, the streamers being actively steered. The source is fired and data is acquired on the curve. In other aspects, the method is performed with only a single vessel or the generally curved advancing path is a sincurve advancing path. The method may include a dual circular shoot in another aspect. And, in yet another aspect, the invention includes an apparatus comprised of a computing apparatus on board a tow vessel receiving positioning data from the marine seismic streamers. It is also programmed to: sail the tow vessel in a generally curved advancing path and actively steer the marine seismic streamers through the generally curved advancing path.

Abstract: Methods and systems for taking measurements related to subterranean formations. The methods and systems provide robust, reliable first arrival data for component signals of interest, which may be used to estimate formation slowness, characterize formation slowness zones, or act as an input to other processes. The methods and systems are capable of automatically providing good first arrival data based on signals received without any human interaction, and without setting or changing any parameters.

Abstract: A method is provided for processing seismic data for interpretation. The method includes recording an original seismic data trace, decomposing the original seismic data trace into a set of predefined wavelets, and reconstructing a seismic data trace from, at least a subset of, the set of wavelets.

Abstract: A system and method may, based on a 3D seismic data set seed point, execute a seed picking algorithm, using the first point for picking a set of second points from the data set, setting each of the points in the set of second points as the first point and repeating the algorithm. An iteration number or other attribute may be assigned to the points, the iteration number corresponding to the number of times the algorithm repeated to process the point. The attribute or a number of attributes may be displayed as a visual characteristic for each point. An iterative process may be applied to a set of seismic data points, starting at a seed data point and finding a set of next iteration seed points from among the set of points neighboring the seed point, continuing only with next iteration seed points, and recording for each of a set of data points the number of points that are found by the process when the point is used as a seed data point.

Abstract: The invention is directed to a system for detecting seismic waves. The system has one or more sensor modules. Each sensor module has a detection unit, a positioning module, a digitizer, a radio transmitter, and a power supply. The system also includes a communications interface including a receiver, a data storage device, and a data relay module, and a data processor. The system may be used to detect seismic events by positioning sensor modules in an area, positioning a communications interface module in an area, establishing communication, polling the sensor modules for data, and relaying the data. The polling and relaying may be repeated at predetermined time intervals. Then, analysis may be performed on the data, and the seismic event may be identified as a precursor.

Abstract: Acoustic telemetry devices and methods that provide directional detection. In one embodiment, a disclosed acoustic telemetry device comprises at least two acoustic sensors and an electronics module.