Abstract: Materials and structures whose index of refraction can be tuned over a broad range of negative and positive values by applying above band-gap photons to a structure with a strip line element, a split ring resonator element, and a substrate, at least one of which is a photoconductive semiconductor material. Methods for switching between positive and negative values of n include applying above band-gap photons to different numbers of elements. In another embodiment, a structure includes a photoconductive semiconductor wafer, the wafer operable to receive above band-gap photons at an excitation frequency in an excitation pattern on a surface of the wafer, the excitation patterns generating an effective negative index of refraction. Methods for switching between positive and negative values of n include projecting different numbers of elements on the wafer. The resonant frequency of the structure is tuned by changing the size of the split ring resonator excitation patterns.

Abstract: A magnetoelectronic device structure 20 includes programming lines 26 and 28 and a magnetoelectronic device 24 between the programming lines 26 and 28. In one embodiment, layers 38, 40, and 42 of a colloidal dispersion of an electrically insulating material and magnetic particles are positioned between the magnetoelectronic device 24 and the programming lines 26 and 28. The magnetic particles cause the colloidal dispersion to have an enhanced magnetic permeability property. The layers 38, 40, and 42 are disposed by a spin coating technique.

Abstract: The invention relates to an assembly method to enable local electrical bonds between zones located on a face of a first substrate and corresponding zones located on a face of a second substrate, said faces being located facing each other, at least one of the substrates having a surface topography, characterised in that the method comprises steps consisting of: forming an intermediate layer comprising at least one burial layer on the face of the substrate or substrates having a surface topography to make it (them) compatible with molecular bonding of said faces of substrates to each other from a topographic point of view, the resistivity and/or thickness of the intermediate layer being chosen to enable said local electrical bonds, bringing the two faces into contact, the substrates being positioned so as to create electrical bonds between areas located on the first substrate and the corresponding areas located on the second substrate, bonding the faces of the first and second substrates by molecular bonding

Abstract: An image sensor with color filters capable of minimizing a distance through which incident light reaches photodiodes and flattening the color filters by minimizing step heights among color filters, and a method of manufacturing the same are provided. In the image sensor with the color filters, a metal is doped into an interlayer insulating SiO2 layer opened through a photosensitive film, and the color filters of red, green, and blue are formed in the interlayer insulating SiO2 layer through a heat treatment. In this case, a color filter array can be flattened by removing step heights among color filters generated in an conventional method in which the interlayer insulating SiO2 layer is sequentially coated with the color filters of red, green, and blue so as to form a color filter array. In addition, the distance through which the incident light reaches the photodiodes can be reduced by forming the color filters in the interlayer insulating SiO2 layer, thereby improving the sensitivity of the image sensor.

Abstract: Provided is a wafer level package of an image sensor capable of simply and easily packaging an image sensor in a packaging process, and a method for manufacturing the same. The wafer level package of an image sensor includes a lower substrate including an image sensor, a conductive pattern coupled to the image sensor, and a plurality of vias coupled to the conductive pattern; a micro lens array film having a plurality of micro lenses corresponding to the image sensor, the micro lenses being formed on the lower substrate; and a sealing line surrounding the image sensor while being spaced apart from the image sensor and being in contact with an upper substrate.

Abstract: In a solid-state imaging device 1 in which a hollow section 9 is formed between a solid-state imaging element 2 and a covering section 4 and an air path 7 extending from the hollow section 9 to the outside is formed in an adhesive section 5, a shielding section 11 for shielding the air path 7 is formed on the air path 7 so as to be positioned on a portion exposed from the covering section 4. This makes it possible to reduce noises occurring in a signal processing section of a semiconductor element while preventing condensation in the covering section for covering the semiconductor element.

Abstract: A sensor semiconductor device and a manufacturing method thereof are disclosed. The method includes: providing a light-permeable carrier board with a plurality of metallic circuits; electrically connecting the metallic circuits to a plurality of sensor chips through conductive bumps formed on the bond pads of the sensor chips, wherein the sensor chips have been previously subjected to thinning and chip probing; filling a first dielectric layer between the sensor chips to cover the metallic circuits and peripheries of the sensor chips; forming a second dielectric layer on the sensor chips and the first dielectric layer; forming grooves between the sensor chips for exposing the metallic circuits such that a plurality of conductive traces electrically connected to the metallic circuits can be formed on the second dielectric layer; and singulating the sensor chips to form a plurality of sensor semiconductor devices.

Abstract: A lidded chip is provided which includes a chip having a major surface and a plurality of first chip contacts exposed at the major surface. A lid overlies the major surface. A chip carrier is disposed between the chip and the lid, the chip carrier having an inner surface confronting the major surface and an outer surface confronting the lid. A plurality of first carrier contacts of the chip carrier are conductively connected to the first chip contacts. A plurality of second carrier contacts extend upwardly at least partially through the openings in the lid.

Abstract: A solid-state imaging device 1 is arranged so that a hollow section 9 is formed between a solid-state imaging element 2 and a covering section 4 and an air path 7 is formed in an adhesive section 5 so as to extend from the hollow section 9 to the outside, wherein the adhesive section 5 is formed so as not to be positioned on a signal processing section 8 for processing a signal of the solid-state imaging element 2. This makes it possible to reduce noises occurring in the signal processing section of the semiconductor element while preventing occurrence of condensation in the covering section for covering the semiconductor element.

Abstract: An infrared detector comprises: first and second container members bonded to each other along an annular bonding portion to define a vacuum-sealed inner space, where the second container member has an infrared-transmissive property; an infrared detecting element disposed in the inner space; a first annular metallization layer formed on the bonding portion of the first container member; a second annular metallization layer formed on the bonding portion of the second container member; a solder metal for air-tightly bonding the first metallization layer and the second metallization layer; and a third metallization layer formed in a vicinity of one of the first and second metallization layers such that the third metallization layer overlaps the other of the first and second metallization layers at least partly.

Abstract: A backside-illuminated imaging device, which performs imaging by illuminating light from a back side of a semiconductor substrate to generate electric charges in the semiconductor substrate based on the light and reading out the electric charges from a front side of the semiconductor substrate, is provided and includes: a back-side layer including an back-side element on the back side of the semiconductor substrate; a front-side layer including an front-side element on the front side of the semiconductor substrate; a support substrate above the front-side layer; a spacer, one end of which comes in contact with the front-side layer and the other end of which comes in contact with the support substrate, to form a space having a uniform distance between the semiconductor substrate and the support substrate; and an adhesive filled in at least a part of the space between the surface-side element formation layer and the support substrate.

Abstract: An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.

Abstract: A junction barrier Schottky diode has an N-type well having surface and a first impurity concentration; a p-type anode region in the surface of the well, and having a second impurity concentration; and an N-type cathode region in the surface of the well and horizontally abutting the anode region, and having a third impurity concentration. A first N-type region vertically abuts the anode and cathode regions, and has a fourth impurity concentration. An ohmic contact is made to the anode and a Schottky contact is made to the cathode. The fourth impurity concentration is less than the first, second and third impurity concentrations.

Abstract: Provided is a semiconductor device that is capable of suppressing occurrence of a crystal defect in an elongated circuit region formed in an SOI substrate. Low-voltage transistor regions are separated, by multiple inner isolation layers, into multiple sub-regions. For this reason, the length of the longitudinal direction of the sub-regions is reduced, even though the low-voltage transistor regions are extremely elongated, for example. This configuration can suppress occurrence of a crystal defect in the low-voltage transistor regions in the longitudinal direction thereof, although such defect may occur due to the difference in thermal expansion or thermal contraction between a semiconductor layer in the low-voltage transistor regions, and the element isolation layers.

Abstract: To provide a semiconductor substrate including a crystalline semiconductor layer which is suitable for practical use, even if a material different from that of the semiconductor layer is used for a supporting substrate, and a semiconductor device using the semiconductor substrate. The semiconductor substrate includes a bonding layer which forms a bonding plane, a barrier layer formed of an insulating material containing nitrogen, a relief layer which is formed of an insulating material that includes nitrogen at less than 20 at. % and hydrogen at 1 at. % to 20 at. %, and an insulating layer containing a halogen, between a supporting substrate and a single-crystal semiconductor layer. The semiconductor device includes the above-described structure at least partially, and a gate insulating layer formed by a microwave plasma CVD method using SiH4 and N2O as source gases is in contact with the single-crystal semiconductor layer.

Abstract: A semiconductor component includes a substrate, two isolation structures, a conductor pattern and a dielectric layer. The isolation structures are disposed in the substrate, and each of the isolation structures has protruding portions protruding from the surface of the substrate. A trench is formed between the protruding portions. The included angle formed by the sidewall of the protruding portion and the surface of the substrate is an obtuse angle. The conductor pattern is disposed in the trench and fills the trench up. The dielectric layer is disposed between the conductor pattern and the substrate.

Abstract: A fuse structure (106) includes a patterned conductor disposed over a passivation layer (302), which is disposed over a substrate (110), such as, for example, an inter-layer dielectric layer of an integrated circuit. A second passivation layer (112) is formed over the integrated circuit including over the fuse structure (106), and then patterned to open a window (108) through the second passivation layer (112) at a location over the fuse structure (106), with the window (108) fully landed by the underlying passivation layer (302). In various aspects of the present invention, the fuse (106) may be programmed either before or after the photoresist layer used in the patterning of the second passivation layer (112) is removed.

Abstract: According to one exemplary embodiment, a programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to a P side terminal of the poly fuse. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to an N side terminal of the poly fuse. During a normal operating mode, a voltage less than or equal to approximately 2.5 volts is applied to the N side terminal of the programmable poly fuse. A voltage higher than approximately 3.5 volts is required at the N side terminal of the poly fuse to break down the P-N junction.

Abstract: A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier.

Abstract: A semiconductor device is manufactured by forming a hole as being extended through a first insulating film and an insulating interlayer stacked over a semiconductor substrate, allowing side-etching of the inner wall of the hole to proceed specifically in a portion of the insulating interlayer, to thereby form a structure having the first insulating film projected out from the edge towards the center of the hole; forming a lower electrode film as being extended over the top surface, side face and back surface of the first insulating film, and over the inner wall and bottom surface of the hole; filling a protective film in the hole; removing the lower electrode film specifically in portions fallen on the top surface and side face of the first insulating film; removing the protective film; and forming a cylindrical capacitor in the hole.

Abstract: A semiconductor device according to the present invention has a multilayer wiring structure laminating and disposing a plurality of with sandwiching an insulating film and includes: a copper wire having copper as a main component; an insulating film formed on the copper wire; an aluminum wire having aluminum as a main component and formed on the insulating film to be electrically connected to the copper wire via a via hole formed to penetrate through the insulating film; and a surface protective film formed on the aluminum wire; and the surface protective film formed with a pad opening exposing a portion of the aluminum wire as an electrode pad for electrical connection with an external portion.

Abstract: An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.

Abstract: Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one embodiment, ends of the features are wider than middle regions of the features. During the pitch reduction process, spacer sidewalls formed between adjacent ends of the features come into substantial contact with one another, isolating the spaces between the features. In another embodiment, the features have a single width and an additional feature is located near ends of the features. Spacer sidewalls formed between adjacent features and the additional feature come into substantial contact with one another, isolating the spaces between the features.

Abstract: A semiconductor wafer assembly includes a disk-shaped semiconductor wafer including on a face side thereof a flat area having a plurality of semiconductor devices formed thereon and a beveled surface disposed around the flat surface, and a circular adhesive film bonded to a reverse side of the semiconductor wafer. The adhesive film is bonded only to an area of the reverse side which is coextensive with the flat area.

Abstract: A microchip formed by joining a first substrate having at least one recess on its surface and a second substrate, wherein small projections of 0.5 to 30 ?m in height are formed on at least a part of the surface having the recess of the first substrate, and a coating formed of a surface processing agent is provided on at least a part of the surface having the small projections formed thereon, as well as a method of manufacturing the microchip, are provided. A microchip allowing easy inspection of the state of application or state of adhesion of liquid material such as a surface processing agent, and allowing accurate optical measurement without causing disturbance such as fluorescence, can be provided.

Abstract: In the present invention, a first circuit pattern 3 composing a semiconductor element is formed on the front side of a substrate 1, a first insulating layer 2 is formed on the first circuit pattern 3, solder electrodes 5 for external connection are formed on the first insulating layer 2, a second insulating layer 6 is formed on the backside of the substrate 1, a second circuit pattern 7 is formed on the second insulating layer 6, through vias 8 are formed to connect the first circuit pattern 3 and the second circuit pattern 7, chip passive components 9 are placed on the second circuit pattern 7, and the backside of the substrate is integrally molded with epoxy resin 10 such that the epoxy resin 10 covers the chip passive components 9.

Abstract: A method for etching features of different aspect ratios in a conductive layer is provided. The method comprises: depositing over the conductive layer with an aspect ratio dependent deposition; etching features into the conductive layer with an aspect ratio dependent etching of the conductive layer; and repeating the depositing and the etching at least once.

Abstract: One possible embodiment is a method of manufacturing a structure on or in a substrate with the following steps a) positioning at least one spacer structure by a spacer technique on the substrate, b) using at least one of the groups of the spacer structure and a structure generated by the spacer structure as a mask for a subsequent particle irradiation step for generating a latent image in the substrate c) using the latent image for further processing the substrate.

Abstract: A GaAs semiconductor substrate includes a surface layer. When an atomic ratio is to be calculated using a 3d electron spectrum of Ga atoms and As atoms measured at the condition of 10° for the photoelectron take-off angle ? by X-ray photoelectron spectroscopy, the structural atomic ratio of all Ga atoms to all As atoms (Ga)/(As) at the surface layer is at least 0.5 and not more than 0.9, the ratio of As atoms bound with O atoms to all Ga atoms and all As atoms (As—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35, and the ratio of Ga atoms bound with O atoms to all Ga atoms and all As atoms (Ga—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35. Accordingly, there is provided a GaAs semiconductor substrate having a surface cleaned to an extent allowing removal of impurities and oxides at the surface by at least thermal cleaning of the substrate.

Abstract: Provided is a method of forming a thin film structure and a stack structure comprising the thin film. The method may include forming a crystalline AlxOy film, forming a LaAlO film on the crystalline AlxOy film, and crystallizing the LaAlO film by annealing the LaAlO film.

Abstract: A method for manufacturing a semiconductor device is provided that can reduce warping of manufactured products after the formation of a final protective film. The method includes, in a semiconductor device having a semiconductor substrate provided with wiring and a final protective film formed on the wiring, forming a first protective film on the wiring, forming a second protective film having tensile stress on the first protective film, and removing the first protective film and the second protective film from contact regions of the wiring.

Abstract: Passivation films including first and second layers (first passivation film) are formed on a GaAs substrate (semiconductor substrate). A SiN film (second passivation film) is formed on the passivation films as a top layer passivation film by a catalytic chemical vapor deposition. The SiN film formed by catalytic chemical vapor deposition has a lower degree of hygroscopicity than that of a conventional SiN film formed by plasma chemical vapor deposition.

Abstract: A semiconductor device having silicon-oxide-nitride-oxide-silicon (SONOS) structure that overcomes spatial limitations which trap charges by not utilizing a flat, planar structure of the ONO film including a charging trap layer, thereby making it possible to improve reliability for data preserving characteristic of a SONOS device.

Abstract: The present invention relates to a semiconductor device, and a method for fabricating a semiconductor device, which involves an oxide-nitride-oxide stack in a silicon-oxide-nitride-oxide-silicon device. Barrier characteristics of an upper blocking dielectric layer and/or a lower tunneling dielectric layer on upper and lower sides of a charge trapping dielectric layer are improved, so as to maintain holding characteristics of charges trapped in the charge trapping dielectric layer, making it possible to improve reliability of a semiconductor device containing the same.

Abstract: According to one embodiment, an integrated circuit includes an internal circuit and a resin layer which covers the internal circuit. A radio wave absorbing material is mixed in the resin layer.

Abstract: A semiconductor device comprises a lead frame, an antenna formed at a predetermined position on the lead frame, and a semiconductor chip. The semiconductor chip is mounted on an island of the lead frame through a spacer.

Abstract: The present invention includes a plurality of mounting portions on which a semiconductor element is mounted, a plurality of electrodes to which the semiconductor elements that are mounted on each of the mounting portions are electrically connected, a corner portion which connects the plurality of mounting portions and which has a hanging lead piece that supports the mounting portions and an electrode connection piece that connects the plurality of electrodes, and a half-blanking portion that has a concave portion formed in a thickness direction of the lead frame and a protrusion formed at a position corresponding to the concave portion, and which is covered with a sealing resin material that seals the semiconductor element. A stress-dispersing portion for dispersing stress that arises, when the half-blanking portion is formed, is provided in the corner portion.

Abstract: A micromechanical component having a substrate and having a thin-layer, as well as having a cavity which is bounded by the substrate and the thin-layer, at least one gas having an internal pressure being enclosed in the cavity. The gas phase has a non-atmospheric composition. A method for producing a micromechanical component having a substrate and having a thin-layer encapsulation, as well as having a cavity which is bounded by the substrate and the thin-layer encapsulation. The method has the steps of positioning a polymer in a cavity, closing the cavity and generating a gas phase of non-atmospheric composition in the cavity by decomposing at least a part of the polymer. An internal pressure is generated, which may be higher than the process pressure when the cavity is closed.

Abstract: A microelectronic unit has a structure including a microelectronic element such as a semiconductor chip with a first contact disposed remote from the periphery of the structure. The unit further includes first and second redistribution conductive pads disposed near a periphery of the structure and a conductive path incorporating first and second conductors extending toward the first contact, these conductors being connected to one another adjacent the first contact. The conductive path is connected to the first contact, and can provide signal routing from the periphery of the unit to the contact without the need for long stubs. A package may include a plurality of such units, which may be stacked on one another with the redistribution conductive pads of the various units connected to one another.

Abstract: A packaged microelectronic element includes a package element that further includes a dielectric element having a bottom face and a top face, first and second bond windows extending between the top and bottom faces, a plurality of chip contacts disposed at the top face adjacent to the first and second bond windows, and first and second sets of package contacts exposed at diagonally opposite corner regions of the top face, wherein the first and second sets conductively connected to the chip contacts. There is also a microelectronic element adjacent to the bottom face of the dielectric element, as well as bond wires extending through the first and second bond windows to conductively connect the microelectronic element to the chip contacts.

Abstract: A semiconductor device comprises a semiconductor chip having a photoelectric conversion function and conductor connecting with the semiconductor chip electrically. The semiconductor chip is sealed by resin. The resin comprises a first sealing resin, second sealing resin and third sealing resin. The second sealing resin has transparency for optical signal to the semiconductor chip and seals one side of the conductor. The third sealing resin seals the other side of the conductor and has a linear thermal expansion coefficient and thickness which may restrain at least a part of flexion of the conductor caused by the linear thermal expansion of the second sealing resin. The first sealing resin seals at least a part of the conductor, is sandwiched between the second sealing resin and the third sealing resin, and has a linear thermal expansion coefficient which may restrain at least a part of the linear thermal expansion of the second sealing resin.

Abstract: A semiconductor package is revealed, primarily comprising a substrate, a chip disposed on the substrate, and an encapsulant to encapsulate the chip. The substrate has a plurality of dimples formed in its top surface thereof without penetrating through the substrate and located at a non-wiring region outside a chip mounting region. Therefore, without changing the appearance of the semiconductor package, the diffusion path of moisture and the adhesive strength between the encapsulant and the substrate can be increased to achieve functions of anti-humidity and anti-delamination.

Abstract: A semiconductor product is constructed of a wiring substrate in which pads for pin connection are formed, and a substrate with pins in which pins are disposed. The substrate with the pins is formed so that one end of the pin is exposed to one surface of a resin substrate formed by resin molding and the other end of the pin extends from the other surface of the resin substrate and one end of the pin is bonded to a pad of the wiring substrate through a conductive material.

Abstract: The surface mount package is assembled from a ceramic base which is imprinted on its upper and lower surfaces with conductive patterns for attachment of and connection to an electronic or electromechanical device, a molded dielectric layer for forming a cavity and a seal ring. The molded dielectric is formed by aligning a dielectric preform with the base, positioning the seal ring on top of the preform, then applying a mold over the layers to shape the dielectric during a firing process that fuses the base, preform and seal ring to create a hermetic seal. The preform is of sufficient thickness that the electronic device will be fully contained within the cavity when placed into the completed package.

Abstract: A method and apparatus to minimize thermal impedance using copper on the die or chip backside. Some embodiments use deposited copper having a thickness chosen to complement a given chip thickness, in order to reduce or minimize wafer warpage. In some embodiments, the wafer, having a plurality of chips (e.g., silicon), is thinned (e.g., by chemical-mechanical polishing) before deposition of the copper layer, to reduce the thermal resistance of the chip. Some embodiments further deposit copper in a pattern of bumps, raised areas, or pads, e.g., in a checkerboard pattern, to thicken and add copper while reducing or minimizing wafer warpage and chip stress.

Abstract: A semiconductor includes a board, a semiconductor element mounted on the board, an electronic component, with the semiconductor element, mounted on the board, a heat radiation member provided so as to face the board, the heat radiation member configured to radiate heat of the semiconductor element, and a thermal connecting member being configured to thermally connect the heat radiation member and the semiconductor element. A metal material is used as the thermal connecting member, and an adhesion preventing member is provided so as to be separated from the electronic component, the adhesion preventing member being configured to prevent the metal material molten and flowing at a heating time being adhered to the electronic component.

Abstract: Near net shape heat spreader components are disclosed that comprise at least one pressure-treated powder material. Heat spreaders are also described that include at least one near net shape heat spreader component, and at least one additional part. Methods of forming heat spreaders are also described that include: a) forming a base portion comprising a pressure-treated powder material and having a first surface comprising a perimeter region surrounding a heat-receiving surface; b) forming a frame portion comprising a second material; and c) joining the base portion and the frame portion.

Abstract: A fluid spreader includes a first surface, wherein the first surface has at least one channel that continuously or discontinuously extends to an outer periphery of the first surface, allowing fluid to flow easily and thereby reducing the thickness of the fluid between the fluid spreader and another device or component.

Abstract: A circuit structure and a method for reducing stresses on semiconductor devices fabricated underneath bondpads include metal layers with a lattice planar configuration which spreads forces applied such as during wafer test probing or during wire bonding. Easing electrical connectivity among circuit elements and maintaining circuit performance is also carried out using the lattice. The lattice has metal strips which may connect circuit elements together or which may connect to a reference voltage source. The metal layer and bondpad corners and edges are formed preferentially without acute angles.

Abstract: A semiconductor package comprises a semiconductor component (e.g., a die) and a via at least partially covered by an encapsulant. The encapsulant forms substantially parallel top and bottom surfaces, with at least part of the via being exposed on the top surface. At least one conductive pad is exposed on the bottom surface, and the via can electrically couple the top and bottom surfaces, as well as couple the semiconductor component at the top and bottom surfaces. An additional semiconductor component can be coupled to the top surface with a circuit pattern formed on the top surface and coupled to the via.