Abstract: For a semiconductor laser, a stacked member comprising an active layer is formed on the surface of a GaN single-crystal substrate, a defect aggregation portion is formed on the rear face of the GaN single-crystal substrate, and an electrode is formed so as to be electrically connected to the defect aggregation portion on the rear face. The defect aggregation portion of this semiconductor laser has numerous crystal defects, and so the carrier concentration is high, and the electrical resistivity is lowered significantly. For this reason, in a semiconductor laser of this invention in which an electrode is formed on this defect aggregation portion, an Ohmic contact can easily be obtained between the GaN single-crystal substrate and the electrode, and by this means a lowered driving voltage is realized.

Abstract: A semiconductor device includes: a semiconductor layer having a first major surface, a second major surface provided on opposite side of the first major surface, and a channel formation region provided in a surface portion on the first major surface side; a first main electrode provided inside a dicing street on the first major surface of the semiconductor layer; a second main electrode provided inside a dicing street on the second major surface of the semiconductor layer; and a control electrode opposed to the channel formation region across an insulating film.

Abstract: Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing (100) platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing (102) platinum- or gold-comprising residues remaining on the one of the first and second surfaces after diffusing the platinum or gold, forming (104) a phosphorus- or boron-doped surface barrier layer on the first or second surface, and heating (105) the semiconductor substrate for local gettering of the platinum or gold by the phosphorus- or boron-doped surface barrier layer.

Abstract: An ESD protection device is provided. The ESD protection device comprises an SCR and an ESD detection circuit. The SCR is coupled between a high voltage and a ground and has a special semiconductor structure which saves area. When the ESD detection circuit detects an ESD event, the ESD detection circuit drives the SCR to provide a discharging path.

Abstract: A strained Si layer 2 is epitaxially grown on a base SiGe layer 1, and a gate insulating film 3a and a gate electrode 4a are formed. An impurity is then ion-implanted (FIG. 2A) into the base SiGe layer 1 and the strained Si layer 2 using the gate electrode 4a as a mask, heat treatment is performed for activation, and a source/drain region 6 is formed (FIGS. 2B and 2C). In this instance, the film thickness of the strained Si layer 2 is set to 2Tp, where Tp (=Rp) is the depth having the maximum concentration of the impurity in the source/drain region 6 of the finished MISFET.

Abstract: Growth of multilayer films is carried out in a manner which allows close control of the strain in the grown layers and complete release of the grown films to allow mounting of the released multilayer structures on selected substrates. A layer of material, such as silicon-germanium, is grown onto a template layer, such as silicon, of a substrate having a sacrificial layer on which the template layer is formed. The grown layer has a lattice mismatch with the template layer so that it is strained as deposited. A top layer of crystalline material, such as silicon, is grown on the alloy layer to form a multilayer structure with the grown layer and the template layer. The sacrificial layer is preferentially etched away to release the multilayer structure from the sacrificial layer, relaxing the grown layer and straining the crystalline layers interfaced with it.

Abstract: A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate that is heated to a temperature in a range of about 300 to 800° C., and a first film is formed in compression overlying the Si substrate. The first film material may be InP, SiGe, GaP, GaAs, AlN, AlGaN, an AlN/graded AlGaN (Al1?xGaxN (0<x<1)) stack, or a AlN/graded AlGaN/GaN stack. The first film is then nanoscale patterned and a lateral nanoheteroepitaxy overgrowth (LNEO) process is used to grow a first GaN layer. The above-mentioned processes are repeated, forming a second film in compression that is nanoscale patterned, and a second GaN layer is grown using the LNEO process. The first and second GaN layers are formed by heating the Si substrate to a temperature in a range of 1000 to 1200° C.

Abstract: A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor.

Abstract: An enhancement mode High Electron Mobility Transistor (HEMT) comprising a p-type nitride layer between the gate and a channel of the HEMT, for reducing an electron population under the gate. The HEMT may also comprise an Aluminum Nitride (AlN) layer between an AlGaN layer and buffer layer of the HEMT to reduce an on resistance of a channel.

Abstract: Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300° C. to 800° C. for annealing times between 30 minutes and 10 hours, depending on the bonding materials. The structures remained pressed together throughout the course of the annealing. Strong bonds were obtained for bonding layers between different substrates that were as thin as 3 nm and as thick as 600 nm. The bonds were ohmic with a relatively small resistance, optically transparent, and independent of the orientation of the underlying structures.

Abstract: An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.

Abstract: A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof.

Abstract: A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

Abstract: A heterojunction bipolar transistor: The transistor may a collector layer, a base layer and an emitter layer. The transistor may include a dielectric material being disposed over the base layer. The base layer may be a SiGe base layer.

Abstract: The object of the present invention is to provide a semiconductor device and the manufacturing method thereof which are capable of preventing decrease in the collector breakdown voltage and reducing the collector resistance. The semiconductor device according to the present invention includes: a HBT formed on a first region of a semiconductor substrate; and an HFET formed on a second region of the semiconductor substrate, wherein the HBT includes: an emitter layer of a first conductivity; a base layer of a second conductivity that has a band gap smaller than that of the emitter layer; a collector layer of the first conductivity or a non-doped collector layer; and a sub-collector layer of the first conductivity which are formed sequentially on the first region, and the HFET includes an electron donor layer including a part of the emitter layer, and a channel layer formed under the electron donor layer.

Abstract: A multilayer thermal expansion interface between silicon (Si) and gallium nitride (GaN) films is provided, along with an associated fabrication method. The method provides a (111) Si substrate and forms a first layer of a first film overlying the substrate. The Si substrate is heated to a temperature in the range of about 300 to 800° C., and the first layer of a second film is formed in compression overlying the first layer of the first film. Using a lateral nanoheteroepitaxy overgrowth (LNEO) process, a first GaN layer is grown overlying the first layer of second film. Then, the above-mentioned processes are repeated: forming a second layer of first film; heating the substrate to a temperature in the range of about 300 to 800° C.; forming a second layer of second film in compression; and, growing a second GaN layer using the LNEO process.

Abstract: The present invention provides nitride semiconductors having a moderate density of basal plane stacking faults and a reduced density of threading dislocations, various products based on, incorporating or comprising the nitride semiconductors, including without limitation substrates, template films, templates, heterostructures with or without integrated substrates, and devices, and methods for fabrication of templates and substrates comprising the nitride semiconductors.

Abstract: In the nitride semiconductor device using the silicon substrate, the metal electrode formed on the silicon substrate has both ohmic contact property and adhesion, so that the nitride semiconductor device having excellent electric properties and reliability is obtained. The nitride semiconductor device includes a silicon substrate (2), a nitride semiconductor layer (10) formed on the silicon substrate (2), and metal electrodes (8, 8?) formed in contact with the silicon substrate (2). The metal electrodes (8, 8?) has first metal layers (4, 4?) which are formed in a shape of discrete islands and in contact with the silicon substrate (2), and second metal layers (6, 6?) which are in contact with the silicon substrate (2) exposed among the islands of the first metal layers (4, 4?) and are formed to cover the first metal layers (4, 4?).

Abstract: A semiconductor integrated circuit includes at least one first circuit portion and at least one second circuit portion. The first circuit portion includes a first interconnect or a diffusion layer formed by exposure using a high-precision mask. The second circuit portion includes a second interconnect or a diffusion layer formed by exposure using a first low-precision mask having a lower precision than the high-precision mask.

Abstract: A solid-state imaging device includes a semiconductor substrate; a first conductive region of the semiconductor substrate; a first conductive region on an upper surface side of the first conductive region of the semiconductor substrate; a second conductive region below the first conductive region on the upper surface side of the first conductive region of the semiconductor substrate. The solid-state imaging device further includes a photoelectric conversion region including the first conductive region located on the upper surface side of the first conductive region of the semiconductor substrate and the second conductive region and a transfer transistor transferring charges accumulated in the photoelectric conversion region to a readout region; and a pixel including the photoelectric conversion region and the transfer transistor. The first conductive region, which is included in the photoelectric conversion region, extends to the lower side of a sidewall of a gate electrode of the transfer transistor.

Abstract: A pixel of an image sensor includes a gate insulation layer formed over a substrate doped with first-type impurities, a transfer gate formed over the gate insulation layer, a photodiode formed in the substrate at one side of the transfer gate, and a floating diffusion node formed in the substrate at the other side of the transfer gate, wherein the transfer gate has a negative bias during a charge integration cycle.

Abstract: A method of forming a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate is prepared first, and the semiconductor substrate has a gate structure, a source region and a drain region. Subsequently, a stress buffer layer is formed on the semiconductor substrate, and covers the gate structure, the source region and the drain region. Thereafter, a stressed cap layer is formed on the stress buffer layer, and a tensile stress value of the stressed cap layer is higher than a tensile stress value of the stress buffer layer. Since the stress buffer layer can prevent the stressed cap layer from breaking, the MOS transistor device can be covered by a stressed cap layer having an extremely high tensile stress value in the present invention.

Abstract: Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs.

Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.

Abstract: The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region.

Abstract: A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.

Abstract: According to the present invention, semiconductor device breakdown voltage can be increased by embedding field shaping regions within a drift region of the semiconductor device. A controllable current path extends between two device terminals on the top surface of a planar substrate, and the controllable current path includes the drift region. Each field shaping region includes two or more electrically conductive regions that are electrically insulated from each other, and which are capacitively coupled to each other to form a voltage divider dividing a potential between the first and second terminals. One or more of the electrically conductive regions are isolated from any external electrical contact. Such field shaping regions can provide enhanced electric field uniformity in current-carrying parts of the drift region, thereby increasing device breakdown voltage.

Abstract: A semiconductor device includes first gate structures, second gate structures, a first capping layer pattern, a second capping layer pattern, first spacers, second spacers, third spacers, and a substrate having first impurity regions and second impurity regions. The first gate structures are arranged on the substrate at a first pitch. The second gate structures are arranged on the substrate at a second pitch greater than the first pitch. The first capping layer pattern has segments extending along side faces of the first gate structures and segments extending along the substrate. The second capping layer pattern has segments extending along the second gate structures and segments extending along the substrate. The first spacers and the second spacers are stacked on the second capping layer pattern. The third spacers are formed on the first capping layer pattern.

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern including a protrusion with a lower surface on the substrate and an upper surface opposite the lower surface, a width of the protrusion gradually decreasing from the lower surface to the upper surface, the upper surface of the protrusion being sharp and defining a first active region of the active pattern along a first direction, isolation layer patterns on the substrate in recesses at both sides of the active pattern, the isolation layer patterns exposing the first active region, a gate structure on the first active region and on the isolation layer patterns, the gate structure extending along a second direction, the first and second directions being perpendicular to each other, and source/drain regions under the first active region at both sides of the gate structure.

Abstract: A plural line CMOS sensor array device is provided with sensor cells arranged in a matrix of coordinate-wise rows and columns. Each cell comprises a photosensitive area, an output node, and a transfer gate for selectively interconnecting the photosensitive area and the output node. Along at least a first coordinate direction adjacent cells are functionally configured as mutually mirror-symmetric structures in that their proximate output nodes are facing each other and are arranged for separately feeding a respective output channel. Preferably, also in a second coordinate direction adjacent cells are functionally configured as mutually mirror-symmetric structures in that their proximate output nodes are facing each other and all such facing output nodes are separately feeding a respective column-directed output channel.

Abstract: Disclosed herein is a solid-state image pickup device which includes: a light-receiving unit for photoelectric conversion of incident light; and a charge transfer unit of an n-channel insulating gate type configured to transfer a signal charge photoelectrically converted in the light-receiving unit; wherein the charge transfer unit has an insulating film formed on a transfer electrode and having a negative fixed charge.

Abstract: Provided is a multi-well CMOS image sensor and a method of fabricating the same. The multi-well CMOS image sensor may include a plurality of photodiodes vertically formed in a region of a substrate, an n+ wall that vertically connects an outer circumference of the photodiodes, and a floating diffusion region that is connected to the photodiodes on a side of the n+ wall to receive charges from the photodiodes, wherein a p-type region is formed between the floating diffusion region and the n+ wall, and the plurality of photodiodes have a multi-potential well structure.

Abstract: The present invention provides a photodiode comprising a first silicon semiconductor layer formed over an insulating layer, a second silicon semiconductor layer formed over the insulating layer, having a thickness ranging from greater than or equal to 3 nm to less than or equal to 36 nm, a low-concentration diffusion layer which is formed in the second silicon semiconductor layer and in which an impurity of either one of a P type and an N type is diffused in a low concentration, a P-type high-concentration diffusion layer which is formed in the first silicon semiconductor layer and in which the P-type impurity is diffused in a high concentration, and an N-type high-concentration diffusion layer which is opposite to the P-type high-concentration diffusion layer with the low-concentration diffusion layer interposed therebetween and in which the N-type impurity is diffused in a high concentration.

Abstract: A solid state image sensing device in which many pixels are disposed in a matrix on a two-dimensional plane comprises a plurality of light receiving devices disposed in such a way that a center interval may periodically change in a column direction and/or a row direction, and a plurality of micro-lenses, for collecting an incident light of each light receiving device, wherein a center interval periodically changes in accordance with the periodic change of the center interval of the light receiving device.

Abstract: A CMOS image sensor includes an image transfer transistor therein. This image transfer transistor includes a semiconductor channel region of first conductivity type and an electrically conductive gate on the semiconductor channel region. A gate insulating region is also provided. The gate insulating region extends between the semiconductor channel region and the electrically conductive gate. The gate insulating region includes a nitridated insulating layer extending to an interface with the electrically conductive gate and a substantially nitrogen-free insulating layer extending to an interface with the semiconductor channel region. The nitridated insulating layer may be a silicon oxynitride (SiON) layer.

Abstract: A solid-state imaging device includes a photoelectric conversion unit, a transistor, and an element separation region separating the photoelectric conversion unit and the transistor. The photoelectric conversion unit and the transistor constitute a pixel. The element separation region is formed of a semiconductor region of a conductivity type opposite to that of a source region and a drain region of the transistor. A part of a gate electrode of the transistor protrudes toward the element separation region side beyond an active region of the transistor. An insulating film having a thickness substantially the same as that of a gate insulating film of the gate electrode of the transistor is formed on the element separation region continuing from a part thereof under the gate electrode of the transistor to a part thereof continuing from the part under the gate electrode of the transistor.

Abstract: According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate; a transistor that is formed on the semiconductor substrate; a ferroelectric capacitor including a bottom electrode that is formed above the semiconductor to be connected with the transistor, a ferroelectric film that is formed on the bottom electrode, and a top electrode that is formed on the ferroelectric film; a first reaction preventing film that covers a lower side surface of the ferroelectric capacitor; and a second reaction preventing film that covers an upper side surface and a top surface of the ferroelectric capacitor.

Abstract: The present invention provides a semiconductor memory device comprising a semiconductor substrate formed of a support substrate, an insulating film formed over the support substrate and a semiconductor layer formed over the insulating film; a MOSFET having a source layer and a drain layer both formed in the semiconductor layer of a transistor forming area set to the semiconductor substrate, and a channel region provided between the source and drain layers; a MOS capacitor having a capacitor electrode which is formed in the semiconductor layer of a capacitor forming area set to the semiconductor substrate and in which an impurity of the same type as the source layer is diffused; and a device isolation layer which insulates and separates between the semiconductor layer formed with the MOSFET and the semiconductor layer formed with the MOS capacitor, wherein the capacitor electrode of the MOS capacitor is formed in polygon and slanting faces enlarged toward the insulating film are provided therearound, and where

Abstract: A semiconductor fin memory structure and a method for fabricating the semiconductor fin memory structure include a semiconductor fin-channel within a finFET structure that is contiguous with and thinner than a conductor fin-capacitor node within a fin-capacitor structure that is integrated with the finFET structure. A single semiconductor layer may be appropriately processed to provide the semiconductor fin-channel within the finFET structure that is contiguous with and thinner than the conductor fin-capacitor node within the fin-capacitor structure.

Abstract: A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.

Abstract: A metal oxide semiconductor (MOS) structure having a high dielectric constant gate insulator layer containing gold (Au) nano-particles is presented with methods for forming the layer with high step coverage of underlying topography, high surface smoothness, and uniform thickness. The transistor may form part of a logic device, a memory device, a persistent memory device, a capacitor, as well as other devices and systems. The insulator layer may be formed using atomic layer deposition (ALD) to reduce the overall device thermal exposure. The insulator layer may be formed of a metal oxide, a metal oxycarbide, a semiconductor oxide, or semiconductor oxide oxycarbide, and the gold nano-particles in insulator layer increase the work function of the insulator layer and affect the tunneling current and the threshold voltage of the transistor.

Abstract: A disclosed semiconductor device comprises a non-volatile memory cell including a PMOS write transistor and an NMOS read transistor. The PMOS write transistor includes a write memory gate oxide film formed on a semiconductor substrate and a write floating gate of electrically-floating polysilicon formed on the write memory gate oxide film. The NMOS read transistor includes a read memory gate oxide film formed on the semiconductor substrate and a read floating gate of electrically-floating polysilicon formed on the read memory gate oxide film. The write floating gate and the read floating gate are electrically connected to each other. The PMOS write transistor is configured to perform writing in the non-volatile memory cell, and the NMOS read transistor is configured to perform reading from the non-volatile memory cell.

Abstract: A split floating gate flash memory cell is comprised of source/drain regions in a substrate. The split floating gate is insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The sections of the floating gate are isolated from each other by a depression in the control gate. The cell is programmed by creating a positive charge on the floating gate and biasing the drain region while grounding the source region. This creates a virtual source/drain region near the drain region such that the hot electrons are accelerated in the narrow pinched off region. The electrons become ballistic and are directly injected onto the floating gate section adjacent to the pinched off channel region.

Abstract: A semiconductor memory device of an aspect of the present invention comprises a plurality of memory cell transistors arranged in a memory cell array, a select transistor which is disposed in the memory cell array and which selects the memory cell transistor, and a peripheral circuit transistor provided in a peripheral circuit which controls the memory cell array, the memory cell transistor including a gate insulating film provided on a semiconductor substrate, a floating gate electrode provided on the gate insulating film, a between-storage-layer-and-electrode insulating film which is provided on the floating gate electrode and through which the amount of passing charge is greater than that through the gate insulating film during the application of an electric field in write and erase operations of the semiconductor memory, and a control gate electrode on the between-storage-layer-and-electrode insulating film.

Abstract: A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a gate structure on a substrate, the gate structure including a first insulation layer, a first electrode layer for a floating gate and a second insulation layer; forming a third insulation layer on the gate structure covering predetermined regions of the substrate adjacent to the gate structure; and forming a second electrode layer for a control gate on the third insulation layer disposed on sidewalls of the gate structure and the predetermined regions of the substrate.

Abstract: A multi-time programmable (MTP) memory includes a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer. The inter-gate dielectric layer is disposed on the floating gate, and a thickness of the inter-gate dielectric layer at edges of the floating gate is larger than a thickness of the inter-gate dielectric layer in a central portion of the floating gate. The control gate is disposed on the inter-gate dielectric layer.

Abstract: A semiconductor device includes a tunnel insulation film formed on a semiconductor substrate, a floating gate electrode formed on the tunnel insulation film, an inter-electrode insulation film formed on the floating gate electrode, a control gate electrode formed on the inter-electrode insulation film, a pair of oxide films which are formed between the tunnel insulation film and the floating gate electrode and are formed near lower end portions of a pair of side surfaces of the floating gate electrode, which are parallel in one of a channel width direction and a channel length direction, and a nitride film which is formed between the tunnel insulation film and the floating gate electrode and is formed between the pair of oxide films.

Abstract: A non-volatile memory device includes a substrate and a tunnel insulation layer pattern, such that each portion of the tunnel insulation pattern extends along a first direction and adjacent portions of the tunnel insulation layer pattern may be separated in a second direction that is substantially perpendicular to the first direction. A non-volatile memory device may include a gate structure formed on the tunnel insulation layer pattern. The gate structure may include a floating gate formed on the tunnel insulation layer pattern along the second direction, a first conductive layer pattern formed on the floating gate in the second direction, a dielectric layer pattern formed on the first conductive layer pattern along the second direction, and a control gate formed on the dielectric layer pattern in the second direction.

Abstract: An embodiment of a process is disclosed herein for fabricating a memory device integrated on a semiconductor substrate and comprising at least a nanocrystal memory cell and CMOS transistors respectively formed in a memory area and in a circuitry area. According to an embodiment, a process includes forming a nitride layer having an initial thickness, placed above a nanocrystal layer, in the memory area and the formation in the circuitry area of at least one submicron gate oxide. The process also provides that the initial thickness is such as to allow a complete transformation of the nitride layer into an oxide layer at upon formation of said at least one submicron gate oxide.

Abstract: The present invention relates to a NAND flash memory array having vertical channels and sidewall gate structure and a fabricating method of the same. A NAND flash memory array of the present invention has insulator strip structure and one or more semiconductor strips are next to the both sides of the insulator strip. A NAND flash memory array of the present invention allows for an improvement of the integrity by decreasing the memory cell area by half and less, and solves the problems of the conventional three-dimensional structure regarding isolation between not only channels but also source/drain regions at the bottom of trenches. A method for fabricating the NAND flash memory array having a pillar structure, which uses the conventional CMOS process and an etching process with minimum masks, enables to cut down costs.