Abstract: A power source apparatus has a series circuit connected between output terminals of a DC power source, the series circuit including a primary winding of a transformer and a switching element; a controller configured to control an ON/OFF operation of the switching element; and an output diode connected between terminals of a second winding of the transformer and configured to rectify an alternating current that is induced on the secondary winding when the controller turns on/off the switching element. The output diode includes a plurality of diodes that are connected in parallel with one another and are made of wide-gap semiconductor.

Abstract: A rectifier for an alternating current generator is provided. The rectifier comprise a plurality of high-side rectifying elements and a plurality of low-side rectifying elements. The high-side rectifying elements are held by a plurality of high-side cooling fins, while the high-side rectifying elements are held by a plurality of low-side cooling fins. By way of example, the plurality of high-side cooling fins are disposed to be apart from each other by a predetermined distance and the plurality of low-side cooling fins are disposed to be apart from each other by a predetermined distance.

Abstract: A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.

Abstract: A semiconductor memory device includes a memory array section configured to serve as an information storage area and an interface section configured to interface between an external memory controller and the memory array section. The memory array section and the interface section are sealed in a package. The interface section has a plurality of interface modules corresponding to a plurality of memory types on a one-to-one basis. The method includes the steps of: selecting one of the plurality of interface modules in accordance with the memory type complying with specifications of the external memory controller being connected; and causing the selected interface module to access the memory array section for either a write or a read operation in response to either a write or a read request issued by the external memory controller.

Abstract: A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at VDD while the bit line drive is switched between VDD and a higher voltage, Vp for programming. The OTPROM is thus compatible with and can be integrated with other technologies without a cost adder and supports optimization of the high current path for minimal voltage drop during fuse programming. A differential sense amplifier with a programmable reference is used for improved sense margins and can support an entire bit line rather than sense amplifiers being provided for individual fuses.

Abstract: The present invention is a manufacturing method for a semiconductor device having steps of; aligning a program head 80 having a program dot array corresponding to each OTP-ROM cell array 21 provided in areas 12 to be a plurality of semiconductor chips arranged in a semiconductor wafer to the OTP-ROM cell array 21 in one of the areas to be the plurality of semiconductor chips 12; and programming the OTP-ROM cell array 21 with a different pattern for each of the areas to be the plurality of semiconductor chips 12 by using the program head 80.

Abstract: The present invention provides a method of operating a one-time programmable read only memory (OTPROM). The OTPROM includes at least a select transistor, an electrode and a dielectric layer disposed on a substrate, wherein the electrode is set up on the source region of the select transistor and the dielectric layer is set up between the electrode and the source region. The method of operating the one-time programmable read only memory includes performing a programming operation to write a digital data value of ‘1’ into the memory and performing a programming operation to write a digital data value of ‘0’ into the memory.

Abstract: An integrated circuit includes a memory element and a circuit. The circuit is configured to program the memory element by applying one or more pulses to the memory element until a sensed resistance of the memory element is within a range of a desired resistance. The one or more pulses have a parameter value that is modified for each subsequent pulse based on the parameter value for an immediately preceding pulse and on a difference between the sensed resistance of the memory element and the desired resistance.

Abstract: An integrated circuit includes a first electrode, a second electrode, and resistivity changing material between the first electrode and the second electrode. The integrated circuit includes a contact contacting a bottom and a first sidewall portion of the first electrode.

Abstract: An integrated circuit includes a first electrode including at least two electrode material layers and a resistivity changing material including a first portion and a second portion. The first portion contacts the first electrode and has a same cross-sectional width as the first electrode. The second portion has a greater cross-sectional width than the first portion. The integrated circuit includes a second electrode coupled to the resistivity changing material.

Abstract: A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a silicon, germanium or silicon-germanium diode, doping the diode with at least one of nitrogen or carbon, and forming a second electrode over the at least one nonvolatile memory cell.

Abstract: A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell including a diode and a metal oxide antifuse dielectric layer over the first electrode, and forming a second electrode over the at least one nonvolatile memory cell. In use, the diode acts as a read/write element of the nonvolatile memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.

Abstract: Disclosed is a memory element array comprising a plurality of memory elements arranged in an array, wherein the memory elements are switching elements each including a gap of nanometer order in which a switching phenomenon of resistance is caused by applying a predetermined voltage between electrodes, and the memory element array is provided with tunnel elements respectively connected to the switching elements in series, each of the tunnel elements preventing generation of a sneak path current flowing to another switching element at a time of applying the predetermined voltage.

Abstract: A path routing from a write current source supplying a write current through an internal data line, a bit line and a source line to a reference potential except a memory cell is configured to have a constant resistance independent of a memory cell position selected in a memory array, and each of the resistance value of the current path between the memory cell and the write current source and the resistance value of the current path between the selected memory cell and the reference potential node is set to 500? or lower. A nonvolatile semiconductor memory device having improved reliability of data read/write is achieved.

Abstract: A method for operating a static random access memory (SRAM) cell includes providing the SRAM cell having a static read margin and a static write margin, wherein the static read margin is greater than the static write margin; applying a dynamic power to perform a write operation on the SRAM cell; and applying a static power to perform a read operation on the SRAM cell.

Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

Abstract: The invention relates to a Magnetic memory system (1, 20) which comprises an information layer (13) and a sensor (2, 22) for cooperating with the information layer (13). The information layer (13) comprises a pattern of magnetic bits (4a, 4b, 4c, 4d, 24a, 24c, 24d) which constitutes an array of bit locations. A bit magnetic field (3a, 3b, 3c, 3d) at a bit location represents a logical value (LO, L1/2, L1). The sensor (2, 22) comprises a magnetoresistive element (6, 26) comprising a fixed magnetic layer (7) and a free magnetic layer (8). The free magnetic layer (8) has a magnetization axis (10) along which the free magnetic layer retains a free magnetization direction (1 Ib, 1 Ic, 21b, 21c).

Abstract: A memory includes a memory array and a read control circuit configured to effectuate a read operation of a memory cell in the array. The read control circuit is configured so that the read operation contemplates one or more drift conditions associated with the memory cell. A method of reading a memory cell is also disclosed and includes detecting one or more drift conditions of a memory cell, and setting one or more read reference levels based on the one or more detected drift conditions. The memory cell is then read using the set one or more read reference levels.

Abstract: A sensing circuit of a phase change memory. The sensing circuit comprises a data current source and a reference current source, a storage memory device and a reference memory device, a storage switch and a reference switch, an auxiliary current source and a comparator. First terminals of the storage memory device and the reference memory device are respectively coupled to the data current source and the reference current source. The storage switch and the reference switch are respectively coupled to second terminals of the storage memory device and the reference memory device. The auxiliary current source is dynamically coupled to the first terminals of the storage memory device and the reference memory device. The comparator is coupled to the first terminals of the storage memory device and the reference memory device.

Abstract: In a method of controlling resistance drift in a memory cell of a resistance-changeable material memory device, the resistance changeable material in the memory cell is treated so that a drift parameter for the memory cell is less than about 0.18, wherein a change in resistance of a memory cell over the time period is determined according to the relationship: Rdrift=Rinitial×t?; where Rdrift represents a final resistance of the memory cell following the time period, Rinitial represents the initial resistance of the memory cell following the programming operation, t represents the time period; and ? represents the drift parameter.

Abstract: An electronic circuit comprises a memory matrix (60) with rows and columns of memory cells (16). First row conductors (10, 12) are provided for each of the rows. Second row conductors (12) are provided for successively overlapping pairs of adjacent rows. Column conductors (14) are provided for each of the columns. Each of the memory cells (16) comprises an access transistor (160), a node (166) and a first and second resistive memory element (162, 164). The access transistor (160) is preferably a vertical transistor having a control electrode coupled to the first row conductor (10) of the row of the memory cell (16), a main current channel coupled between the column conductor (14) for the column of the memory cell (160) and the node (166). The first and second resistive memory element (162, 164) are coupled between the node (166) and the second row conductors (12) for the pairs of rows to which the memory cell belongs.

Abstract: A phase change memory device comprises: a phase change element for rewritably storing data by changing a resistance state; a memory cell arranged at an intersection of a word line and a bit line and formed of the phase change element and a diode connected in series; a select transistor formed in a diffusion layer below the memory cell, for selectively controlling electric connection between an anode of the diode and a ground line in response to a potential of the word line connected to a gate; and a precharge circuit for precharging the diffusion layer below the memory cell corresponding to a non-selected word line to a predetermined voltage and for disconnecting the diffusion layer below the memory cell corresponding to a selected word line from the predetermined voltage.

Abstract: A semiconductor memory device may have a lower leakage current and/or higher reliability, e.g., a longer retention time and/or a shorter refresh time. The device may include a switching device and a capacitor. A source of the switching device may be connected to a first end of a metal-insulator transition film resistor, and at least one electrode of the capacitor may be connected to a second end of the metal-insulator transition film resistor. The metal-insulator transition film resistor may transition between an insulator and a conductor according to a voltage supplied to the first and second ends thereof.

Abstract: A nonvolatile memory device includes at least one nonvolatile memory cell which comprises a silicon, germanium or silicon-germanium diode which is doped with at least one of carbon or nitrogen in a concentration greater than an unavoidable impurity level concentration.

Abstract: A nonvolatile memory device includes at least one memory cell which comprises a diode and a metal oxide antifuse dielectric layer, and a first electrode and a second electrode electrically contacting the at least one memory cell. In use, the diode acts as a read/write element of the memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.

Abstract: A memory unit is provided herein. Two non-volatile devices are used to store a logic state of the memory unit into the non-volatile devices. Although a power supply for the memory unit is shut down, the non-volatile devices still keep the data stored therein. The present invention not only has an advantage of high speed operation of a static random access memory (SRAM), but also has a function for storing data of a non-volatile memory.

Abstract: A method for controlling non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as doped polysilicon between storage elements and their associated word lines, and providing contacts for the shield plates. The shield plates reduce electromagnetic coupling between floating gates of the storage elements, and can be used to optimize programming, read and erase operations. In one approach, the shield plates provide a field induced conductivity between storage elements in a NAND string during a sense operation so that source/drain implants are not needed in the substrate. In some control schemes, alternating high and low voltages are applied to the shield plates. In other control schemes, a common voltage is applied to the shield plates.

Abstract: Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write channel convert the digital bit patterns to analog data signals to be stored in a memory array at a particular bit capacity level in order to achieve a desired level of reliability.

Abstract: A method of sensing data in a multi-level cell memory using two or less sense operations and adjusting column load is provided. A sensing circuit implementing a serial-parallel sense scheme is also provided. The column loads are re-configurable based on the sensing circuit and the serial-parallel sense scheme.

Abstract: According to some embodiments, a method and apparatus for program verify sensing disclosed. During a program verify sensing operation, a tracking signal may be generated to match a sense amplifier signal. A data stream from a sequence generator may be held at a pass/hold logic until the tracking signal reaches a trip point. The data stream may be subsequently latched at a main latch with the sense amplifier signal.

Abstract: A memory system includes a first block in which data is stored with a low density and a second block in which data is stored with a high density. When data is received it is written to the first block, and in parallel some of the data is written to the second block, so that the second block is partially programmed. The second block is later fully programmed by copying additional data from the first block.

Abstract: A memory system includes a first block in which data is stored with a low density and a second block in which data is stored with a high density. When data is received it is written to the first block, and in parallel some of the data is written to the second block, so that the second block is partially programmed. The second block is later fully programmed by copying additional data from the first block.

Abstract: A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are proximate the row to be programmed. In one example of the invention, after the row has been programmed, the proximate cells are verified by read, comparison, and, if necessary, reprogramming operations to compensate for charge added to proximate memory cells resulting from programming the row. In another example of the invention, a row of memory cells is programmed with charge levels that take into account the charge that will be added to the memory cells when proximate memory cells are subsequently programmed.

Abstract: A non volatile memory device and method of operating including providing a verification voltage to a gate of a selected memory cell within multiple memory cells and providing a first pass voltage to a gate of a non-selected memory cell within the memory cells during a program verification operation; and providing a read voltage to the gate of the selected memory cell and providing a second pass voltage to the gate of the non-selected memory cell during a read operation. The second pass voltage is greater than the first pass voltage.

Abstract: There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash memory device can also include a judgment circuit for storing multi-bit/single-bit information indicating whether each of the memory blocks is a multi-bit memory block or not, determining whether or not a memory block of an inputted block address is a multi-bit memory block according to the stored multi-bit/single-bit information and outputting an appropriate flag signal. A read/write circuit for selectively performing multi-bit and single-bit read/program operations of the memory block corresponding to the block address is also included, as well as control logic for controlling the read/write circuit such that the read/write circuit can perform multi-bit or single-bit read/program operations based on the flag signal.

Abstract: Provided is a method of programming a memory device. The method includes performing a program voltage applying operation; and performing a verifying operation, wherein a plurality of verifying operations are consecutively performed after a program voltage applying operation.

Abstract: A nonvolatile storage device having a memory cell array composed of a plurality of memory cells. The plurality of memory cells include a bit line to which the drain terminals of the plurality of memory cells that have noncovalent connected gate terminals are commonly connected and a source line to which the source terminals of the plurality of memory cells that have commonly connected gate terminals are commonly connected and which extend perpendicularly to the bit line. The memory cell also includes a first source selector switch for connecting the source line to a source bias line.

Abstract: Methods and memory systems are provided that can detect bit errors due to read disturbances. A main page of a flash memory in a memory system is read. A bit error in data that is read from the main page is detected and corrected. In parallel with reading the main page, a bit error is detected in data that is read from a dummy page of the flash memory.

Abstract: The present invention discloses a storage device and a circuit element switching method thereof. The storage device includes: a plurality of memory modules, wherein each of the plurality of memory modules includes a plurality of chip enable terminals; a memory control unit that includes a plurality of bank selection terminals; and a switch module that is coupled between the plurality of memory modules and the memory control unit, and utilized for dispersedly coupling the plurality of bank selection terminals to the plurality of chip enable terminals of each of the plurality of memory modules. The circuit element switching method applied to the storage device includes: providing a memory control unit including a plurality of bank selection terminals; and dispersedly coupling the plurality of bank selection terminals to a plurality of chip enable terminals of each of the plurality of memory modules.

Abstract: Provided are a semiconductor device having a block state confirmation cell that may store information indicating the number of data bits written to a plurality of memory cells, a method of reading memory data based on the number of the data bits written, and/or a memory programming method of storing the information indicating the number of the data bits written. The semiconductor device may include one or more memory blocks and a controller. Each of the memory blocks may include a plurality of memory cells each storing data, and a block state confirmation cell storing information indicating the number of data bits written to the memory cells. The controller may read the data bits from the memory blocks based on the number of data bits, which is indicated in the information in the block state confirmation cell.

Abstract: An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between a corresponding wordline enable signal line and a corresponding wordline are controlled by an output of a block selection circuit. The transfer transistors include a dummy transfer transistor electrically coupled to the dummy memory cell, and configured to transmit a dummy wordline enable signal.

Abstract: In a semiconductor device, a first transistor of an SOI structure has a source region, a drain region, a body region positioned between the source region and the drain region, and a gate electrode positioned above the body region. A first capacitor of the SOI structure has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal. The semiconductor device stores data in a nonvolatile manner in accordance with carriers accumulated in a first node electrically connecting the gate electrode of the first transistor and the first terminal of the first capacitor.

Abstract: A non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as doped polysilicon between storage elements and their associated word lines, and providing contacts for the shield plates. The shield plates reduce electromagnetic coupling between floating gates of the storage elements, and can be used to optimize programming, read and erase operations. In one approach, the shield plates provide a field induced conductivity between storage elements in a NAND string during a sense operation so that source/drain implants are not needed in the substrate. In some control schemes, alternating high and low voltages are applied to the shield plates. In other control schemes, a common voltage is applied to the shield plates.

Abstract: Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate, and a third gate, e.g., a control gate, a back gate, and a floating gate, as a memory in logic cell. The method includes programming the floating gate to a first state to cause the memory in logic cell to operate as a first logic gate type. The method further includes programming the floating gate to a second state to cause the memory in logic cell to operate as a second logic gate type.

Abstract: When performing a data sensing operation, including a verify operation during programming of non-volatile storage elements (or, in some cases, during a read operation after programming), a first voltage is used for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation. In some embodiments, the second voltage is lower than the first voltage.

Abstract: Systems and methodologies are provided herein for increasing operation speed uniformity in a flash memory device. Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance of the memory cell from an edge of the memory array increases. This difference in distributed substrate resistance can vary voltages supplied to different memory cells in the memory array depending on their location, which can in turn cause non-uniformity in the speed of high voltage operations on the memory array such as programming. The systems and methodologies provided herein reduce this non-uniformity in operation speed by providing compensated voltage levels to memory cells in a memory array based at least in part on the location of each respective memory cell.

Abstract: A nonvolatile memory device is provided. The nonvolatile memory device includes a semiconductor substrate and memory cell units arranged in a matrix on the semiconductor substrate. Each of the memory cell units includes a tunnel insulation layer on the semiconductor substrate. A first memory gate and a second memory gate are disposed on the tunnel insulation layer. An isolation gate is disposed between the first and second memory gates. A word line covers the first memory gate, the second memory gate and the isolation gate. A method of forming the nonvolatile memory device is also provided.

Abstract: To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached. At that point, the magnitude of the programming pulses stops increasing and the programming pulses are applied in a manner to provide varying time duration of the programming signal between verification operations. In one embodiment, for example, after the pulses reach the maximum magnitude the pulse widths are increased. In another embodiment, after the pulses reach the maximum magnitude multiple program pulses are applied between verification operations.

Abstract: To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached. At that point, the magnitude of the programming pulses stops increasing and the programming pulses are applied in a manner to provide varying time duration of the programming signal between verification operations. In one embodiment, for example, after the pulses reach the maximum magnitude the pulse widths are increased. In another embodiment, after the pulses reach the maximum magnitude multiple program pulses are applied between verification operations.

Abstract: A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor; a first voltage drop circuit configured to reduce an applied read voltage during a read operation; a second voltage drop circuit configured to reduce the applied read voltage; a string select line driver circuit configured to drive the string select line with the reduced voltage provided by the first voltage drop circuit; and a ground select line driver circuit configured to drive a ground select line with the reduced voltage provided by the second voltage drop circuit.