Abstract: An auxiliary cooling device includes two side boards with a space defined therebetween and the existed memory chips and the cooling plates on two sides of the memory chips are received in the space. A cooling fan is connected between the two side boards and sends air flows toward the memory chips and the cooling plates to remove heat via air paths defined in the inside of each side board.

Abstract: An apparatus includes a microchannel structure having microchannels formed therein. The microchannels are to transport a coolant and to be proximate to an integrated circuit to transfer heat from the integrated circuit to the coolant. The apparatus also includes a plurality of walls coupled to the microchannel structure to define a manifold. The manifold is in communication with at least a plurality of the microchannels. The plurality of walls includes a side wall. The side wall has a port therein. The port allows the coolant to flow in a direction that is either into the manifold or out of the manifold.

Abstract: An utility meter is provided. The meter includes a base and a first barrier operably associated with the base. The base and the first barrier define a first compartment between the base and the first barrier. The meter also includes a heat generating component positioned in the first compartment and operably associated with the base. The meter also includes a second barrier extending from the base. The second barrier and the first barrier define a second compartment between the second barrier and the first barrier. The meter further includes an arrangement for moving heat connected to the heat generating component and extending from the first compartment to the second compartment.

Abstract: A heat sink retention module including a frame, first and second wire modules and a latch. The frame receives a heat sink base and is securable to a circuit board. First and second wire modules each include a pair of arm sections pivotally coupled to opposing sides of the frame about a transverse axis, a transverse handle section, and a spring clip formed adjacent the pivoting end of each arm section. The transverse axis of the first wire module is longitudinally spaced apart from the transverse axis of the second wire module. When the wire modules are adducted and flexed, a generally downward force is applied to the heat sink base by the spring clips, which extend generally perpendicular to each arm section. The wire modules are kept in the adducted position by a latch selectively securable between the transverse handle sections of the first and second wire modules.

Abstract: In some embodiments, a heatsink includes a thermally conductive core and at least ten thermally conductive fins extending quasi-radially from the thermally conductive core, wherein most of the fins are of uniform length, and wherein at least a portion of the thermally conductive core is shaped such that the fins having uniform length form a substantially rectangular cross sectional form factor. Other embodiments are disclosed and claimed.

Abstract: A wired circuit board that can prevent inconsistency in characteristic impedance to allow effective transmission of electrical signals from a magnetic head to a control board portion. A wired circuit board is constructed so that a suspension board portion for supporting the magnetic head and a control board portion for controlling the magnetic head are formed to be continuous and integral with each other. To be more specific, a first conductor layer connected to the magnetic head in the suspension board portion and a second conductor layer connected to a preamplifier IC in the control board portion are formed from the same material and formed on a common insulating base layer simultaneously. Further, a common insulating cover layer to cover the first conductor layer and the second conductor layer is formed on the common insulating base layer.

Abstract: In one aspect, an electronic assembly includes an interconnection substrate, a component, and a discontinuity compensator. The interconnection substrate includes a signal conductor and a ground conductor. The component includes a device having a signal line and a ground conductor, a package, and a signal lead. The signal lead is electrically coupled to an internal signal path of the package and has an external portion extending from the package to the signal conductor of the interconnection substrate. The discontinuity compensator electrically couples a ground path of the package to the ground conductor of the interconnection substrate. The discontinuity compensator includes an electrically conducting planar surface that is oriented in a plane intersecting the interconnection substrate and forms with at least a substantial part of the external portion of the signal lead a transmission line structure having an impedance substantially matching the nominal impedance over the specified bandwidth.

Abstract: An electronic device includes: a circuit board having a convex-curved component and a housing having a support member with a concave-curved end and receiving the convex-curved component of the circuit board. The convex-curved component is freely turnable in the concave-curved end. Thereby, a simple structure prevents moments from being transmitted to the circuit board from a housing.

Abstract: A regulator may include a load voltage sensing circuit configured to generate a feedback signal representative of output voltage from an isolated flyback converter. The regulator may include a pulse generator configured to controllably generate the pulses and to increase at least one off time and at least one period of the pulses after a load on the flyback converter decreases.

Abstract: A detection circuit for detecting the demagnetizing time of a magnetic device is provided. An input circuit is coupled to the magnetic device for detecting a magnetizing voltage and a demagnetizing voltage of the magnetic device. A control circuit is coupled to the input circuit for generating a demagnetizing-time signal in response to the magnetizing voltage, the demagnetizing voltage, and a magnetizing time. The magnetizing time is correlated to the enable period of the magnetizing voltage. The demagnetizing time of the magnetic device is represented by the demagnetizing-time signal.

Abstract: A DC-to-DC converter having a transformer with a primary and a tapped secondary, two serial output filter inductors connected parallel with the secondary, a center output filter inductor connected between the secondary tap and serial output inductors, two serially connected switches connected in parallel with the two output inductors for receiving a signal to control operation of the switches during steady state and an output load connected between the serial connection of the serial output inductors and serial switching devices. The transformer primary side connected with double-ended primary-side topologies. The transformer secondary and output filers configured to form a current tripler rectifier, current quadtupler rectifier or current N-tuper rectifier.

Abstract: A converter includes a converter circuit 1 having a plurality of bridge-connected semiconductor switching devices for converting AC power into DC power, a smoothing condenser connected in parallel to the DC side of the converter circuit and a current detector provided in a condenser circuit to control a condenser current flowing through the smoothing condenser to be a set value. The condenser current is controlled to be the set value (e.g. zero) to thereby reduce the capacity of the smoothing condenser and make the converter small.

Abstract: Methods and apparatus are provided for reducing voltage distortion effects at low speed operation in electric drives. The method comprises receiving a first signal having a duty cycle with a range between minimum and maximum achievable duty cycles, producing a second duty cycle based on the minimum achievable duty cycle if the duty cycle is within a distortion range and less than a first clipping value, producing a second duty cycle based on the closer of minimum and maximum pulse widths if the duty cycle is within the distortion range and between the first and a second clipping value, producing a second duty cycle based on the maximum achievable duty cycle if the duty cycle is within the distortion range and greater than the second clipping value, and transmitting a second signal to the voltage source inverter having the second duty cycle.

Abstract: A switch power supply with standby function is disclosed. The power supply can satisfy the need of the green environment protection. And a single ended green switch power supply IC or thick film or modular circuit design with standby function is disclosed, too. It comprises a standby power supply, a main power supply, a PFC device, and a supplemental circuit, wherein a remote control signal is transmitted to main control circuit in response to a main error signal to control main power supply. A method for preventing switch power current from overload and saturation is disclosed too. Finally, the present invention also provides a green power supply with standby function as well as its IC associated with digital processing highly qualified PFC, and a PC standard (such as ATX, ATX12, SSI) computer switch power supply.

Abstract: A multiplicity of synchronized inverters for driving a multiplicity of loads such as CCFLs that require high ac voltages are arranged in close proximity of the respective loads and controlled in phase. A frequency determination capacitor and a frequency determination resistor are connected to one of the inverters to generate a triangular wave signal and a clock signal. The triangular wave signal and clock signal thus generated are supplied to other inverters to synchronize all the loads so that they can be controlled in phase. The resistance of the frequency determination resistor is set to a substantially small magnitude at the time of startup to increase the frequency of the triangular wave signal, thereby enabling quick startup of the loads.

Abstract: The systems and methods described herein provide for a universal controller capable of controlling multiple types of three phase, two and three level power converters. The universal controller is capable of controlling the power converter in any quadrant of the PQ domain. The universal controller can include a region selection unit, an input selection unit, a reference signal source unit and a control core. The control core can be implemented using one-cycle control, average current mode control, current mode control or sliding mode control and the like. The controller can be configured to control different types of power converters by adjusting the reference signal source. Also provided are multiple modulation methods for controlling the power converter.

Abstract: An apparatus and method of switching a switch of a power supply are disclosed. According to aspects of the present invention, a method includes controlling a switch of a switching power supply to switch on and off within a switching cycle. The switching cycle has a substantially fixed period. One group of consecutive switching cycles is separated from a next group of consecutive switching cycles by a time of no switching. Each group of consecutive switching cycles has at least a predetermined minimum of two or more switching cycles. The time of no switching is adjusted in a closed loop to regulate an output of the switching power supply.

Abstract: Disclosed is a method and apparatus that includes a power supply having a primary coil and a secondary coil. The secondary coil generates an output voltage and a feedback voltage related to the output voltage. The feedback voltage is sampled at a time instant that is digitally controllable. The output voltage is determined from the feedback voltage.

Abstract: Disclosed is an electric circuit, in particular for a medium voltage power converter. The circuit has at least four semiconductor switches which form a series connection and which are connected to poles of a direct current voltage (Ud). A diode is connected in parallel in an inverse direction to each semiconductor switch. A capacitor is connected in parallel to the two semiconductors in the middle of the series connection. The circuit is provided with a pole of an output potential (Ua) which is connected centrally in the series connection. The circuit has a control device for successively controlling the semiconductor switches. The time interval between the transition of two of the semiconductor switches into their respective controlling states is minimal.

Abstract: A DC to DC converter having improved transient response, accuracy, and stability. The DC to DC converter includes a comparator configured to compare a reference signal with a second signal. The reference signal has a DC offset determined, at least in part, by a DC reference voltage source. The second signal is representative of an output voltage of the DC to DC converter. The comparator is further configured to provide a control signal to a driver that drives the output voltage of the DC to DC converter in response to a comparison of the reference and second signal. The DC to DC converter further includes an accuracy circuit to enhance accuracy of the DC to DC converter. The DC to DC converter may further include a stability circuit to enhance stability of the DC to DC converter.

Abstract: An inverter type drive unit for feeding AC electric power of variable parameters to an electric motor has an electronic control section, and a power converting and output section which includes one or more identical power modules, each forming a complete 3-phase output stage. The power modules are arranged side-by-side in a multiplying direction and are clamped by retaining devices to a cooling structure. The power modules are connected in parallel to DC input terminals and to AC output terminals via conductive sheets which are insulated from each other. The DC connected conductive sheets cover substantially the entire physical surface area covered by the power modules so as to accomplish an even, simultaneous and low impedance DC current supply to all power modules.

Abstract: An integrated circuit has been described that includes a user programmable identification code register. The register can be programmed by the user to emulate other integrated circuit devices. The integrated circuit register can also be reset to reflect the original manufacturer information. The integrated circuit can be a memory device and allows the user to upgrade a system while indicating to the original system that the device is compatible.

Abstract: A novel match/mismatch emulation scheme for an addressed location in a CAM system that includes a plurality of CAM blocks. The plurality of CAM blocks are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of CAM cells and associated read/write bit lines connecting the group of CAM cells to an addressed search circuit. During debug mode, where the individual array cells do not participate in search, all the cells in the debug column behave the same way to emulate a match/mismatch on all words. The circuit provides a control input to include address evaluation of a debug cell in a row. The circuit also provides simultaneous switching noise analysis on an evaluating row. The resulting CAM cell provides a circuit to test individual rows for defects and noise analysis.

Abstract: A content addressable memory array includes a plurality of rows of active CAM cells electrically coupled to a corresponding plurality of active match lines and at least one row of dummy cells, which are configured to generate an always-match condition on a dummy match line when the CAM array is undergoing a search operation. A match line pull-up circuit is provided. This match line pull-up circuit is electrically coupled to the plurality of active match lines and the dummy match line. The pull-up circuit is responsive to a calibration control signal that sets a pull-up strength of the match line pull-up circuit when the CAM array is undergoing the search operation. A sense amplifier, which is coupled to the match lines, includes a control circuit configured to adjust the calibration control signal in response to evaluating a first voltage on the dummy match line relative to a reference voltage.

Abstract: A memory module, system and method of making the same includes a memory module including a plurality of memory devices having a first portion of memory devices cooperatively forming a first rank of memory devices and a second portion of memory devices cooperatively forming a second rank of memory devices. The first and second portions of memory devices are grouped into a plurality of memory device stacks, wherein each of the plurality of memory device stacks includes at least one of the plurality of memory devices coupled to a first portion of the plurality of DQ signals and at least another one of the plurality of memory devices coupled to a different second portion of the plurality of DQ signals.

Abstract: A method and system for a high current semiconductor memory cell provides a semiconductor memory cell with two current carrying structures. At least one of the current carrying structures is segmented and formed of narrow wire segments from one or more levels coupled to wider connective squares of another level. The wire segments may be a conductive material and the connective squares a refractory material. The short length wire segments may include a length less than the average grain size of the material of which they are formed.

Abstract: A semiconductor memory structure based on gate oxide break down is constructed in a deep N-well. Thus, the electrical field over the programmable element during the transient procedure of gate oxide break down can be controlled to achieve the best memory programming results. The conductivity of the programmed memory cell is increased greatly and conductivity variation between the memory cells is reduced. This is achieved by adding a body bias during the programming process. The body here refers to a P-well formed within the deep N-Well. Furthermore, the read voltage offset is reduced greatly with this new memory configuration. These improved programming results will allow faster read speed and lower read voltage. This new structure also reduces current leakage from a memory array during programming.

Abstract: Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are significantly reduced. In some embodiments, after a short read cycle, the content of the memory cell is latched and maintained as long as the subsequent read attempts are directed to the same memory cell. In these embodiments the read cycle need only be long enough to latch the memory content of the cell, and as long as the subsequent read attempts target the same memory cell the latched value will be used instead of repeating the read process.

Abstract: To greatly increase the storage density of a storage apparatus, an electron beam E emitted from a cold cathode 101 is accelerated by an accelerating electrode 102, caused to converge by a convergence electrode 103, deflected by a deflection electrode 104 and applied to a minute region of a storage film 105. The storage film 105 includes, for example, a phase change film 105a. The film is rapidly heated and cooled to change into an amorphous state upon irradiation with an electron beam E with high energy, while being gradually cooled to change into a crystallized state upon irradiation with an electron beam E with approximately intermediate energy, thereby storing data. Upon irradiation with an electron beam E with low energy, the potential difference between a detection electrode 105b and an anode 105c is detected depending on the state, i.e., the amorphous or crystallized state, thereby reading stored data.

Abstract: A storage device includes a memory cell having a storage element having a characteristic of changing from a state of a high resistance value to a state of a low resistance value by being supplied with a voltage equal to or higher than a first threshold voltage, and changing from a state of a low resistance value to a state of a high resistance value by being supplied with a voltage equal to or higher than a second threshold voltage different in polarity from the first threshold voltage, and a circuit element connected in series with the storage element, wherein letting R be a resistance value of the storage element after writing, V be the second threshold voltage, and I be a current that can be passed through the storage element at a time of erasure, R?V/I.

Abstract: Disclosed are embodiments of a method and apparatus for avoiding cell data destruction caused by cell stability problems in static random access memory (SRAM) cells. In one embodiment, data inside of an SRAM cell is transferred to one of its bitline in advance of an actual Read/Write operation utilizing a transfer device controlled by a pre-read signal. In one embodiment, the read and write bitlines are shared and the transfer device and pr are not needed. Since the bitline voltage has already been changed to the state which reflects the cell data in advance, the memory cells remains relatively stable. By shifting the bitline voltage before the wordline is turned on, the accessed cell is relieved from the stress which would have otherwise caused cell stability problems.

Abstract: Source contacts of driver transistors are short-circuited through the use of an internal metal line within a memory cell. This metal line is isolated from memory cells in an adjacent column and extends in a zigzag form in a direction of the columns of memory cells. Individual lines for transmitting the source voltage of driver transistors can be provided for each column, and the source voltage of driver transistors can be adjusted also in units of memory cell columns in the structure of single port memory cell.

Abstract: An embodiment of the present invention is an SRAM memory array comprising memory cells with each cell containing six devices, the storage nodes which store the true and complement of the data are constructed from a four device, cross coupled flip-flop cell, wherein one internal storage node of this cell is connected through an access pass gate to one local bit line (LBL), the second internal storage node connected in a like manner to a second LBL, each LBL connected to a limited number, e.g. 8 to 32 of other similar storage cells, the two LBLs each connected to the gate of a separate read head nFET for discharging to ground one of two previously precharged global read lines so as to pass the inverse of the signal on the LBL and thus on the read head gate to a global read/write bit line.

Abstract: A memory cell array includes memory cells, bit lines running along a first direction, word lines running along a second direction perpendicular to the first direction, and continuous active area lines, wherein transistors are at least partially formed in the active area lines. The transistors electrically couple corresponding memory cells to corresponding bit lines via bit line contacts, and the transistors are addressed by the word lines. The bit line contacts are formed in a region generally defined by an intersection of a bit line and a corresponding active area line. Neighboring bit line contacts which are connected with one active area line are connected with neighboring bit lines. Consequently, one active area line is crossed by a plurality of bit lines.

Abstract: An integrated circuit (IC) is provided that includes at least one static random access memory (SRAM) cell wherein performance of the SRAM cell is enhanced, yet with good stability and writability. In particular, the present invention provides an IC including at least one SRAM cell wherein the gamma ratio is about 1 or greater. The gamma ratio is increased with degraded pFET device performance. Morever, in the inventive IC there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides an integrated circuit (IC) that comprises at least one SRAM cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the nFET and the pFET.

Abstract: A semiconductor memory device includes a write line, at least three first data-writing circuits which are connected to the write line, and memory cells which include a magnetoresistive element, are connected electrically and/or magnetically to the write line, and are arranged between the first data-writing circuits.

Abstract: A magnetoresistance effect element is also located between second wiring and common wiring. The magnetoresistance effect element is electrically connected to the second wiring without a spin filter. When a reading current is supplied between the second wiring for supplying a reading current and the common wiring, since this is not supplied via a spin filter, no spin polarized current is supplied into the magnetoresistance effect element, so that it becomes difficult to magnetization-reverse a magnetosensitive layer. Even in a structure where, in order to improve recording density, the magnetosensitive layer is reduced in area so as to lower a writing current, no magnetization reversal occurs due to a supply of the reading current, and information can be read out without making the reading current considerably small in comparison with the writing current.

Abstract: The direction of magnetization of a reading ferromagnetic material 5R forming a spin filter when reading is the same as that of a pinned layer 1. In this case, a torque that works on the spin of a free layer 3 due to a spin polarized current becomes “zero.” When the element size is made small so as to improve the integration degree of the magnetic memory, according to the scaling law, the writing current can be made small. In the present invention, the resistance to the spin injection magnetization reversal due to a reading current is high, so that the magnitude of the writing current can be lowered.

Abstract: An analog memory may be formed using a phase change material. The phase change material may assume one of a number of resistance states which defines a specific analog characteristic to be stored.

Abstract: A phase change memory device includes a memory cell having a phase change material, a write driver adapted to supply a program current to the memory cell during a programming interval, and a pump circuit adapted to enhance a current supply capacity of the write driver during the programming interval. The pump circuit is activated prior to the programming interval in response to an external control signal.

Abstract: A non-volatile memory latch may be formed with a phase change memory layer. Such a latch may be faster and more easily integrated into main stream semiconductor processes than conventional latches that use non-volatile memory elements such as flash memory.

Abstract: A thermally insulated memory device includes a memory cell, the memory cell having electrodes with a via extending therebetween, a thermal insulator within the via and defining a void extending between the electrode surfaces. A memory material, such as a phase change material, is within the void and electrically couples the electrodes to create a memory material element. The thermal insulator helps to reduce the power required to operate the memory material element. An electrode may contact the outer surface of a plug to accommodate any imperfections, such as the void-type imperfections, at the plug surface. Methods for making the device and accommodating plug surface imperfections are also disclosed.

Abstract: Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data. The very long write-1 time may require wait states. To eliminate wait states for sequential accesses, the PCM cells are divided into 16 banks. Each bank has its own bank write latch that stores data locally at the bank while the bank is being written. Data lines to the banks are freed up to transfer data to other banks once the data is written into the local bank write latch, allowing the long set-current pulse to be applied locally to slowly grow crystals in the alloy resistors. External host data are buffered and applied to the data lines by an array data mux.

Abstract: Read disturbs in phase change memories may be reduced by progressively reducing the read pulse falling edges. This may reduce the possibility of quenching and inadvertent amorphization of at least a portion of the bit. As a result, in some embodiments, read disturbs may be reduced.

Abstract: A semiconductor storage device comprising: unit blocks each including memory cells, first row of sense amplifiers on one side of bit lines; second row of sense amplifiers on an other side of the bit lines; first switch means which switches a connection state between the one side of the bit lines and the first row of sense amplifiers; second switch means which switches a connection state between the other side of the bit lines and the second row of sense amplifiers; third switch means arranged in the approximate center of the bit lines in an extending direction thereof to switch a connection state of the bit lines; and refresh control means which divides the unit block into two areas and controls the refresh operation using the switch means and the row of sense amplifiers according to which area a selected word line to be refreshed is in.

Abstract: In a memory cell array, a plurality of memory cells are arranged in a matrix. Each of the plurality of memory cells stores one of a plurality of threshold levels. When writing one of the plurality of threshold levels into a first memory cell of the memory cell array, a control circuit writes a threshold level a little lower than the original threshold level. When not writing a second memory cell adjacent to the first memory cell consecutively, the control circuit writes the original threshold level into the first memory cell.

Abstract: An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.

Abstract: A method for preventing a memory from generating a leakage current is disclosed. The memory includes a boundary memory cell and a neighboring memory cell. The neighboring memory cell is adjacent to the boundary memory cell. The method includes the following step. The first terminal of the neighboring memory cell is connected to the second terminal through a metal line.

Abstract: The read reference of a nonvolatile memory integrated circuit is changed in response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command.

Abstract: Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.