Abstract: Methods of manufacturing a nitride trapping EEPROM flash memory are described where each memory cell uses Si-Fin to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in a row of nitride trapping memory cells is used to produce the inversion region that acts as a source region or a drain region for transferring of a required voltage, which conserves the density of a memory cell given that the source region and the drain region for each memory cell are not doped. The flash memory includes a plurality of polysilicon layers intersecting with a plurality of Si-Fin layers.

Abstract: A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word line are biased at a pass voltage that is less than the normal pass voltage. These unselected word lines are both located a predetermined distance from the selected word line. The remaining word lines are biased at the normal pass voltage.

Abstract: A low voltage of the order of or one to three volts instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero immediately adjacent to the source or drain side select gate of a NAND flash device to reduce or prevent the shifting of threshold voltage of the memory cells coupled to word line zero during the programming cycles of the different cells of the NAND strings. This may be implemented in any one of a variety of different self boosting schemes including erased areas self boosting and local self boosting schemes. In a modified erased area self boosting scheme, low voltages are applied to two or more word lines on the source side of the selected word line to reduce band-to-band tunneling and to improve the isolation between two boosted channel regions.

Abstract: Bit line-to-bit line noise is discharged in a NAND string prior to sensing a programming condition of a selected non-volatile storage element in the NAND string. A source voltage is applied which boosts the voltage in conductive NAND strings. The voltage boost results in capacitive coupling of noise to neighboring NAND strings. A current pull down device is used to discharge each NAND string prior to performing sensing. After each NAND string is coupled to a discharge path for a predetermined amount of time, bit lines of the NAND string are coupled to voltage sense components for sensing the programming condition of the selected non-volatile storage elements based on a potential of the bit lines. The selected non-volatile storage elements may have a negative threshold voltage. Further, a word line associated with the selected non-volatile storage elements may be set at ground.

Abstract: Multi-level cell memory devices comprise a charge trapping structure with an enlarged second bit operation window formed by hole injection through a gate electrode or substrate for producing multiple logic levels on each storage side of the charge trapping structure. A hole injection process is conducted through either a gate electrode or substrate to cause fringe-induced effect. Hole charges are stored in a charge trapping layer that intersects with a word line and the hole charges are stored along fringes of the word line. Each memory cell in the MLC memory device includes a total of 2 m bits with m bits for each side of the memory cell, a total of 2*2m multiple voltage threshold Vt distributions with 2m multiple voltage threshold Vt distributions for each side of the memory cell, and a total of 2*2m logic states with 2m logic states for each side of the memory cell.

Abstract: A memory includes a sense amplifier segment and a plurality of word lines including a first transfer word line and a second transfer word line complementary to the first transfer word line. The memory includes a plurality of bit lines coupled to the sense amplifier segment and a memory cell located at each cross point of each word line and each bit line. The first transfer word line and the second transfer word line are adapted for simultaneously inverting data bit values stored in memory cells along a failed word line to correct a parity error during self refresh.

Abstract: An array structure of single-level poly NMOS EEPROM memory cells and method of operating the array is discussed implemented in a higher density embedded EEPROM layout that eliminates the use of high voltage transistors from the array core region. If they are utilized, the high voltage transistors are moved to row and column drivers in the periphery region to increase array density with little or no added process complexity to allow economic implementation of larger embedded SLP EEPROM arrays. During program or erase operations of the array, the method provides a programming voltage for the selected memory cells of the array, and a half-write (e.g., mid-level) voltage to the remaining unselected memory cells to avoid disturbing the unselected memory cells of the array.

Abstract: A method programs a memory device that includes at least one memory cell matrix. The programming method the steps of: erasing the memory cells; soft programming the memory cells; and complete programming of a group of such memory cells each of them storing its own logic value. Advantageously, the first complete programming step of a group of such memory cells involves cells belonging to a block (A) of the matrix being electrically insulated from the rest of the matrix. A memory device suitable to implement the proposed method is also described.

Abstract: A system and method are disclosed for enhancing the performance of erase operations in CMOS compatible EEPROM memory cells. An EEPROM memory cell is described in which the erase voltage and the coupling ratio of the EEPROM memory cell are simultaneously decreased while maintaining the erase performance (e.g., erase speed) of the EEPROM memory cell. Significant improvement in the endurance of CMOS compatible EEPROM devices is obtained due to the enhanced erase performance of the EEPROM memory cells of the present invention.

Abstract: An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and the wordline control circuit selecting an identical wordline N times (N is an integer larger than one) from among the wordlines in one horizontal scan period of the display panel.

Abstract: A branch target buffer (BTB) storing a data entry related to a branch instruction is disclosed. The BTB conditionally enables access to the data entry in response to a word line gating circuit associated with a word line in the BTB. The word line gating circuit stores a word line gating value derived from branch history data related to the instruction. Additionally, a branch prediction unit and a processor incorporating the BTB are disclosed, along with methods for operating the BTB.

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.

Abstract: A method is provided for transferring data in a memory that includes memory cells forming memory pages, and a page buffer that includes a register, with signal lines selectively transferring data stored in the register to the memory cells of a selected one of the memory pages and an output interface of the memory. Data read from or to be written to the memory cells of the selected one of the memory pages is at least temporarily stored in the register, and outputs of the register are buffered so as to decouple the outputs of the register from the signal lines. The signal lines include bitlines that are each coupled to some of the memory cells and data lines that are coupled to the output interface of the memory. The buffering comprises selectively driving the bitlines or the data lines according to a data word that is stored in the register.

Abstract: A voltage generator and methods thereof are provided. The example voltage generator may include a voltage comparison block which generates an output voltage in response to a read command, the output voltage corresponding to a difference between a reference voltage and a determination voltage and a voltage generation block which outputs the determination voltage and a comparison voltage in response to the read command, an inverse read command having a phase opposite that of the read command, a switching pulse signal and the output voltage. A first example method may include outputting a determination voltage and a comparison voltage in response to a read command, an inverse read command having a phase opposite that of the read command, a switching pulse signal and an output voltage, the output voltage generated in response to the read command and corresponding to a difference between the reference voltage and the determination voltage.

Abstract: Disclosed herein are an internal voltage generation control circuit and an internal voltage generation circuit using the same.

Abstract: In a semiconductor memory, a sub bit line hierarchical switch is provided correspondingly to each sub bit line between the sub bit line and a main bit line corresponding to the sub bit line, and a complementary sub bit line hierarchical switch is provided correspondingly to each complementary sub bit line between the complementary sub bit line and a complementary main bit line corresponding to the complementary sub bit line. Furthermore, the semiconductor memory includes a hierarchical switch control unit for turning off all the sub bit line hierarchical switch and the complementary sub bit line hierarchical switch when a given signal is input.

Abstract: The flip-flop according to the invention serves for storing an item of logic state information and has at least one data input and at least one data output. The flip-flop comprises at least one latch stage for storing the state information if the flip-flop is switched on. Furthermore, the flip-flop according to the invention comprises at least one memory cell having a capacitance as storage element. In this case, the at least one memory cell serves for storing the state information if the flip-flop is switched off.

Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Abstract: A memory includes a plurality of memory cells, a sense amplifier coupled to at least one of the plurality of memory cells, a temperature dependent current generator comprising a plurality of selectable temperature dependent current sources for generating a temperature dependent current, a temperature independent current generator comprising a plurality of selectable temperature independent current sources for generating a temperature independent current, and a summer coupled to the temperature dependent current generator and the temperature independent current generator for combining the temperature dependent current and the temperature independent current to generate a reference current for use by the sense amplifier. A temperature coefficient of the reference current is approximately a same as a temperature coefficient of a memory cell current of at least one of the plurality of memory cells.

Abstract: Provided is a memory device capable of automatically controlling a self refresh cycle by sensing an ambient temperature, rather than setting Extended Mode Register Set (EMRS) code. The memory device includes a temperature sensing unit for generating a first voltage independent of a temperature variation and a second voltage dependent upon a temperature variation, a comparing unit for comparing the first voltage with the second voltage to provide a comparison result signal, and a self refresh signal generating unit for receiving a self refresh entry signal and generating a self refresh signal of temperature compensated cycle under the control of the comparison result signal.

Abstract: An integrated semiconductor memory that has at least one temperature measuring element and repeatedly carries out a temperature measurement during the operation of the semiconductor memory, wherein the semiconductor memory repeats the temperature measurement at instants corresponding to a measuring frequency of the temperature measuring element. According to an embodiment of the invention, the measuring frequency of the temperature measuring element is variable and the temperature measuring element is driven in such a way that the measuring frequency changes in a manner dependent on the temporal development of measured values of the repeated temperature measurements.

Abstract: A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.

Abstract: A semiconductor memory device is comprised of a refresh counter for sequentially generating a count value indicating one or more row addresses corresponding to one or more word lines to be refreshed when receiving a refresh request at a predetermined interval in normal operation, in which the refresh counter includes n+1 stage counters assigned to n bits included in the row address and a dummy bit not included in the row address, and a counter portion from the least significant bit to the dummy bit forms an N-ary counter, so as to control whether or not refresh is performed in response to a value of the dummy bit when receiving the refresh request.

Abstract: A core control circuit outputs operation control signals to a memory core in order to perform refresh operations in response to an internal refresh request from a refresh request generating circuit and an external refresh request. The core control circuit sets the number of memory cells each subjected to the refresh operation in response to the external refresh request larger than the number of memory cells each subjected to the refresh operations in response to the internal refresh request. By relatively increasing the number of memory cells each subjected to the refresh operation in response to one external refresh request, the number of external refresh requests required to refresh all memory cells can be reduced. Accordingly, the frequency with which the external refresh request is supplied to the semiconductor memory can be lowered, which can improve access efficiency.

Abstract: Dual port memory array circuitry is provided that includes bit line voltage clamping circuitry. The clamping circuitry contains control transistors that are used to enable and disable the clamping circuitry. The clamping circuitry also contains voltage regulator transistors and feedback paths. When a write operation is performed on one port of the dual port memory array while a read operation is being performed on the other port of the dual port memory array, the bit line voltage clamping circuitry prevents the voltages on the read port bit lines from dropping too low. This allows the write operation to be performed rapidly, even if the memory cell being written to has been adversely affected by variations due to process, voltage, and temperature.

Abstract: Semiconductor memory devices, block select decoding circuits and a method of activating a word line are provided. An example semiconductor memory device may include a plurality of memory banks. Each of the plurality of memory banks may include memory blocks which may be arranged in different addressable orders. If two edge memory blocks are activated in a given one of the plurality of memory banks, a non-edge memory block may be concurrently activated in at least one of remaining memory banks other than the given one memory bank. Accordingly, a number of concurrently activated memory blocks, a voltage required to enable a word line and noise may be reduced. The example semiconductor device may include the example block select decoding circuit, and likewise may perform the example method of activating a word line with an activation of a reduced number of memory blocks.

Abstract: Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.

Abstract: An acoustic logging system with a borehole tool comprising a transmitter assembly and an axially spaced receiver assembly. The transmitter and receiver assemblies are optionally rotatable with respect to each other, depending upon the embodiment of the logging system. The logging system is designed to measure, among other parameters, the velocity (or slowness) and amplitude of shear wave energy induced by the transmitter assembly within formation penetrated by the borehole. These parameters are extracted from full wave acoustic data responses of receiver elements comprising the receiver assembly, and are measured as a function of azimuth around the borehole. These parameters are subsequently used to determine anisotropic properties of the formation, such as the azimuthal direction of formation fracturing with respect to the well borehole. Optional rotation of the transmitter and receiver assemblies minimizes adverse effects of maintaining calibration and balance of multiple transmitters and receivers.

Abstract: An apparatus for range-estimating a noise source including a first passive, vertical hydrophone array of at least two receivers at a first distance from the noise source. The apparatus includes a second passive, vertical hydrophone array of at least two receivers at a second distance from the noise source. The apparatus also includes a processor communicating with the first passive, vertical hydrophone array and the second passive, vertical hydrophone array to determine a ratio of the first distance to the second distance.

Abstract: A device for adapting a wrist watch for securing onto and wearing upon an upper portion of laced footwear is disclosed. The device, used in pairs, secures a wrist watch to the laces of a shoe, sneaker or other laced footwear. The device permits the time to be checked by simply glancing down at the shoe, and leaves the wrists of the wearer free. The device permits the wearer to check the time even when both hands are occupied on a task.

Abstract: An information storage medium, a recording and/or reproducing apparatus and a recording and/or reproducing method area, the information storage medium including an access control area for recording access control data (ACD) having common information set so that even a recording and/or reproducing apparatus that cannot recognize a predetermined function applied to the medium can control access to the medium, the ACD including ACD attribute information providing information indicating whether or not to delete the ACD when the medium is re-initialized. According to the information storage medium, when the disc is re-initialized, by recording common information in relation to disc access control which even a drive system with a different standard can know, a drive system that cannot recognize a function applied to the disc as well as a drive system that can recognize the function can perform an appropriate operation by referring to this common information, such that compatibility of the disc can be improved.

Abstract: A slim optical pickup in which a leaf spring is combined with an upper surface of a semiconductor substrate, which is a silicon optical bench (SiOB) monolithically manufactured with a photodetector. The slim optical pickup has a substrate including a light source for generating a light beam, an optical element to irradiate light to an optical disc, a photodetector for receiving a light beam reflected by the optical disc, and a plurality of first bonding pads; a heat sink attached to the surface of the substrate; and a supporting means having a plurality of second bonding pads formed on an inner side of an array of the plurality of the first bonding pads on the substrate.

Abstract: For automatic adjustment of tracking balance, a microprocessor controls a servo control unit to adjust a tracking balance signal value for the optical disc reproduction to be a mid-value between a tracking balance signal value (hereafter referred to as first tracking balance signal value) to make a tracking error balance value 0% and a tracking balance signal value (hereafter referred to as second tracking balance signal value) to minimize jitter when the first tracking balance signal value is different from the second tracking balance signal value. This makes it possible to perform balanced tracking control with a good balance between tracking performance and jitter performance.

Abstract: A focus jump technique enables focus control on recording layers of a disc in such a manner that its effect is not absorbed by disturbance or a variation in the movement speed of an objective lens. The technique involves monitoring level of a focus error signal and rejecting noise from the error signal. A speed sensor detects movement speed of an objective lens; and a speed control circuit generates a voltage for controlling the objective lens, based on the detected movement speed. Movement speed of the objective lens is detected during focus jump, a corresponding lens drive signal is generated, and an end position is determined from behavior of the error signal immediately before the end of the jump. A focus control is pulled, from a focus point corresponding to one recording layer, into a focus point corresponding to another recording layer forcibly in a stable manner.

Abstract: The present invention relates to an apparatus for copying the data content of a source multi-session DVD-storage medium to a destination multi-session DVD-storage medium, wherein the data content is organized in sessions and files, and each session contains a file allocation table storing at least the physical start address of each file within a session, and wherein the address space between two adjacent sessions on said DVD-storage media is different. The apparatus comprises a read unit for reading data from said first storage medium, a write unit for writing data on said second storage medium, and a controller unit for controlling said read unit and said write unit. An address converting unit adapted to analyze the file allocation table of each session and to apply a predetermined address offset to each address in the file allocation table before writing said data to the second storage medium is also provided.

Abstract: A write signal control circuit in an optical disk drive for adjusting the duty cycle of the write signals by a duty cycle adjusting unit. The write signal control circuit includes a write signal generator for converting an EFM signal into the write signals according to the write strategy waveform generating rules, a duty cycle adjusting unit for adjusting the duty cycle of each write signal according to adjusting parameters and for outputting adjusted write signals, and a duty cycle detector for detecting the duty cycle of each adjusted write signal and outputting a respective duty cycle control signal. The duty cycle adjusting unit further receives the duty cycle control signal to adapt the adjusting parameters.

Abstract: The invention provides a data recording device comprising: an interval counter; an ? counter; and a segment counter, wherein the interval counter and the ? counter operate with a clock having a constant frequency which is independent of clock information, the interval counter is reset when division information is detected and, also, is reset and activates the ? counter when it reaches a count value corresponding to a segment length, the ? counter is reset when the division information is detected and, also, is reset and increments the count value of the segment counter when it reaches a count value corresponding to a predetermined length smaller than the segment length, and the segment counter increments its count value when the division information is detected and outputs a writing inhibition signal when it reaches a count value corresponding to the frame length.

Abstract: In an optical disk system using a PRML identification system, a method for deriving an optimum recording wave in a short period of time is provided. Parameters of the recording wave are adjusted by using an evaluation value obtained by a signal evaluation method which is suitable for the PRML identification system as an index. In this case, as a parameter adjusting method, a plurality of adjusting methods are utilized.

Abstract: An optical disk medium in which a learning area can be expanded, an optical disk information recording method and an optical disk apparatus are provided. A first lead-in area and second lead-in area are provided on the inner side and outer side of a data area. The first lead-in area includes a first learning area, management information recording area and data connection area and the second lead-in area includes a protection area which protects the user data in the inner portion thereof and a second learning area which is provided on the outer side of the protection area and sets an optimum condition for an operation of recording data into the data area. An area in which information indicating the utilization state of the protection area is recorded is prepared in one of the management information recording area and data connection area.

Abstract: There is provided an apparatus capable of switching between a laser that emits light having a wavelength suitable for detecting samples and a laser required for reading traced data, while an analysis optical disc is being traced. In an analyzer in which an analysis disc having a sample to be analyzed which is located in a part of its track is irradiated with laser light to read the state of the sample, a selector switch alternately selects a laser having a wavelength for reading data represented by bits or wobble grooves on the disc and a laser having a wavelength suitable for detecting a sample, in response to an instruction from a control unit.

Abstract: An apparatus for detecting and correcting an error in a wobble signal, includes a window generator which generates a window signal using a phase locked wobble signal, which is generated in synchronization with a raw wobble signal rwb obtained by binarizing the wobble signal read from an optical recording medium, and a control operation unit which corrects the error in the rwb signal and outputs the corrected rwb signal where the error in the rwb signal is detected in the window signal. Accordingly, the error in the wobble signal can be detected and corrected using the window signal, thereby increasing the performance of an optical recording/reproducing system and improving a phase locked loop (PLL) circuit using the apparatus.

Abstract: An optical disk recording method includes the steps of: providing a multi-pulse chain from a recording wave; independently changing the pulse rise timing and pulse fall timing (pulse width) of the first pulse in the multi-pulse chain in accordance with a preceding space length and a recording mark length; changing the pulse rise timing and pulse fall timing (pulse width) in accordance with a following space length and the recording mark length in a predetermined timing or in independence; and in relation to the smallest mark recorded by irradiation with mono pulse, changing the rise timing in accordance with the preceding space length and the recording mark length and the fall timing (pulse width) in accordance with the following space length and recording mark length, compensating various optical disks different in recording material without change of the fundamental waveform.

Abstract: An information recording method enables the precise formation of a recording mark on a recording layer having a high light transmittance such as an L1 layer of a double-layered optical recording medium. The information recording method uses the following recording strategy. A laser beam is pulse-modulated so as to create a pulse series including a write pulse of a recording power and a cooling pulse of a base power. Data to be recorded is modulated to have a length of a recording mark along a track of the recording layer. At the same time, the length of the recording mark is made to correspond to an integral multiple nT of T where T is one clock cycle. An nT recording mark corresponding to nT is recorded by using the same number of write pulses and cooling pulses when n is 4 or larger. Moreover, an average width AveTc for a single cooling pulse width Tc is set to satisfy: 1.0<AveTc/T<1.6 and a total pulse width SumTc of the used cooling pulses is set to satisfy: 0.5?SumTc/nT?0.8.

Abstract: The present invention discloses a mixed mode circuit for data slice with auto calibration and method thereof, which comprises a data slicer for converting an analog signal into a digital signal; a set of current pump for supplying a variable power supply; a microprocessor for controlling and adjusting the set of current pump; a digital sum value counter for performing an addition or a subtraction operation according to the result outputted by the data slicer; a digital signal processor for reading the internal values of the digital sum value counter and calculating the average of these internal values to obtain a parameter value. With the aforementioned structure, the invention integrates the mixed mode data slicer of analog and digital circuits so as to adopt the merits and eliminate the drawbacks of the pure analog and digital data slicer and thus achieves the objective of reading data from an optical disk better and more accurately.

Abstract: An information recording medium includes a lead-in area and a data area for storing contents information. The lead-in area includes a first lead-in information area and a second lead-in information area. The first lead-in information area corresponds to a first playback mode. The second lead-in information area corresponds to a second playback mode different from the first playback mode. The first lead-in information area has a first depth and is designed for storing lead-in information related to the contents information stored in the data area. The second lead-in information area includes pre-pits having a second depth greater than the first depth. The pre-pits represent predetermined information, such as information of copyright protection, related to the contents information stored in the data area.

Abstract: A hologram reproduction apparatus includes a light-receiving unit such as a two-dimensional sensor which obtains two-dimensionally modulated image data, and an A/D converter which A/D-converts analog data obtained by the light-receiving unit into digital data. In addition, the hologram reproduction apparatus detects a number of pixels having a digital value larger than a first defined value in the A/D-converted image data for one page, by a first pixel number detecting unit. The hologram reproduction apparatus controls a magnitude value of the image data at the time of the A/D conversion by the first control unit so that the number of detected pixels is within a predetermined range. Thereby, a dynamic range of the A/D conversion to the two-dimensional modulated image data can effectively be used. Therefore, a quantization noise due to the A/D conversion can be reduced, and also a reproduction S/N can be improved.

Abstract: An optical pickup includes: a first projector for projecting a first light beam of a first wavelength so as to record and reproduce information with respect to an optical disk having a first light transmissive layer; a second projector for projecting a second light beam of a second wavelength longer than the first wavelength so as to record and reproduce information with respect to an optical disk having a second light transmissive layer; an objective lens common to the first and second light beams; and a diffraction optical element made of a lens with a diffraction grating and a refracting face and disposed in an optical path between the first and second projectors and the objective lens. The diffraction optical element is set to satisfy a predetermined equation.

Abstract: A zone phase correcting lens wherein a change in the third-order spherical aberration or the like is small in the case of a change in temperature and an optical head device having the zone phase correcting lens used as an objective lens. A minus sign is appended to the height measurement of a step formed so as to make the lens thickness in the optical axis thinner toward the outer region and a plus sign is appended to a step formed so as to make the lens thickness thicker toward the outer region. Supposing that D is an absolute value of the sum of the height measurements of the steps having the minus sign on the first surface and the second surface and E is an absolute value of the sum of the height measurements of the steps having the plus sign on the first surface and the second surface, a wavelength ?1 and a refractive index N1 of the lens for a first laser beam satisfy the following conditions: 10×?1<{D×(N1?1)}<30×?1 2×E<D.

Abstract: A high density optical disc that can be driven changeably with the existent optical disc by the same driving apparatus. On the recording surface of the optical disc, a light transmissive layer with a thickness of about 0.2 to 0.4 mm is formed. The recording face is accessed by allowing a light beam with a wavelength of 395 to 425 nm in a spot shape to be irradiated onto it. Also, the light beam is converged in a spot shape by an objective lens having the numerical aperture of about 0.62 to 0.68.

Abstract: An optical pickup device comprises a light emitting element for emitting a laser beam, and a housing in which the light emitting element is mounted, wherein the light emitting element is contained in a holder for protecting the light emitting device, the holder including a projecting portion for dissipating heat generated by the light emitting element, and the projecting portion is located within the housing. Thus, an optical pickup device having a light emitting element held in a holder which is superior in heat dissipation and is resistant to damage can be provided.