Abstract: A system and method for recording trace data while conserving cache resources includes generating trace data and creating a cache line containing the trace data. The cache line is assigned a tag which corresponds to an intermediate address designated for processing the trace data. The cache line also contains embedded therein an actual address in memory for storing the trace data, which may include either a real address or a virtual address. The cache line may be received at the intermediate address and parsed to read the actual address. The trace data may then be written to a location in memory corresponding to the actual address. By routing trace data through a designated intermediate address, CPU cache may be conserved for other more important or more frequently accessed data.

Abstract: A data-storage apparatus, a data-storage method and a recording/reproducing system are provided, which effectively use the time elapsing before data is transferred to be written in a recording medium, such as disc-seeking time and disc-rotation standby time, thereby to raise the speed of transferring data. A hybrid storage apparatus has two storage areas, i.e., a disc and a nonvolatile solid-state memory. The disc and the memory have a disc cache area, a system area, and a user area each. If data is transferred from the host apparatus, it is written into the cache area of the nonvolatile solid-state memory that can be accessed at high speed for the first super cluster. While the data being so written, the head is moved to a prescribed position. Any data coming after the head is moved to this position is written into the cache area.

Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for communicating a first number of power management signals to at least a portion of the memory circuits that is different from a second number of power management signals received from the system.

Abstract: Accessing data memory includes writing data to a first memory location and to a second memory location in response to a request to write data to a memory address that corresponds to both locations, where the first and second memory locations are mirrored, in response to a request to read data from the memory address, reading data from the first memory location or the second memory location based on load balancing, and accessing data from the second memory location in response to a request to access data at the memory address when memory hardware corresponding to the first memory location has failed. Accessing the data memory may include requesting access to a specific one of the first and second memory locations. The memory address may contain a portion that is common to both the first memory location and the second memory location. Hardware coupled to the memory may cause data written using the memory address to be automatically written to the first memory location and the second memory location.

Abstract: A mobile computing hard disk drive has both a flash memory device and a DRAM device, with the HDD controller managing data storage between disk, DRAM, and flash both when write requests arrive and when the HDD is idle to optimize flash memory device life and system performance.

Abstract: A technique involves accessing a hard disk platter surface using surface virtualization. The technique includes receiving a command to access a hard disk platter surface. The command specifies an address. The technique further includes providing a virtual surface identifier based on the address specified by the command, and generating a particular real surface identifier based on the virtual surface identifier. The particular real surface identifier corresponds to a particular hard disk platter surface among multiple hard disk platter surfaces of a set of disk drives. The technique further includes accessing the particular hard disk platter surface among the multiple hard disk platter surfaces of the set of disk drives based on the particular real surface identifier. Such operation is capable of being carried out within a disk drive controller in a manner that is transparent to a host, or alternatively by the host.

Abstract: In one embodiment, a processing node includes a first processor core and a second processor core. The first processor core includes a first cache memory, such as an L2 cache, for example. The second processor core includes a second cache memory, such as an L2 cache memory. The processing node further includes a configuration unit that is coupled to the first processor core and the second processor core. The configuration unit may selectably disable portions of the first and the second cache memories.

Abstract: A data processing apparatus and a method for caching data values in data processing apparatus comprising a level one cache and a level two cache is disclosed. Both the level one cache and the level two cache are operable to store the data values. The method comprises the steps of: a) receiving a transaction request in which a data transaction relating to a data value is requested to occur, the transaction request including cache policy attributes associated with an address of the data value; and b) determining from the cache policy attributes whether or not the data value can be stored by the level one cache and the level two cache and, if so, in which one of the level one cache and the level two cache the data value is to be stored in order to ensure that the data value is prevented from being stored in both the level one cache and the level two cache.

Abstract: A method for accessing data in memory comprising, receiving address bits associated with a data item including a first tag, an index, and a sector ID from a requestor, associating the index with a congruence class in a primary directory, determining whether the first tag matches a second tag in a plurality of tags in the congruence class, wherein the each tag of the plurality of tags uniquely identifies a cache line associated with a primary ID in the congruence class, defining the primary ID of the second tag of the primary directory that matches the first tag, determining whether the primary ID and the sector ID are present in a secondary directory entry having a one to one correspondence with a sector in a data array, and sending the data item from the sector to the requestor.

Abstract: In a first aspect, a first method is provided for removing entries from an address cache. The first method includes the steps of (1) writing data to a register; and (2) removing a plurality of address cache entries from the address cache based on the data written to the register. Numerous other aspects are provided.

Abstract: A method for managing requests for deferred updates to shared data elements while minimizing grace period detection overhead associated with determining whether pre-existing references to the data elements have been removed. Plural update requests that are eligible for grace period detection are buffered without performing grace period detection processing. One or more conditions that could warrant commencement of grace period detection processing are monitored while the update requests are buffered. If warranted by such a condition, grace period detection is performed relative to the update requests so that they can be processed. In this way, grace period detection overhead can be amortized over plural update requests while being sensitive to conditions warranting prompt grace period detection.

Abstract: A write-through cache scheme is created. A store data command is sent to a cache line of a cache array from a processing unit. It is then determined whether the address of the store data is valid, wherein the original data from the store's address has been previously loaded into the cache. A write-through command is sent to a system bus as a function of whether the address of the store data is valid. The bus controller is employed to sense the write-through command. If the write-through command is sensed, a clean command is generated by the bus controller. If the write-through command is sensed, the store data is written into the cache array, and the data is marked as modified. If the write-through command is sensed, the clean command is sent onto the system bus by the bus controller, thereby causing modified data to be written to memory.

Abstract: A preemptive write back controller is described. The present invention is well suited for a cache, main memory, or other temporarily private data storage that implements a write back strategy. The preemptive write back controller includes a list of the lines, pages, words, memory locations, or sets of memory locations potentially requiring a write back (i.e., those which previously experienced a write operation into them) in a write back cache, write back main memory, or other write back temporarily private data storage. Thus, the preemptive write back controller can initiate or force a preemptive cleaning of these lines, pages, words, memory locations, or sets of memory locations.

Abstract: A cache connected to the virtualization engine in the center of a storage area network. The invention caches data in a virtual cache, without requiring translation to the physical location. The cache is done as the data crosses the network through the virtualization engine, eliminating the need to do the further translation and forwarding over the network to the actual storage controller in the event the data is in the cache. In addition, the invention eliminates the need for multiple caches at each physical storage controller.

Abstract: Method and related apparatus for internal data accessing of a computer system. In a computer system, a peripheral can issue accessing requests for system memory space with or without snooping the central processing unit (CPU). While serving a peripheral of single virtual channel utilizing a chipset supporting multiple virtual channels, the present invention assigns accessing requests to different processing queues according to their snooping/non-snooping attributes, such that reading/non-snooping requests are directly routed to a system memory. Also responses from system memory and CPU are buffered in the chipset respectively by utilizing buffer resources of different virtual channels. And by applying accessing routing dispatch, data accessing efficiency can be increased.

Abstract: Methods for dynamically allocating memory in a multiprocessor computer system such as a non-uniform memory access (NUMA) machine having distributed shared memory. The methods include allocating memory by specified node, memory class, or memory pool in response to requests by the system (kernel memory allocation) or a user (application memory allocation). Through these methods memory is allocated more efficiently in a NUMA machine. For example, allocating memory on a specified node in a NUMA machine, such as the same node on which a process requiring the memory is running, reduces memory access time. Allocating memory from a specified memory class allows device drivers with restricted DMA ranges to operate with dynamically allocated memory. Other benefits of these methods include minimizing expensive remote-memory accesses using a distributed reference count mechanism and lock-free cache access.

Abstract: Embodiments generally relate to a method of reducing latency and cost. A device access request is received in a memory of non-local node over a NUMA interconnect from a source node. The device access request is forwarded to an off-node controller from the memory of the non-local node. The device access request completion notification and data is forwarded to the source node.

Abstract: A multi-interfaced memory device includes an array of memory cells having a first interface and a second interface. The first interface and the second interface share an address bus and a data bus. One of the interfaces may be a random access memory interface and the second interface may be a paged access interface.

Abstract: In a data processing system having a memory control device including at least two mirrored memory ports, a method and computer-readable medium for processing read requests are disclosed herein. In accordance with the method of the present invention, a read request is received on a system interconnect coupling read requestors with memory resources. The received read request is issued only to a specified one of the at least two mirrored memory ports within the memory control device. In response to detecting an unrecoverable error resulting from the read request issued to the one mirrored memory port, the received read request is issued to an alternate of the at least two mirrored memory ports.

Abstract: Apparatus and method offloads processing from a networking processor operating in a storage environment. Three main functions are offloaded: semaphore processing, frame order processing, and timer processing. Offloading of semaphore processing enables ordered access to semaphores. Offloading of frame order processing enables the network processor to quickly transmit an incoming frame if the incoming frame is the next one in the frame order. Offloading of timer processing enables background checking of the timer list.

Abstract: In one embodiment of the invention, a method is provided for retrieving certain electronic information previously stored on certain storage media after a threshold set in the storage retention criteria has been exceeded in an electronic information storage system that stores electronic information on storage media in accordance with a storage retention criteria is provided. The method includes storing a record in a memory associated with a system manager that assigns the storage retention criteria to the certain electronic data, designating the storage media available for overwrite after the threshold set in the storage retention policy has been exceeded, identifying the certain storage media available for overwrite, and retrieving information from the certain media after the threshold set in the storage retention policy has been exceeded.

Abstract: Provided are a storage system and data management method capable of improving the usage efficiency of a storage extent. With this storage system, a first storage apparatus dynamically allocates a storage extent to the first volume and sends data written by the host system in the first volume to the second storage apparatus; a second storage apparatus writes the data sent from the first storage apparatus in a corresponding position in the second volume pair-configured with the first volume and stores as management information the position to which the data from the first storage apparatus in the second volume was written; and the second storage apparatus, during the restoration processing of the first volume, refers to the management information and sends to the first storage apparatus the data in a position to which the data from the first storage apparatus in the second volume was written.

Abstract: The storage system includes a plurality of storage nodes and a control device coupling unit. Each of the storage nodes includes at least one storage device configured to store data and at least one control device configured to control input and output of data for the storage device. The control device coupling unit is configured to connect the control devices without using an access path between the control device and a host computer connected to the storage system. The control devices connected by the control device coupling unit are included in mutually different storage nodes.

Abstract: A storage system and a backup method achieving enhanced reliability without degradation in the performance of the entire system. A first storage apparatus stores data transmitted from a host system and transmits it to a second storage apparatus and a third storage apparatus. The second storage apparatus and the third storage apparatus store the data transmitted from the first storage apparatus and verify the consistency in the data between themselves.

Abstract: Embodiments of the present invention include creating a subsequent backup copy of a data set by storing a full backup copy of the data set to reflect a state of a data set including blocks of data, at a first point in time. At a second point in time, after the first point in time, changes to the data set are identified. Next, as part of the subsequent backup copy, only each block of the data set which has been changed or added since the first point in time is stored.

Abstract: Upon receiving a primary/secondary switching command from a secondary host system, a secondary storage control device interrogates a primary storage control device as to whether or not yet to be transferred data that has not been remote copied from the primary storage control device to the secondary storage control device is present. In the event that yet to be transferred data is present, the secondary storage control device receives yet to be transferred data from the primary storage control device and updates a secondary volume. The primary storage control device then manages positions of updates to the primary volume due to host accesses to the primary volume occurring at the time of the secondary storage control device receiving the primary/secondary switching command onwards using a differential bitmap table.

Abstract: A scheme for securing a memory subsystem or stack is disclosed. A first memory device performs an authentication on a received operation. If the authentication is valid, a write protect signal to a second memory device is disabled, allowing write or erase operations to be performed on the second memory device.

Abstract: A method for securing access to a data medium comprises listing at least one unique identifier of media that a data transfer element is allowed to access in memory storage of the data transfer element, accessing only media having at least one of the listed unique identifiers in media cartridge memory with the data transfer element, and writing a unique identifier associated with the data transfer element to the cartridge memory of the selected medium with the data transfer element in response to no library assigned unique identifier being present in the cartridge memory of the selected medium.

Abstract: A method and system for reallocating memory in a logically partitioned environment. The invention comprises a Performance Enhancement Program (PEP) and a Reallocation Program (RP). The PEP allows an administrator to designate several parameters and identify donor and recipient candidates. The RP compiles the performance data for the memory and calculates a composite parameter. For each memory block in the donor candidate pool, the RP compares the composite parameter to the donor load threshold to determine if the memory is a donor. For each memory block in the recipient candidate pool, the RP compares the composite parameter to the recipient load threshold to determine if the memory is a recipient. The RP calculates the recipient workload ratio and allocates the memory from the donors to the recipients. The RP monitors and update the workload statistics based on either a moving window or a discrete window sampling system.

Abstract: Methods and systems for controlling centralized memory management in wireless terminal devices. Memory management scripts associated with a wireless application are stored in a registry accessible through a data network for on-demand download and execution. A memory management kernel in each terminal device monitors a memory utilization of the terminal device. Based on the memory utilization, the memory management kernel interacts with an application gateway hosting the terminal device to download and execute one or more of the memory management scripts.

Abstract: Techniques are presented for automatically generating Serial Presence Detect (SPD) contents. Standards for specific values associated with SPD contents are electronically represented with SPD tokens and rules. When a memory module is identified, a string of needed SPD tokens are acquired for that memory module. The SPD tokens are searched for in the standards and specific SPD values are assembled for the memory module based on the defined rules. The resulting SPD values which are associated with the rules form the needed SPD contents for the memory module. The SPD contents are used to configure an Electrically Erasable Programmable Read-Only Memory (EEPROM) on a memory module.

Abstract: An approach for freeing memory based upon its relocatable or non-relocatable property is provided. In one embodiment, drivers and other processes that do not provide callback methods or similar capability to route DMA requests to the correct physical address are identified and all memory allocations made by the driver or other process are made from the appropriate region.

Abstract: The storage control device of the present invention is able to perform input and output of data between blocks whose size is different with good efficiency. The size of extended logical blocks, which are units of data input and output within a storage control device, and the size of physical blocks, which are provided within the storage device, are different from one another. A write object range generation unit reads out both of the extended logical blocks which are adjacent to the write data, and creates a write object range by linking them to the write data. An assurance code checking unit checks a corresponding assurance code for each of these extended logical blocks. And a block size adjustment unit deletes superfluous data from the adjacent blocks, and adjusts the size of the write object range, so that it becomes an integral multiple of the size of the physical blocks.

Abstract: A data storage device including a non-volatile semiconductor memory and an attribute information storage unit. In an attribute information storage unit of the data storage device, there are stored the number of sectors in one block and the information indicating the logical address of a sector lying at a block boundary. A host device, on which is mounted the data storage device, grasps the number of clusters that make up one block in the data storage device and the location of the leading cluster position of the block and records the data on the block basis.

Abstract: Multiple virtual addresses map to the same physical location in memory if it has been determined that they are all intended to access the same data. In one embodiment, such virtual addresses are identified, and correspondence information (such as from a translation table) is changed in order to ensure that they all correspond to the same physical location, thus freeing up memory and preventing problems such as undue swapping. A memory request servicer and translation table are used in one embodiment in order to properly respond to two requests, using different virtual addresses, both of which store identical data, by accessing the same location in physical memory. In one embodiment, code rebasing for a code page is only performed if it has not been performed before; if it has, a reference to the already rebased code page is returned. Physical memory which has more than one use (e.g. physical memory referred to by multiple virtual addresses) is designated read-only.

Abstract: A computer system comprising a main memory and a processor die coupled to the main memory by a first bus. The processor die includes a processor core coupled to a first cache memory and multiple base and bounds registers (BBRS). Each of BBRs have a base virtual address field, an ending virtual address field and a base physical address field. The first cache memory has a table lookaside buffer (TLB) entry stored therein.

Abstract: A system and method for generating and updating a file system on a client computer. An original file system may be compared to an updated file system and the differences between the two file systems may be defined in specific data blocks. The differences may include new data blocks, modified data blocks, and data blocks that have been deleted. The new data blocks or modified data blocks may be sent to the client computer along with reference file updates to update the file system on the client computer. A virtual file system on the client computer may be created using the set of data blocks and the reference files to point to which data blocks contain the data for specific files. As the file system is updated, new data blocks and modified data blocks may replace deleted data blocks in the set of data blocks.

Abstract: A bitwise addressing mode includes including the shaping of symbols of variable length during an operation for reading or writing a symbol in a bank of memories. The addressing is then done with the aid of a word address and of a bit pointer designating the start of the symbol in the word corresponding to the word address. A shift operation is performed during an operation of reading or of writing.

Abstract: Profile information can be used to target read operations that cause a substantial portion of misses in a program. A software value prediction technique that utilizes latency and is applied to the targeted read operations facilitates aggressive speculative execution without significant performance impact and without hardware support. A software value predictor issues prefetches for targeted read operations during speculative execution, and utilizes values from these prefetches during subsequent speculative execution, since the earlier prefectches should have completed, to update a software value prediction structure(s). Such a software based value prediction technique allows for aggressive speculative execution without the overhead of a hardware value predictor.

Abstract: Processor (100) has a plurality of registers (120) for storing instructions for execution by the plurality of execution units (160). The plurality of registers (120) are coupled to the plurality of execution units (160) via distribution means (140). Distribution means (140) have a plurality of dispatch units (144) coupled to the plurality of execution units (160) and a reroutable network, e.g. a data communication bus (142), coupling the plurality of execution units (120) to the plurality of dispatch units (144). The data communication bus (142) is controlled by control unit (148). Dispatch units (144) are arranged to detect dedicated instructions in the instruction flow, which signal the beginning of an inactive period of an execution unit (160a, 160b, 160c, 160d) in the plurality of execution units (160).

Abstract: An SMT system has a dynamically shared GCT. Performance for the SMT is improved by configuring the GCT to allow an instruction group from each thread to complete simultaneously. The GCT has a read port for each thread corresponding to the completion table instruction/address array for simultaneous updating on completion. The forward link array also has a read port for each thread to find the next instruction group for each thread upon completion. The backward link array has a backward link write port for each thread in order to update the backward links for each thread simultaneously. The GCT has independent pointer management for each thread. Each of the threads has simultaneous commit of their renamed result registers and simultaneous updating of outstanding load and store tag usage.

Abstract: In one embodiment, a pipelined processor is described that includes an execution pipeline having a plurality of stages and a multi-cycle instruction (MCI) controller adapted to assert a stall signal to stall the multi-cycle instruction within one of the stages of the execution pipeline. The MCI controller is adapted to issue a plurality of instructions to subsequent stages in the pipeline while the multi-cycle instruction is stalled.

Abstract: In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported for the first store memory operation. The load/store unit comprises a queue having a first entry assigned to the first store memory operation. The load/store unit is configured to retain the first store memory operation in the first entry subsequent to retirement of the first store memory operation if the first store memory operation is not complete. The queue may have multiple entries, and more than one store may be retained in the queue after being retired by the retire unit.

Abstract: A method is provided for accessing, by an application running on a first processor, operating system services from an operating system running on a second processor by performing an assisted call. A data plane processor first constructs a parameter area based on the input and output parameters for the function that requires control processor assistance. The current values for the input parameters are copied into the parameter area. An assisted call message is generated based on a combination of a pointer to the parameter area and a specific library function opcode for the library function that is being called. The assisted call message is placed into the processor's stack immediately following a stop-and-signal instruction. The control plane processor is signaled to perform the library function corresponding to the opcode on behalf of the data plane processor by executing a stop and signal instruction.

Abstract: Methods and apparatus are disclosed to prefetch memory objects. An example method includes identifying program states associated with an executing program; associating memory profiles with respective ones of the program states; identifying at least one next probable state based on calculated entropy values; and prefetching memory objects associated with the at least one memory profile corresponding to the at least one next probable state.

Abstract: A branch prediction apparatus includes a branch information receiving unit that receives simultaneously, branch information for each of a plurality of branch instructions that are completed simultaneously, and a parallel branch predicting unit that performs branch prediction in parallel for the branch instructions completed simultaneously, based on the branch information received and a branch history of the respective branch instructions, to obtain branch prediction results.

Abstract: One embodiment of the present invention provides a system that predicts a jump target for a jump instruction. During operation, the system starts fetching the jump instruction while executing a process. Next, the system uses a program counter for the process and uses state information that is specific to the process to look up the jump target for the jump instruction. Finally, the system uses the jump target returned by the lookup as a predicted jump target for the jump instruction.

Abstract: This invention has as its object to provide an information input system which can flexibly select the storage location of information input from an input apparatus. To achieve this object, in an information input system which comprises an input apparatus for inputting information, and an information processing apparatus which is connected to the input apparatus and processes information transferred from the input apparatus, the input apparatus has a storage unit for storing input information, a connection detection device for detecting whether or not the information processing apparatus is connected to the input apparatus, and a controller for controlling to transfer the input information to the information processing apparatus without storing the information in the storage unit, when the connection detection device detects that the information processing apparatus is connected to the input apparatus.

Abstract: In some embodiments a boot progress of a System Boot Strap Processor in a multi-processor system is monitored and a boot processor failure is detected using an Application Processor. If the boot processor failure is detected at least a portion of the system is reinitialized (and/or the system is rebooted). Other embodiments are described and claimed.

Abstract: A convertible computer is equipped with a notebook computer function and a tablet computer function. When a system power supply is turned on, a functionality or physical configuration such as rotation state of a display module can be detected, and an environment can be controlled such as an operating system (OS) for a tablet computer or notebook computer is selectively booted. Input signals of input units can also be controlled in an activation or inactivation state according to a system mode. An operation of switch sensing an open/closed state of a liquid crystal display (LCD) can be controlled by a signal generated by the rotation operation of the display module. In a state in which at least one control value necessary for setting a system environment is stored in a memory, the system mode switching operation is monitored and the system environment is set according to the switched system mode.