Abstract: A method and system for evaluating performance of a device by on-chip determination of BER may include establishing and generating PRBS test packets in a closed communication path internally within a physical layer device (PLD) and a remote PLD. A BER for the PLD may be determined from within the PLD based on a comparison of at least a portion of the generated test packets with at least a portion of the generated test packets transmitted over the closed communication path received by the PLD via the closed communication path from the remote PLD. A transmit path of the PLD may be internally coupled to a receive path of the PLD, and a receive path of the PLD may be internally coupled to a transmit path of the PLD. The PLD may be internally configured to operate in an internal optical loopback mode or an internal electrical loopback mode.

Abstract: A remote control signal receiver receives a remote control signal in which bit signals are included as pulse signals. The remote control signal receiver includes a remote control signal receiving portion that receives a remote control signal, and a microcomputer. The microcomputer detects a change in a logic level of pulsed signals in the remote control signal, detects a pulse period and a pulse width of the pulse signals of the remote control signal, and determines whether there is an error in the remote control signal based on the detected pulse period and the pulse width of the pulse signals of the remote control signal. It is possible to detect an error in a remote control signal received by the remote control signal receiver.

Abstract: Disclosed is a method and apparatus for autonomously self-monitoring and self-adjusting the operation of an integrated circuit device throughout the integrated circuit device's useful life. The invention periodically performs performance self-testing on the integrated circuit device throughout the integrated circuit devices useful life. The invention also evaluates whether results from the self-testing are within acceptable limits and self-adjusts parameters of the integrated circuit device until the results from the self-testing are within the acceptable limits.

Abstract: A test apparatus for a mixed-signal semiconductor device that includes a plurality of event tester modules including analog and digital signal tester boards, a test head for event tester modules, a performance board including a socket for a DUT, a test fixture including a connection means, an option circuit for when the DUT is a mixed-signal integrated circuit including an analog and digital function blocks, a tester controller controlling the overall operation, and a switching parallel connection circuit sequentially connecting a single event tester board with a plurality of the DUTs. The event tester board and the DUTs are connected by a group unit. The number of parallel test is increased by an improved tester board or an improved performance board without the use of an extra event tester board for an analog signal test.

Abstract: A method and apparatus for testing semiconductor wafers is disclosed in which a test circuit is used that includes a waveform generator. The test circuit can test a single transistor or can test multiple transistors. A testing method is disclosed in which a supply voltage is applied to the waveform generator to produce pulses that are applied to the gate of a transistor to be tested. A bias voltage is applied to the source and drain of the transistor to be tested, and the charge pumping current that is generated at the substrate is then measured. The process can be repeated at different bias voltage levels to obtain additional current measurements, indicating the maximum charge pumping current for the transistor that is being tested. The determined maximum charge pumping current can then be used for determining whether there is excessive 1/f noise in the device under test.

Abstract: A method and apparatus for stopping the internal clock of a microprocessor synchronously with the execution of an instruction is provided. A stop instruction is placed in a sequence of instructions to be executed by the microprocessor. The execution of the stop execution may store a stop value into a stop register of the microprocessor. Clock stop logic detects when the stop value has been stored into the stop register. The clock stop logic instructs a clock generation component, of the microprocessor, to cease generation of an internal clock signal, thereby preventing the microprocessor from changing state. As further instructions are not executed by the microprocessor, the state of the microprocessor reflects the execution of the instruction immediately prior to the stop instruction. The processing state of the microprocessor may be obtained for use in debugging the design of the microprocessor or the instructions executed thereby.

Abstract: A method and system for built-in self-testing architecture, including: a logic built-in self-test (LBIST) controller in operable communication with a pseudo-random pattern generator; a multiple input signature register in operable communication with a plurality of scan channels; and circuitry in operable communication with the pseudo-random pattern generator and the multiple input signature register, wherein the circuitry includes a channel skip function which allows selection of any combination of scan channels to skip while scanning.

Abstract: Disclosed is a method for segmenting functionality of a hybrid built-in self test (BIST) architecture for embedded memory arrays into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction set. A block of higher-speed test logic is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller at a higher frequency. The higher-speed test logic includes a multiplier for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.

Abstract: A tester and method are provided for testing semiconductor devices. Generally, the tester includes a multitasking Algorithmic Pattern Generator (APG) to concurrently execute multiple programs on multiple test sites using a single pattern generator. In one embodiment, up to eight test programs are run independently and concurrently on eight independent sixteen-pin devices on a 128 pin test site. When the multitasking APG is ready to broadcast to a device, timing system associated with that device only (and not the other devices) are loaded. While the timing system is executing the cycle of the test programs for the device just loaded, the APG continues on to load the other devices. Because of the slow cycle rates required for programming versus reading, the tester is particularly advantageous for testing flash memory. Optionally, for higher throughput, the APG can be run in lock step at up to a maximum operating frequency of the APG during read cycle of flash.

Abstract: A pattern generator includes a main memory for storing a plurality of sequence data blocks for generating a test pattern, a first sequence cache memory for sequentially storing the sequence data blocks, a second sequence cache memory, a data development section for sequentially executing the sequence data blocks stored in the first cache memory and generating a test pattern and a read-ahead means, when the data development section detects a read-ahead instruction on reading ahead the other sequence blocks during executing one sequence data block, for reading the other sequence blocks from the main memory and storing the same in the second sequence cache memory.

Abstract: Integrated circuit bus integrity may be verified without specialized test equipment. In a diagnostic mode, the integrated circuit may output a series of predetermined activation patterns onto the data bus to verify integrity of the data bus. Further bus verification may be provided by an address capture mode where address bus contents are reflected onto the data bus. A microprocessor may control diagnostic mode operation.

Abstract: To reduce a circuit area of a data line driving circuit. The data line driving circuit includes a plurality of circuit blocks. A circuit block has shift register unit circuits, logical operation unit circuits and a control unit circuit. The control unit circuit specifies the operation period of the corresponding circuit block on the basis of the input and output signals of the shift register unit circuits and supplies a clock signal and an inverted clock signal to the shift register unit circuit.

Abstract: A magnetic memory which in some embodiments compares compressed fault maps is disclosed. In one embodiment, the magnetic memory may include at least two magnetic memory cells which are configured to store data. The magnetic memory includes a control system configured to periodically obtain parametric values from the magnetic memory cells and generate a corresponding compressed fault map using the parametric values. In some embodiments, at least one of the compressed fault maps is compared to a previous one of the compressed fault maps, and an indication is provided if there are differences.

Abstract: A memory system may include a plurality of non-volatile memory cells and a memory controller coupled to the plurality of non-volatile memory cells. The plurality of non-volatile memory cells may be arranged in blocks with each block including a plurality of pages of non-volatile memory cells. Moreover, the plurality of non-volatile memory cells may include a plurality of data blocks of non-volatile memory cells, a plurality of reserved blocks of non-volatile memory cells, and at least one management block of non-volatile memory cells. The memory controller may be configured to receive a data address for a page of non-volatile memory cells of a data block during a memory access operation, and to determine if the page of non-volatile memory cells corresponding to the data address is identified as being defective in the at least one management block.

Abstract: A method for improving the reliability of host data stored on Fiber Channel attached storage subsystems by performing end-to-end data integrity checks. When a read or write operation is initiated, an initial checksum for data in the read/write operation is generated and associated with the data, wherein the association exists through a plurality of layers of software and attached storage subsystems. The initial checksum is passed with the data in the read/write path. When a layer of software in the read/write path receives the initial checksum and data, the layer performs an integrity check of the data, which includes generating another checksum and comparing it to the initial checksum. If the checksums do not match, the read/write operation fails and the error is logged. If the checksums match, the integrity check is repeated through each layer in the read/write path to enable detecting data corruption at the point of source.

Abstract: The invention relates to an encoding method for encoding a codeword to obtain a parity code. The code is embedded in the codeword and divides the codeword to have intermediate symbol locations between a first and a second set of data symbols. Each data symbol forms a coefficient. The first and the second set of data symbols and the parity code respectively form a first polynomial (M1(x)), a second polynomial (M2(x)), and a parity code polynomial (R(x)).

Abstract: Improved method of encoding and repairing data for reliable storage and transmission using erasure codes, which is efficient enough for implementation in software as well as hardware. A systematic linear coding matrix over GF(2q) is used which combines parity for fast correction of single erasures with the capability of correcting k erasures. Finite field operations involving the coding and repair matrices are redefined to consist of bitwise XOR operations on words of arbitrary length. The elements of the matrix are selected to reduce the number of XOR operations needed and buffers are aligned for optimal processor cache efficiency. Decode latency is reduced by pre-calculating repair matrices, storing them in a hashed table and looking them up using a bit mask identifying the erasures to be repaired.

Abstract: Symbol by symbol variable code rate capable communication device. A communication device is operable to perform processing of a variable code rate signal whose code rate varies on a symbol by symbol basis. This may involve performing encoding of input to generate the variable code rate signal; alternatively, this may involve performing decoding of a variable code rate signal. In doing so, this approach may involve using a single encoder and/or decoder (depending on the application). In some instances, a single device is operable to encode a first variable code rate signal (for transmission to another device) and to decode a second variable code rate signal (that has been received from another device). In addition, a method of coding (including one or both of encoding and decoding) may also operate of a variable code rate signal whose code rate varies on a symbol by symbol basis.

Abstract: A data detector detects an identification signal of a prescribed format from N-bit wide parallel input data (where N is a natural number). The data detector includes P first comparing sections (where P is a natural number), Q second comparing sections (where Q is a natural number), and a determining section. Each of the P first comparing sections compares one of first P data of continuous (P+Q) data in the parallel input data with a first pattern. Each of the Q second comparing sections compares one of Q data following the P data with a second pattern. The determining section determines whether the identification signal has been detected or not according to a comparison result of the P first comparing sections and a comparison result of the Q second comparing sections.

Abstract: An algorithm for detecting a fault in an ECM output signal by determining a status of the output signal, incrementing an error timer and a retry timer when the status is abnormal, incrementing a retry counter when the retry timer reaches a maximum retry time, and reporting an intermittent fault if the retry counter reaches a retry limit before the error timer reaches an error timer maximum.

Abstract: A method and apparatus for locating items on a physical document and a method for creating a geographical link from an electronic document to the physical document. The geographical link is created by encoding, in a geographic link to the physical document, geographic coordinates of a referenced item in the electronic document. The electronic document is not derived from the physical document. Locating items on the physical document includes calibrating an opto-touch foil that is aligned on the physical document, including processing a calibration location included in locations appearing in the physical document and referred to in the electronic document. For each location, foil coordinates of the opto-touch foil corresponding to where each location appears in the physical document are computed utilizing geographic coordinates of each location and a generated calibration relationship between the geographic coordinates of the calibration location and calibration foil coordinates of the opto-touch foil.

Abstract: The present invention includes a method and system for persistently self-replicating multiple ranges of cells through a copy-paste operation, in a multi dimensional spreadsheet. A set of ranges of cells is defined, wherein each range of cells has the same size. Each time the content of a range of cells belonging to this set is changed, a self-replication operation is performed automatically. The self-replication operation includes the steps of copying the changed range of cells onto a buffer; determining the set of ranges of cells to which the changed range of cells belongs to; identifying the ranges of cells belonging to the set; and pasting the content of the buffer in each of identified range of cells belonging to the set.

Abstract: A computer-implemented method and computer-readable medium are provided for generating a multiple column layout. According to the method, a layout is defined that includes two or more columns and one or more spans that extend across two or more of the columns. Each span is defined as being either content defined or height defined. Content is laid out from a document in each span that is height defined until a defined height is reached. Content is laid out from the document in each span that is content defined until a specified point in the content is reached. When all content or height defined spans have been laid out, the remaining portion of the content is laid out across all of the columns.

Abstract: A displayed document comprises an annotation widget, the widget associated with an annotation document and a corresponding annotation key in an annotation store. The annotation document associated with a workflow action program. A user with a predetermined privilege selects a widget and is presented with the annotation document. The user performs an annotation task modifying the annotation document and submits the annotation document to the annotation store, the submission triggering the workflow action program to progress the workflow to another step.

Abstract: A system and method for describing a portal page, comprising, defining a placeholder on a template, associating at least one portlet with the placeholder, and wherein the template can be customized for least one of a group and a user.

Abstract: A system and method of generating data representing a master document for use in an automated document generation system comprises storing data representing a first mark-up notation or style and data representing a second mark-up notation or style different to the first mark-up notation or style. Data representing a mapping between the first and second mark-up notations or styles is stored. Data representing a precedent or master document written in the first mark-up notation or style is received. The received data is analyzed, in dependence on the data representing the first mark-up notation or style, to determine component elements of the first precedent or master document and the interrelationships of the component elements. Data is generated representing a precedent or master document written in the second mark-up notation or style based on the analysis and dependent on the data representing the mapping and the second mark-up notation or style. Lastly, the generated data is output.

Abstract: The generation of metadata shall be simplified. Therefore, a method is presented in which a metadata-template is filled with selected essence and MD-links obtained from a list of links to essence and/or a list of current metadata. Furthermore, it is possible to obtain the MD-links from further metadata or essences directly or indirectly linked with the selected essence.

Abstract: A system that may be used to generate documents and for broader uses such as assembling computer-processable components into computer-processable end products. In one form, the system is a document generation system having an assembly facility configured to be coupled to an origination platform; a knowledge base configured to be coupled to the assembly facility and to store objects in an object-relational hierarchy; and a content management system configured to be coupled to the knowledge base, where the content management system is configured to include an object and a rule. The system may be configured to interact with a knowledge base to create a first set of end products, each end product containing an object; apply precedence to the first set of end products; extract rules from the knowledge base; and assemble a second set of documents based upon applying precedence and rules.

Abstract: Various techniques are disclosed for representing extensible business reporting language (XBRL) documents in multidimensional form. For example, a computer-implemented system may include a computer and an XBRL taxonomy document containing extensible markup language (XML) elements. The system further comprises one or more XBRL instance documents each containing XML elements and each conforming to a schema defined by the XBRL taxonomy document, an XBRL engine to parse the XBRL taxonomy document and identify members of a first dimension, and to parse the one or more XBRL instance documents to identify members for each of one or more additional dimensions, wherein each additional dimension corresponds to a respective XBRL instance document. The system may also include a modeling engine to generate a multidimensional model having a plurality of dimensions. Users can view different dimensions and members of a multidimensional XBRL data model as though XBRL data were organized as multidimensional data cubes.

Abstract: A list control allows for a harmonized display of heterogeneous list element data by using at least two templates. The templates define the layout for the list element data. The templates consult an interface while calculating the layout. The interface provides information regarding the location of at least one gridline; the layout for the list element data is based on that location. The list control implements the interface, thus allowing heterogeneous templates to rely one interface providing on one gridline location. In order to take into account the requirements of each list element for gridline location, the interface requests information regarding a preliminary gridline location for each list element and bases the final gridline location on this information.

Abstract: According to the present invention, the quality of a small character can be prevented from lowering during copy of an image in an original. An image in an original is read by a scanner, and a recognition unit performs detection of a character size and a character position as well as character recognition. A CPU reads a font from a dictionary in accordance with the recognized character recognized by the recognition unit, and an image is generated based on the character size and the character position detected by the recognition unit and a copy magnification set by an MMI.

Abstract: A dynamic services infrastructure accepts data describing data resources and stores that data in a relational database from which it may be retrieved to handle service requests issued by application programs. The database stores Service Definition data which is initially supplied in the form of XML Service Descriptor documents which are then mapped into the database from which they may be accessed. Each Service Definition includes an input specification which identifies the address of a resource as well as the nature of the input data to be supplied to the resource with the request, and further includes an output specification which describes the nature of the output information which is supplied by the resource in response to the request.

Abstract: A method, system, and article of manufacture that help system administrators visualize the relationship between a global setting and the setting in each instance. One embodiment of the present invention comprises receiving a selection of a setting, determining an inheritance state for the selected setting, and displaying a graphical indication of the inheritance state of the selected setting. In some embodiments, the method further comprises displaying a graphical indication of the inheritance relationship between the selected setting and at least one related setting. The method may also include receiving a change inheritance relationship command, and changing the inheritance relationship for the selected setting.

Abstract: A system, method, computer program product and interface is included for providing an e-mail viewer pane including a sender identifier and text of an e-mail that is received from the sender; and an icon displayed simultaneously with the e-mail viewer pane for initiating a phone session with the sender upon the selection of the icon.

Abstract: A collaboration services suite is adapted to support a plurality of integrated telecommunications services accessed by geographically dispersed team members using a virtual team environment (VTE) client that generates a graphical user interface (GUI) for each of the respective team members. Communications sessions are automatically set up by the collaboration services suite in response to request messages generated by the VTE client when a team member initiates a communications session request using the GUI. Team members require no knowledge of another team member's communications device address in order to initiate a communications session. The collaboration services suite includes a VTE server that communicates with the VTE clients, a presence engine that collects and maintains a status of communications devices specified in a current profile of the team member; and, a call server for handling setup and control of a voice component of each communications session completed.

Abstract: A method and system that organize and retrieve multimedia objects. A controller may select an identifier associated with a media object to send a request to play the media object. The controller may send the request by transmitting the identifier stored in the controller. An appliance receives the request from the controller. The appliance retrieves the media object from a first server via a network connection when the media object is not stored in the appliance. Then the appliance may play the media object.

Abstract: A method for positioning a selected object in a computer generated original image on a display, comprising the steps of: distorting the original image to produce a distorted region for the object; dragging the object and the distorted region to a desired position; and, dropping the object at the desired position, whereby the object is accurately positioned. The steps of dragging and dropping are preferably performed by moving a cursor on the display with a pointing device such as a mouse.

Abstract: The present invention provides a computer-implemented method for managing commands for a terminal session. Specifically, using the graphical user interface of the present invention, a user can select a terminal session, and input one or more commands. Upon being input, a command is automatically send to the selected terminal session and added to a history or list of commands. Thus, the commands are “recorded” for potential future use upon being input. The commands are typically arranged in the list in a particular sequence, such as the order in which the commands were input. The user can individually send a command in the list to a terminal session, or the user can send a sequence of commands to the terminal session. In any event, results of executing the commands in the terminal session can be verified.

Abstract: A user interface system and method of displaying lists of information using a squeezed/semi-collapsed state of the group that shows, for example, a portion of the group (e.g., only the first few items of the group) is provided. The squeezed/semi-collapsed state takes up less room on the screen than an open state but gives the user more information about the group than the closed state, allowing more groups to be visible simultaneously while still providing detailed information about the contents of the group.

Abstract: A method, apparatus, and a user interface for managing and prioritizing items in a list are provided. Each item in the list is associated with and displayed adjacent to a user interface control for flagging the associated list item. When selected, the user interface control is operative to flag the corresponding list item. Moreover, the user interface control is further operative to change its visual state to indicate that the corresponding list item is flagged. List items flagged by other users appear differently. When again selected, the user interface control is further operative to remove the flagged state for the corresponding item and to set the state of the item as completed.

Abstract: The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.

Abstract: A systematic method and system for behavioral transformations for hardware synthesis and code optimization in software compilation based on Taylor Expansion Diagrams. The system can be integrated with any suitable architectural synthesis system. It can also be built into a compiler tool for general purpose processor or into a specific target compiler. For hardware synthesis, an arithmetic expression of the computation is extracted from the behavioral-level HDL design or directly from its matrix representation, and represented in canonical data structure, called Taylor Expansion Diagram. In architectural synthesis, factorization, common sub-expression extraction and decomposition of the resulting Taylor Expansion Diagram is performed, producing an optimized data flow graph, from which the structural HDL design is obtained using standard architectural synthesis.

Abstract: A method is provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances of line width and space limit violations in the electronic package physical design data are identified. The identified instances of line width and space limit violations are evaluated using predefined qualified options and tolerance limitations and the electronic package physical design data are modified to optimize shapes to replace the instances of line width and space limit violations.

Abstract: A method of producing multiple models of a hardware (integrated circuit) design including: translating a master model of a design of the integrated circuit to at least first and second models that are functionally equivalent to the master model and that are at different levels of abstraction from each, other and in which each of the first and second models includes integrated circuit timing information that is accurate for its level of abstraction.

Abstract: A method of minimizing phase noise is provided. In operation, a first phase noise in a first circuit located on an integrated circuit is determined. Additionally, a second phase noise in a second circuit coupled to the first circuit but which is not located in the integrated circuit is determined, the second circuit being programmable. Further, the first phase noise is compared with the second phase noise. If the phase noises are about the same, it is determined that the noise source is from an algorithm of a random number generator, the second circuit is modified to optimize the performances of the integrated circuit, and the modified second circuit is copied to the first circuit. If the phase noises are different, it is determined that a source of the phase noise is at least one of a power supply coupling and a substrate coupling in the integrated circuit.

Abstract: A thermally aware design automation suite integrates system-level thermal awareness into the design of semiconductor chips. A thermal analysis engine performs fine-grain thermal simulations of the semiconductor chip based on thermal models and boundary conditions for all thermally significant structures in the chip and the adjacent system that impact the temperature of the semiconductor chip. The thermally aware design automation suite uses the simulations of the thermal analysis engine to repair or otherwise modify the thermally significant structures to equalize temperature variations across the chip, impose specified design assertions on selected portions of the chip, and verify overall chip performance and reliability over designated operating ranges and manufacturing variations. The thermally significant structures are introduced or modified via one or more of: change in number, change in location, and change in material properties.

Abstract: A method for matching patterns, based on an orthogonal sub-space projection of layout shapes using Walsh patterns, performs a preliminary density feature extraction of a circuit design layout, allows a user to define a pattern, and performs a high resolution search of the layout to locate all instances of the pattern. A sorted list of layout windows ranging from the most similar to quantitatively less similar is generated. The method for matching patterns significantly reduces false positives in comparison with the prior art and enables the same density data to be reused as a window is stepped in small increments across the layout.

Abstract: The present invention includes a method and an apparatus, in one embodiment, in the form of an integrated circuit and programmable fabric design tool, for calculating skew in a manner that does not include unnecessary skew values, resulting in a skew value without pessimism. A setup slack determination ensures that data launched or transmitted from a source register reaches the destination register within a specified maximum cycle time and is defined as the difference between a minimum (early) destination time and a maximum (late) source time without unnecessary skew values. A hold check slack determination ensures the data does not “race” from the source register to the destination register on the same clock edge and is calculated as a difference between a maximum (late) destination time and a minimum (early) source time without unnecessary skew values. A circuit's operational frequency and layout are based upon the method for calculating skew.

Abstract: Some embodiments of the invention provide a routing method. The routing method receives a set of nets to route in a region of an integrated circuit (“IC”) layout. The routing method defines routes for the nets in a manner that ensures that each segment of each route is not less than a minimum length that is required for the segment. In some embodiments, the routing method identifies a route for a net by performing one or more path search operations. Each path search operation identifies one set of path expansions that can be used to define a segment of a route for the net. A path search operation in some embodiments performs a viability check for each path expansion that it identifies, in order to ensure that any segment that might eventually result from an identified set of path expansions satisfies its minimum required length.

Abstract: A method of distributing an array of interconnects on an electronic device divides the array into multiple regions, each region having certain performance requirements. For each region, predefined performance curves are used to choose from a plurality of interconnect distribution pattern modules one or more interconnect distribution pattern modules that satisfy the corresponding performance requirements. The chosen interconnect distribution pattern modules are used to generate a performance indication map highlighting those vulnerable interconnect(s) that may suffer severe crosstalk interference. Each vulnerable interconnect is then relocated to a different location until the performance requirements are met.