Abstract: A biological tissue equivalent phantom unit to be used by the specific absorption rate measuring system for evaluating absorption of electromagnetic wave energy includes a biological tissue equivalent phantom for absorbing an electromagnetic wave. In addition, two or more electro-optical crystals are arranged at two or more measurement points in the biological tissue equivalent phantom. The electro-optical crystals have a dielectric constant that is approximately equal to that of the biological tissue equivalent phantom. Two or more optical fibers are laid in the biological tissue equivalent phantom for optically connecting each of the electro-optical crystals to an external destination.

Abstract: A probe includes a tubular conductor having an aperture at one end thereof. An electromagnetic wave transmitting unit for transmitting an electromagnetic wave, via the tubular conductor, to a position distant from the aperture is disposed at one of the inside and the outside of the tubular conductor, and an electromagnetic wave receiving unit for receiving an electromagnetic wave, via the tubular conductor, from the position distant from the aperture is disposed in the other of the inside and the outside of the tubular conductor. The size of the aperture is smaller than or equal to the wavelength of the electromagnetic waves. The electromagnetic waves transmitted and received at the outside and the inside of the tubular conductor are coupled through the aperture. When an analyte to be observed is disposed so as to face the aperture, information of the analyte is obtained on the basis of a change in the coupling of the electromagnetic waves through the aperture.

Abstract: A system and method for sensing the proximity of an electronic device, in particular, a radio frequency mobile communication device such as a mobile telephone, wireless modem equipped portable computer, or the like to a body employs an antenna capable of altering its impedance for changing the amount of radio frequency electromagnetic energy reflected by the antenna when the antenna is in proximity to the body. The radio frequency electromagnetic energy reflected by the antenna is measured and used for determining proximity of the antenna to the body.

Abstract: A method of operating a passenger screening kiosk system to perform at least one verify a passenger's identity, detect the presence of an explosive material, and detect the presence of a metallic material includes initiating a prompt to be issued by the passenger screening kiosk system to prompt the passenger to enter the passenger screening kiosk system, prompting the passenger to enter the passenger screening kiosk system, and determining whether the passenger is within the passenger screening kiosk system.

Abstract: Novel system and methodology for determining resistance of wires in a communication cable having at least two pairs of wires used for providing power from a power supply device to a powered device. A measuring mechanism may determine DC resistance of the wires before the power supply device applies power to the communication cable.

Abstract: A system for monitoring the displacement of turbine blades that includes a turbine blade with a cutting tooth and one or more sensor wires, each sensor wire including a severable portion, that become severed by the cutting tooth as turbine blade displacement occurs. The sensor wires may be embedded in a honeycomb, which may be an area of abradable material attached to turbine shrouds. The sensor wires may include a plurality of radial sensor wires embedded in the honeycomb at varying predetermined radial distances from a turbine rotor. The sensor wires also may include a plurality of axial sensor wires embedded in the honeycomb at varying predetermined axial locations along the length of the honeycomb.

Abstract: A semi-automatic multiplexing system for automated semiconductor wafer testing employs a jumper block for each device type in the semiconductor wafer to be tested, each jumper block having inputs for receiving a test input/output line, a plurality of block contacts corresponding to pads of a device to be tested, and manually set connectors or jumper cables for selectively interconnecting jumper block inputs to block contacts. A multiplexer is then used for selectively connecting tester input/output lines to the jumper blocks, thereby reducing the number of relays required for connecting test signals to the devices in the semiconductor wafer.

Abstract: A method of making an interposer in which at least two dielectric layers are bonded to each other to sandwich a plurality of conductors there-between. The conductors each electrically couple a respective pair of opposed electrical contacts which are formed within and protrude from openings which are also formed within the dielectric layers as part of this method. The resulting interposer is ideally suited for use as part of a test apparatus to interconnect highly dense patterns of solder ball contacts of a semiconductor chip to lesser dense arrays of contacts on the apparatus's printed circuit board.

Abstract: The present invention is for enabling to carry out probing tests en bloc at the same time on electronic devices and semiconductor chips having high-density terminals. For this purpose, the electric signal connecting device includes vertical probes for getting into contact with terminals for electric connection created on electric functional elements to be tested for electric connection, and a resin film supporting the vertical probes, and the vertical probes are planted resiliently deformably in a surface of a resin film in a direction along the film surface, and an end of the vertical probes is brought into contact with terminals of electric functional elements to be tested and another end of the vertical probes is brought into contact with terminals of an electric function testing apparatus so that signals may be transmitted and received between the electric functional elements to be tested and the electric function testing apparatus.

Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

Abstract: In one embodiment, the invention provides a test assembly for electrically connecting a test component to a testing machine for testing electrical circuits on the test component. The assembly comprises a contactor assembly to interconnect with the test component, a probe assembly to mechanically support the contactor assembly and electrically connect the contactor assembly to the testing machine, and a clamping mechanism comprising a first clamping member and a second clamping member, the clamping members being urged together to exert a clamping force to deform contactor bumps of an electrical connection between the probe assembly and the contactor assembly.

Abstract: An electronic device test apparatus for testing IC chips (IC) by pushing their input/output terminals (HB) against contact units of a test head, provided with an IC moving system (410) for picking up and moving an IC chip (IC) at the front surface where input/output terminals (HB) are led out, a first camera for capturing an image of the front surface of an IC chip (IC) before being picked up, a second camera for capturing an image of a back surface of an IC chip (IC) after being picked up, and an image processing system for calculating the position of input/output terminals (HB) of an IC chip (IC) picked up by the IC moving system (410) from the image information captured by the first camera and second camera and identifying the relative position of the IC chip (IC) picked up by the IC moving system (410) with respect to a contact unit based on the results of calculation, wherein the IC moving system (410) corrects the position of the IC chip based on the relative position of the input/output terminals (HB)

Abstract: Embodiments disclosed herein are directed to compliant probe structures for making temporary or permanent contact with electronic circuits and the like. In particular, embodiments are directed to various designs of cantilever-like probe structures. Some embodiments are directed to methods for fabricating such cantilever structures. In some embodiments, for example, cantilever probes have extended base structures, slide in mounting structures, multi-beam configurations, offset bonding locations to allow closer positioning of adjacent probes, compliant elements with tensional configurations, improved over travel, improved compliance, improved scrubbing capability, and/or the like.

Abstract: The present invention relates to a contact tip structure of a connecting element designed for electric testing of electronic components. The connecting element comprises a fixing post coupled to a first electronic component; a beam extending away from said fixing post; a base coupled at one end of the said beam; and a contact tip extending vertically from the bottom surface of the said base. The beam includes an elastic region and an inelastic region extending at a shorter distance than the elastic region. The base vertically extends from the inelastic region in a certain distance and the horizontally extended length (L) of the elastic region of the beam and the vertically extended length (D) of the base are determined such that the contact tip is horizontally extended at a pre-determined distance according to the following formula: Dsin ?+L(cos ??1)(? means an angle of elastic deformation of the beam).

Abstract: A system including a chassis operable to receive a plurality of physical application modules and a test port via which an external test device is communicatively coupled to the system. Each physical application module includes a module bridge interface and boundary-scan test functionality. The test port is communicatively coupled to each of a chassis bridge interface in the chassis. When the module bridge interface of each of the physical application modules is communicatively coupled to a respective one of the plurality of chassis bridge interfaces, the boundary-scan test functionality of the respective physical application module is communicatively coupled to the test port.

Abstract: A circuit module testing apparatus and method are provided. According to various embodiments, a circuit module testing apparatus includes a printed circuit board, a socket receptacle adapted to be connected to the printed circuit board, a socket having pins on a first side, the pins adapted to be removably inserted into the socket receptacle, the socket adapted to receive a circuit module for testing, and a test circuit board soldered to the first side of the socket, the test circuit board having selected pins shorted for testing the module and clipped to prevent engagement with the socket receptacle. According to one embodiment, the test circuit board has selected pins shorted for interconnect built-in self-testing (IBIST). Other aspects and embodiments are provided herein.

Abstract: Methods and apparatus to test power transistors of integrated circuits on a wafer are disclosed. An example method comprises measuring a drain-source on resistance of a first transistor, measuring a drain-source on resistance of a second transistor, computing a scaling ratio between the transistors based on the drain-source on resistances of the transistors, measuring a first current indicative of an over-current condition of the first transistor, and computing a second current of the second transistor based on the current of the second transistor and the scaling ratio.

Abstract: A system and method for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary header on the voltage island of the chip communicates with the primary power supply via a primary header power path. A secondary header on the voltage island of the chip communicates with a secondary power supply via a secondary header power path. A control decoder communicating with the IC chip and the voltage island regulates the state of the primary and secondary headers.

Abstract: A method and apparatus for noise suppression. A circuit has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.

Abstract: An (SST) driver circuit having additional circuitry for minimizing data-dependent jitter in the SST driver and increasing frequency amplitude in the SST driver. The additional circuity comprises a plurality of switches configured to be turned on or pulsed on momentarily during operation to discharge a node in the SST output stage for the purpose of removing the stored charge before the next transition cycle of the output stage.

Abstract: A temperature-compensated output buffer circuit is disclosed, which includes a pull-up circuit including a first pull-up transistor for providing a first pull-up output signal responsive to a pull-up input signal, and a supplemental pull-up circuit in parallel with the first pull-up transistor. The supplemental pull-up circuit is configured to generate a supplemental pull-up output signal with the first pull-up output signal and the supplemental pull-up output signal, forming a pull-up output signal. The output buffer further includes a pull-down circuit, including a first pull-down transistor for providing a first pull-down output signal and a supplemental pull-down circuit in parallel with the first pull-down transistor. The supplemental pull-down circuit is configured to generate a supplemental pull-down output signal with the pull-up output signal and the pull-down output signal coupled to form an output buffer output signal.

Abstract: Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a switch to produce components such as crossbars, multiplexers, look-up tables (LUTs) and other logic circuits used in programmable logic structures (e.g., (FPGAs)). The programmable, non-volatile memory elements comprise one or more structures based on Phase Change Memory, Programmable Metallization, Carbon Nano-Electromechanical (CNT-NEM), or Metal Nano-Electromechanical device technologies.

Abstract: Circuits, methods, and apparatus for output devices having parasitic transistors for a higher output current drive. One such MOS output device includes a parasitic bipolar transistor that assists output voltage transitions. The parasitic transistor may be inherent in the structure of the MOS device. Alternately, one or more regions, such as implanted or diffused regions, may be added to the MOS device to form or enhance the parasitic bipolar device. The parasitic transistor is turned on when during an appropriate output transition and turned off once the transition is complete. The parasitic device may be turned on by injecting current into the bulk of a pull-down device, by pulling current out of the bulk of a pull-up device, or by tying the bulk of the output device to an appropriate voltage, such as VCC for a pull-down device or ground for a pull-up device.

Abstract: Embodiments are described for an output driver circuit capable of maintaining a substantially constant output impedance across a wide range of output voltages. The driver circuit includes a pull-up circuit and a pull-down circuit, each having two or more current paths that either source currents to or sink currents from the output node. The addition of the third current path provides additional current such that the sum of the total currents have a magnitude that changes linearly as the output voltage at the output node is being driven.

Abstract: A power management circuit is provided for controlling power dissipation in at least one combinational logic circuit. The power management circuit includes a detector operative to receive at least a first input signal to the combinational logic circuit and to detect a transition of the first input signal between a first logic state and a second logic state. The detector generates a control signal indicative of whether or not a transition of the first input signal has occurred.

Abstract: Various embodiments of the invention provide for cell structures having independently accessible circuit elements as a part of a customizable logic array device. In one embodiment, a cell forming a portion of a customizable logic array device includes a base layer, which, in turn, including circuit elements each having one or more inputs and one or more outputs. The cell also includes a configuration layer configured to form a logic device from one or more of the circuit elements. Further, the cell includes an interlayer connection layer configured to connect each of the inputs and the outputs to the configuration layer so as to enable each of the circuit elements to be independently accessible. Advantageously, the interlayer connection layer facilitates usage of each of the circuit elements to reduce the number of unused circuit elements in the cell.

Abstract: A comparator circuit for reducing current consumption in a low consumption mode while suppressing the generation of glitches during a transitional period. The comparator circuit includes a comparison core circuit unit, a monitor circuit unit formed by a first transistor, and a nonlinear amplification circuit. The comparison core circuit includes second and third transistors connected to a constant current source. The source terminal and gate terminal of the first transistor have the same connection as the source terminal and gate terminal of the third transistor. The current flowing to the first transistor is supplied to the nonlinear amplification circuit. The nonlinear amplification circuit amplifies the supplied current with an incorporated constant current source and supplies the amplified current to the source terminals of the second and third transistors of the comparison core circuit.

Abstract: A data input buffer in a semiconductor is capable of avoiding operation speed deterioration of the data input buffer due to the temperature condition or process characteristic. The data input buffer in a semiconductor device includes an input detecting unit for detecting logic level of input data by comparing the voltage level of the input data with a reference voltage, a current driving capability adjusting unit for adjusting current driving capability of the input detecting unit based on at least one of temperature condition and process characteristic, and a buffering unit for buffering the output signal from the input detecting unit.

Abstract: A driver circuit includes first and second three-terminal active elements, and first and second delay units. The first and second three-terminal active elements are series-connected. Each of the first and second three-terminal active elements has an amplification function and first, second, and third electrodes. The second and third electrodes of each three-terminal active element are series-connected between the first and second potentials. The first and second delay units receive the same input signal. The outputs of the first and second delay units are respectively connected to the first electrodes of the first and second three-terminal active elements. The delay amount of the second delay unit is larger than that of the first delay unit. The delay amount of the first delay unit is a finite value including zero.

Abstract: A driver circuit for providing an output signal for switching an electrical load on and off has a field-effect transistor having a gate terminal and an output for providing the output signal to the electrical load, a buffer circuit connected to the gate terminal of the field-effect transistor to impress a charge change current on the gate terminal of the field-effect transistor based on a drive signal, and a comparator having a first input for receiving the gate voltage and a second input for receiving the output signal to determine whether the gate voltage and the output voltage fulfill a predetermined relationship with respect to each other, and to provide the drive signal to the buffer circuit so that the charge change current is changed in magnitude when the predetermined relationship is fulfilled as compared to the charge change current when the predetermined relationship is not fulfilled.

Abstract: This disclosure relates to an electronic driver device for an external load to which an input signal is applied at its input and that produces an output signal to the external load from its output. Such an electronic driver device includes elements that reduce dependence of the slew rate of the output signal on the external load capacitance.

Abstract: A frequency dividing circuit includes: a D-type flip flop that outputs frequency-divided signal synchronized with input clock and reverse phase signal corresponding to the frequency-divided signal; a variable delay circuit that generates a delay feedback signal delayed by a specific delay time from the reverse phase signal input from the D-type flip flop and feeds back the delay feedback signal to the D-type flip flop; and a delay adjusting circuit that detects a phase difference between the reverse phase signal input from the D-type flip flop and the delay feedback signal input from the variable delay circuit, obtains detected results, and outputs to the variable delay circuit a control signal to perform control so that the delay time becomes time required to ensure setup/hold time of the D-type flip flop, based on the detected results.

Abstract: An instantaneous phase error detector (IPED) and method includes a first gate configured to logically OR output phase error signals as data to a first latch, and a second gate configured to logically combine the output phase error signals to clock the first latch. A delay element delays to the data to the first latch where the output of the first latch provides instantaneous phase error change information. A second latch is coupled to the output phase error signals to output a lead/lag signal to indicate which of the output phase error signals is leading. A phase-locked loop employing the output of the IPED is also disclosed along with static phase measurement and jitter optimization features.

Abstract: A digital DLL circuit includes: a first register configured to hold a delay specifying value to specify a delay; a second register configured to specify a correction value for a gate delay inside an LSI; a digitally-controlled variable delay circuit; and a control circuit configured to produce a delay control value to implement control so that a delay by the variable delay circuit is kept at the delay specifying value of the first register. The digital DLL circuit further includes an adder circuit configured to add a gate delay correction value held by the second register to the delay control value output from the control circuit, and output a resultant value to a control input of the variable delay circuit.

Abstract: An analog, duty cycle replicating frequency converter extracts duty cycle information from an input, pulse width modulated signal and generates an output pulse width modulated signal of the same duty cycle at a different frequency without regard to the frequency of the input signal. It uses bipolar transistor based circuitry, adaptable to an application specific integrated circuit, to derive voltages representing the on-time and period durations of the input signal, convert these voltages to currents representing the logarithms thereof, generate a voltage representing the difference between the currents, exponentially convert the voltage to a current representing the duty cycle and control an oscillator to generate an output pulse width modulated signal at a predetermined frequency with the duty cycle of the input signal.

Abstract: A synchronous memory device having an output driver controller, comprises a DLL circuit for receiving an external clock and outputting an internal clock; an output driver for outputting data in synchronism with the internal clock; and an output driver controller for controlling operation of the output driver, wherein the output driver controller makes the output driver active after receiving from the DLL circuit a control signal indicating that the internal clock is locked and is in a stabilized state.

Abstract: A delay circuit for delaying an input signal according to a desired delay time setting and outputting the same is provided. The delay circuit includes: a delay element for delaying the input signal for a delay time based on a given supply current and outputting the same; a current supply section for generating a supply current; a voltage generating section for generating a base voltage dependent on a delay time setting; and a control section for converting a base voltage to a control voltage dependent on the characteristic of the current supply section and providing the same to the current supply section in order to cause the current supply section to generate the supply current. The current supply section may have a predetermined conductivity and include a first MOS transistor for applying a drain current to the delay element as the supply current.

Abstract: A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

Abstract: Methods and circuits for performing high-speed, high-resolution signal comparisons using offset cancellation, reduction of charge injection noise, and sharing of coupling capacitors between circuit stages. A multistage comparator circuit includes first and second preamplifiers electrically coupled to each other through series connections including coupling capacitors. A latch for storing the comparison output signal is electrically coupled to the output of the second preamplifier. The multistage comparator operates such that the offset voltages of the first preamplifier and of the second preamplifier and latch are stored on the coupling capacitors before performing comparisons.

Abstract: An IC having improved reliability includes at least first and second circuit blocks and at least first and second power domains, the first circuit block being connected to the first power domain and the second circuit block being connected to the second power domain. The IC further includes at least one control circuit configured to generate at least first and second control signals. The first control signal is operative to selectively connect the first power domain to a first voltage supply, and the second control signal is operative to selectively connect the second power domain to a second voltage supply. The IC includes at least first and second clamp circuits, the first clamp circuit being connected to the first power domain, the second clamp circuit being connected to the second power domain. Each of the clamp circuits is operative to prevent a voltage on a corresponding power domain from rising above a prescribed voltage level for the corresponding power domain.

Abstract: A voltage converter and a method of converting a voltage which maintain a first driver of a driver pair in an active state, where current flows, for only a predetermined time period. The driver pair may include a pull-up driver and a pull-down driver. One driver may be active when an input signal has a first transition, but not a second transition. The other driver may be active when the input signal has the second transition, but not the first transition. Alternatively, one driver may be inactive when the input signal has the second transition and active for a first portion of the first transition and inactive for a second portion of the first transition. Alternatively, only one driver may be active at any given time.

Abstract: A method, apparatus and/or system of a level shifter circuit having a structure to reduce fall and rise path delay is disclosed. In one embodiment, a level shifter circuit comprise a first set of sequentially coupled pull-up and pull-down sub-circuits cross coupled to a second set of sequentially pull-up and pull-down sub-circuits to generate a positive feedback loop; an output node coupled to a shared node between the first pull-up and pull-down sub-circuits through an output inverter; a pull-up NMOS transistor with a gate contact coupled to the input of the second set, a source contact coupled to an input of the output inverter and a drain contact coupled to the output voltage of the level shifter circuit; and a pull-down NMOS transistor with a gate contact coupled to the input of the second set, a drain contact coupled to an output of the output inverter and a source contact coupled to a ground.

Abstract: The invention relates to a current controlled level shifter which has an input stage having an input for supplying an input signal and having first and second outputs for providing a first and a second control current. A first shifter stage is connected to the outputs of the input stage and is designed to produce an output signal which is dependent on the first and second control currents. A feedback path is designed to provide at least one feedback signal which is dependent on the output signal and to supply it to the input stage. The input stage is designed to compare the input signal with the at least one feedback signal and to set the amplitudes of the control currents on the basis of this comparison.

Abstract: Systems and methods for conveying signals between integrated circuit (IC) components in domains having different supply voltages. AC coupling is used to increase the speed at which the common mode voltage of a signal is shifted from one level to another. One embodiment comprises a method for level shifting a binary signal in an IC. This method includes receiving an input binary signal and decoupling its AC component from its common mode component. A second common mode component is added to the AC component, providing a binary output signal. The common mode voltage of the input signal may be greater (or smaller) than that of the output signal. In one embodiment of the method, duty cycle compensation (DCC) is performed. The DCC drives the duty cycle toward a desired value.

Abstract: A level conversion circuit includes a controlling section supplied with a first power supply voltage and a second power supply voltage different from each other, the controlling section outputting a bias voltage, detecting rising of the first power supply voltage and the second power supply voltage, and outputting a control signal corresponding to a period from the rising of a power supply voltage to stabilization of the power supply voltage, and a level converting section supplied with the control signal and the bias voltage, operation of the level converting section being set in one of a shutdown state and a normal operation state according to the control signal, and the level converting section converting level of an input signal and outputting a signal different in level from the input signal when the operation of the level converting section is set in the normal operation state.

Abstract: The present invention discloses a multi-function circuit module having voltage level shifting function and data latching function via switching a plurality of switch elements. The multi-function circuit module includes a first circuit module, a fourth switch element, and a fifth switch module, wherein the first circuit module further includes a first switch module, a second switch module, and a third switch module. The multi-function circuit module can substantially reduce the circuit layout area. For example, when the multi-function circuit module of the present invention is applied in a source driving chip circuit, the multi-function circuit module can replace the original low-to-high voltage level shifting circuit and data latching circuit, so as to attain the purpose of reducing the chip area.

Abstract: A quadrature mixer circuit and an RF communication semiconductor integrated circuit capable of suppressing variations in secondary distortion while reducing the current consumption are provided. In a quadrature mixer circuit, even if local signals different by 90 degrees inputted to the bases of I transistors and Q transistors have large amplitudes, interference is suppressed by I resistors, Q resistors, and capacitors. Also, since the capacitors are provided, changes in bias current values can be suppressed. Accordingly, variations in secondary distortion can be suppressed. Furthermore, the capacitors combine current outputs of a differential circuit formed of I transistors and the resistor and a differential circuit formed of Q transistors and the resistor. Therefore, current consumption can also be reduced.

Abstract: A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified into a circuit which uses a MOST that changes dynamically into an enhancement mode and a depletion mode.

Abstract: A pull-out lower limit voltage for setting a voltage level when the gate voltage of the charge transfer transistor is pulled out is supplied to a reset circuit. In order to secure the breakdown voltage margin of the transistor and the capacitor used in a booster cell, a voltage which is not necessarily constant is used as the pull-out lower limit voltage. Accordingly, it is possible to provide a stabilized booster circuit in which an optimal gate voltage level of the charge transfer transistor can be set, overcharging can be suppressed, and the recovery time of the booster circuit can be shortened.

Abstract: A charge pump circuit including a plurality of switches and a switch control circuit is provided. The charge pump circuit is suitable for a display panel. The switches switch from “off” state to “on” state in an enable transition, and switch from “on” state to “off” state in a disable transition. The switch control circuit is coupled to the switches for controlling the on/off states of the switches and allowing the charge pump circuit to provide an output voltage that is different from an input voltage. The switch control circuit prolongs the time required for enable transition of the switches to be longer than the time for disable transition thereof. The equivalent impedances of the switches change from high values to low values when the switches are at the enable transition.