Abstract: A light emitting device includes: a plurality of transistors individually corresponding to a plurality of pixels arrayed in a matrix shape, and a plurality of wiring lines connected with the transistors and disposed between the pixels. The wiring lines include signal lines connected with the transistors of the pixel columns composed of a plurality of pixels along a row direction or a column direction, and two or more common electrode lines connected with the transistors of a pixel group composed of a plurality of pixels along the row direction and the column direction. The common electrode lines are arranged on the two sides centering the signal lines.

Abstract: A nitride semiconductor light-emitting device includes a layered portion emitting light on a substrate. The layered portion includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The periphery of the layered portion is inclined, and the surface of the n-type semiconductor layer is exposed at the periphery. An n electrode is disposed on the exposed surface of the n-type semiconductor layer. This device structure can enhance the emission efficiency and the light extraction efficiency.

Abstract: A surface mounting device-type light emitting diode (SMD-type LED) comprises a package housing one or more pairs of electrodes therein, the package having a predetermined space in the center thereof and a light-emission window which is opened so that light is emitted through the light-emission window; a lens formed on the package so as to cover the light-emission window; an LED chip formed on an electrode inside the package; a wire for electrically connecting the LED chip and the electrode; and a phosphor-mixed layer formed on the surface of the lens adjacent to the light-emission window.

Abstract: An ultraviolet ray emitting element package comprises a condenser lens, and an ultraviolet ray emitting element which is arranged approximately at a center and in a bottom side of the condenser lens and which is apart from a bottom of the condenser lens, wherein a refractive index difference reduction substance having an ultraviolet ray durability is filled in a gap formed by the ultraviolet ray emitting element and the bottom of the condenser lens.

Abstract: Disclosed is a light-emitting device (100) has a light-emitting layer portion (24) which is composed of a group III-V compound semiconductor and a transparent thick-film semiconductor layer (90) with a thickness of not less than 40 ?m which is formed on at least one major surface side of the light-emitting layer portion (24) and composed of a group III-V compound semiconductor having a band gap energy larger than the photon energy equivalent of the peak wavelength of emission flux from the light-emitting layer portion (24). The transparent thick-film semiconductor layer (90) has a lateral surface portion (90S) which is a chemically etched surface. The dopant concentration of the transparent thick-film semiconductor layer (90) is not less than 5×1016/cm3 and not more than 2×1018/cm3. The light-emitting device can have a transparent thick-film semiconductor layer while being significantly improved in light taking-out efficiency from the lateral surface portion.

Abstract: A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.

Abstract: A semiconductor device is provided which comprises a periphery region 23a extending downward from a third semiconducting region 23, enveloping an outer surfaces 21a and 22b of first and second semiconducting regions 21 and 22. A PN junctions is formed between second and third semiconducting regions 22, 23 inside of periphery region 23a perfectly away from side surfaces 28 of semiconductor substrate 27 to exert no adverse effect on breakdown by crystal defect in and foreign matters attached to side surfaces of semiconductor substrate 27. As periphery region 23a has the thinner diffusion concentration of impurity with the deeper area of periphery region 23a to widely spread depletion layer on boundary of the periphery region 23a with increase electric resistance.

Abstract: A method of forming an isolation region using porous silicon and a related structure are disclosed. One embodiment of the method may include forming a collector region; forming a porous silicon region in the collector region; forming a crystalline silicon intrinsic base layer over the collector region, the intrinsic base layer extending over a portion of the porous silicon region to form an extrinsic base; and forming an isolation region in the porous silicon region. The method is applicable to forming an HBT having a structure including a crystalline silicon intrinsic base extending beyond a collector region and extending over an isolation region to form a continuous intrinsic-to-extrinsic base conduction path of low resistance. The HBT has improved performance by having a smaller collector to intrinsic base interface and larger intrinsic base to extrinsic base interface.

Abstract: Electromechanical circuits, such as memory cells, and methods for making same are disclosed. The circuits include a structure having electrically conductive traces and supports extending from a surface of the substrate, and nanotube ribbons suspended by the supports that cross the electrically conductive traces, wherein each ribbon comprises one or more nanotubes. The electro-mechanical circuit elements are made by providing a structure having electrically conductive traces and supports, in which the supports extend from a surface of the substrate. A layer of nanotubes is provided over the supports, and portions of the layer of nanotubes are selectively removed to form ribbons of nanotubes that cross the electrically conductive traces. Each ribbon includes one or more nanotubes.

Abstract: A power metal-oxide-semiconductor field effect transistor (MOSFET)(100) incorporates a stepped drift region including a shallow trench insulator (STI)(112) partially overlapped by the gate (114) and which extends a portion of the distance to a drain region (122). A silicide block extends from and partially overlaps STI (112) and drain region (122). The STI (112) has a width that is approximately 50% to 75% of the drift region.

Abstract: The invention is directed to an improvement of reliability in a chip-size package type semiconductor device and a manufacturing method thereof. A semiconductor substrate formed with a pad electrode is prepared, and a first protection layer formed of epoxy resin is formed on a front surface of the semiconductor substrate. Then, a via hole is formed from a back surface of the semiconductor substrate to the pad electrode. A wiring layer is then formed from the via hole of the semiconductor substrate, being electrically connected with the pad electrode through the via hole. Then, a second protection layer and a conductive terminal are formed, and the semiconductor substrate is separated into individual semiconductor dies by dicing.

Abstract: A dielectric layer may be formed by depositing the dielectric layer to an intermediate thickness and applying a nitridation process to the dielectric layer of intermediate thickness. The dielectric layer may then be deposited to the final, desired thickness.

Abstract: Image sensors and methods of manufacturing an image sensor are disclosed. A disclosed photo diode may receive short wavelength light in its depletion region without exhibiting defective phenomenon such as noise and dark current. In the illustrated example, this performance is achieved by forming a trench type light-transmission layer to occupy a major surface of the photo diode so as to reduce the area available for defects on the surface of the semiconductor substrate. As a result of this reduction, the depletion region formed upon the operation of the sensor may extend toward the surface of the semiconductor substrate without concerned for defects. The image sensor may be manufactured without forming a blocking layer in connection with a silicide layer.

Abstract: The present invention, in the various exemplary embodiments, provides a RGB color filter array. The red, green and blue pixel cells are arranged in a honeycomb pattern. The honeycomb layout provides the space to vary the size of pixel cells of an individual color so that, for example, the photosensor of blue pixels can be made larger than that of the red or green pixels. In another aspect of the invention, depicted in the exemplary embodiments, the honeycomb structure can also be implemented with each pixel row having a same color of pixel cells which can simplify can conversion in the readout circuits. In another aspect of the invention, the RGB honeycomb pixel array may be implemented using a shared pixel cell architecture.

Abstract: A pixel area, which is composed of a plurality of unit pixels each including a photoelectric conversion unit and a signal scanning circuit, is formed on a semiconductor substrate. An optical black pixel region, in which a plurality of optical black pixels for setting a dark-time level are formed, is formed in the pixel area. A barrier layer, which has an impurity concentration that is higher than an impurity concentration of the semiconductor substrate and has a conductivity type that is identical to a conductivity type of the semiconductor substrate, is formed in the optical black pixel region of the semiconductor substrate.

Abstract: A ferroelectric capacitor includes a bottom electrode, a ferroelectric layer formed on the bottom electrode, and a top electrode formed on the ferroelectric layer. A plurality of projection electrodes are formed on the bottom electrode.

Abstract: The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiOx) doped with lanthanide elements, such as samarium, europium, gadolinium, holmium, erbium and thulium, produces a reliable structure for use in a variety of electronic devices. The dielectric structure is formed by depositing titanium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing a layer of a lanthanide dopant, and repeating to form a sequentially deposited interleaved structure. Such a dielectric layer may be used as the gate insulator of a MOSFET, as a capacitor dielectric, or as a tunnel gate insulator in flash memories, because the high dielectric constant (high-k) of the layer provides the functionality of a thinner silicon dioxide layer, and because the reduced leakage current of the dielectric layer when the percentage of the lanthanide element doping is optimized.

Abstract: The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.

Abstract: A semiconductor device and method of manufacturing the same having pad extending parts, the semiconductor device includes an isolation layer that defines an active region and a gate electrode which traverses the active region. A source region is provided in the active region at one side of the gate electrode, and a drain region is provided in the active region at a second side of the gate electrode. A first interlayer insulating layer covers the semiconductor substrate. A source landing pad is electrically connected to the source region, and a drain landing pad is electrically connected to the drain region. A pad extending part is laminated on one or more of the source landing pad and the drain landing pad. The pad extending part has an upper surface located in a plane above a plane corresponding to the upper surfaces of the source landing pad and the drain landing pad.

Abstract: A non-volatile memory includes a substrate, a plurality of data storage elements positioned on the substrate, a plurality of control gates positioned above the data storage elements, an insulating layer positioned on surfaces and sidewalls of the control gates, and a bit-line positioned on the insulating layer to cross the control gates.

Abstract: A semiconductor device includes a semiconductor substrate, a gate insulating film, gate electrodes, a first silicon oxide film, bit lines formed on the first silicon oxide film and including lower surfaces having respective recesses, a contact plug layer located between the gate electrodes and including a first portion, a second portion having a fourth side surface between the opposed second side surfaces of first silicon oxide film and a third portion having an upper surface and fifth side surfaces embedded in the respective recesses of the bit line, a first silicon nitride layer between a third side surface of the first portion of the contact plug and a first side surface of the gate electrode, and a second silicon oxide film. The entire upper surface and fifth side surface of the third portion of the contact plug directly contact with inner surfaces of the recesses respectively.

Abstract: A semiconductor device is provided which has insulating film side wall spacers having a barrier function. The semiconductor device comprises: a gate oxide film and a gate electrode formed on and above a semiconductor substrate; source/drain regions formed in the semiconductor substrate; and first laminated side wall spacers having two or more layers and formed on side walls of the gate electrode, the first laminated side wall spacers including a nitride film as a layer other than an outermost layer, the outermost layer being made of an oxide film or an oxynitride film and having a bottom surface contacting the semiconductor substrate, the gate oxide film or a side wall spacer layer other than the nitride film.

Abstract: A vertical array of flash memory cells. Transistor bodies are disposed on a substrate, comprising a source, channel and drain region, stacked thereon. Two joint gate structures are disposed on opposite sidewalls of every two transistor bodies respectively, and include a joint tunnel oxide layer disposed conformally on sidewalls of the two transistor bodies and the substrate there between, two floating gates on the opposite sidewalls of the tunnel oxide layer, a joint insulating layer covering the floating gates and the substrate there between, and a joint control gate layer on the sidewalls of the transistor bodies and the substrate there between. A dielectric layer covers the transistor bodies, where bit lines and word lines are disposed therein in contact with the top surfaces of the transistor bodies and the control gates between every two transistor bodies respectively. Source lines are disposed in the substrate to contact the source regions.

Abstract: A memory cell (110) has a plurality of floating gates (120L, 120R). The channel region (170) comprises a plurality of sub-regions (220L, 220R) adjacent to the respective floating gates, and a connection region (210) between the floating gates. The connection region has the same conductivity type as the source/drain regions (160) to increase the channel conductivity. Therefore, the floating gates can be brought closer together even though the inter-gate dielectric (144) becomes thick between the floating gates, weakening the control gate's (104) electrical field in the channel.

Abstract: A twin-ONO-type SONOS memory includes a semiconductor substrate having a source region, a drain region and a channel region between the source and drain regions, twin silicon oxide-silicon nitride-silicon oxide (ONO) dielectric layers, a first ONO dielectric layer being on the channel region and the source region and as second ONO dielectric layer being on the channel region and the drain region, and a control gate on the channel region, between the twin ONO dielectric layers, the twin ONO dielectric layers extending along at least lower lateral sides of the control gate adjacent the channel region, wherein the twin ONO dielectric layers extend towards the source and drain regions further than the control gate.

Abstract: A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.

Abstract: A vertical trench transistor has a first electrode, a second electrode and also a semiconductor body arranged between the first and second electrodes, there being formed in the semiconductor body a plurality of transistor cells comprising source region, body region, drift region and gate electrode and also contact holes for making contact with the source and body regions, contact being made with the source and body regions by means of the first electrode, and at least the bottom of each contact hole adjoining at least one drift region, so that Schottky contacts between the first electrode and corresponding drift regions are formed at the bottoms of the contact holes. The dimensions and configurations of the body regions or of the body contact regions optionally arranged between body regions and contact holes are chosen in such a way as to avoid excessive increases in electric fields at the edges of the contact hole bottoms.

Abstract: A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween.

Abstract: An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and the p channel MIS transistor are simultaneously formed by patterning ruthenium film deposited on a gate insulator. Next, by introducing oxygen into each of the gate electrodes, the gate electrodes are transformed into those having high work function. Thereafter, by selectively reducing the gate electrode of the n channel MIS transistor, it is transformed into a gate electrode having low work function.

Abstract: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Abstract: Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. Second spacers are disposed on sidewalls of the first spacers and on exposed sidewalls of the first contact pads. Second contact pads are disposed on the first contact pads.

Abstract: The present invention provides a novel method for increasing the amount of deuterium incorporated into trap sites of a transistor device during a deuterium passivation anneal by electrically pre-stressing the fabricated device prior to a deuterium anneal. The method of the present invention equally applies to SOI and CMOS technology. As a result, the incorporation of more deuterium during a deuterium anneal in the process flow reduces the number of undesirable trap sites.

Abstract: In a semiconductor device, a gate electrode, an impurity diffused region, a body potential fixing region, a first insulator, and a dummy gate electrode are provided on top of an SOI substrate consisting of an underlying silicon substrate, a buried insulator, and a semiconductor layer. The impurity diffused region is a region formed by implanting an impurity of a first conductivity type into the semiconductor layer around the gate electrode. The body potential fixing region is a region provided in the direction of an extension line of the length of the gate electrode and implanted with an impurity of a second conductivity type. The first insulator is formed at least in the portion between the body potential fixing region and the gate electrode. The dummy gate electrode is provided on the first insulator between the body potential fixing region and the gate electrode.

Abstract: A thin film transistor is disclosed comprising a substrate, a dielectric layer, and a semiconductor layer. The semiconductor layer, which is crystalline zinc oxide preferentially oriented with the c-axis perpendicular to the plane of the dielectric layer or substrate, is prepared by liquid depositing a zinc oxide nanodisk composition. The thin film transistor has good mobility and on/off ratio.

Abstract: Disclosed are embodiments of a field effect transistor that incorporates an elongated semiconductor body with a spiral-shaped center channel region wrapped one or more times around a gate and with ends that extend outward from the center region in opposite directions away from the gate. Source/drain regions are formed in the end regions by either doping the end regions or by biasing a back gate to impart a preselected Fermi potential on the end regions. This disclosed structure allows the transistor size to be scaled without decreasing the effective channel length to the point where deleterious short-channel effects are exhibited. It further allows the transistor size to be scaled while also allowing the effective channel length to be selectively increased (e.g., by increasing the number of times the channel wraps around the gate). Also, disclosed are embodiments of an associated method of forming the transistor.

Abstract: The present invention provides a MOS transistor device for providing ESD protection including at least one interleaved finger having a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further includes at least one isolation gate formed in at least one of the interleaved fingers. The device can further include a bulk connection coupled to at least one of the source, drain and gate regions via through at least one of diode, MOS, resistor, capacitor inductor, short, etc. The bulk connection is preferably isolated through the isolation gate.

Abstract: A high-frequency noise isolation structure and a method for forming the same are provided. The noise isolation structure isolates a first device region and a second device region over a semiconductor substrate. The noise isolation structure preferably includes a sinker region substantially encircling a first device region, a buried layer underlying the first device region and joining the sinker region, a deep guard ring substantially encircling the sinker region, and a deep trench oxide region substantially encircling the sinker region. The isolation structure further includes a wide guard ring between the first and the second device regions. The sinker region and the buried region preferably have a high impurity concentration. Integrated circuits to be noise decoupled are preferably formed in the respective first and second device regions.

Abstract: A semiconductor integrated circuit comprising: a pair of MOS transistors which are formed in a same well on a semiconductor substrate and arranged adjacent to each other with a distance such that charge exchange between capacitances of respective drain diffusion layers is possible; and a wiring structure which is formed to apply differential signals to respective gates of the pair of MOS transistors and to apply a common potential to respective sources of the pair of MOS transistors.

Abstract: The channels of first and second CMOS transistors can be selectively stressed. A gate structure of the first transistor includes a stressor that produces stress in the channel of the first transistor. A gate structure of the second transistor is disposed in contact with a layer of material that produces stress in the channel of the second transistor.

Abstract: An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the dielectric layer and the buffer layer, and opens to the underlying layer. The hole includes a buffer layer portion at the buffer layer and a dielectric layer portion at the dielectric layer. At least part of the buffer layer portion of the hole has a larger cross-section area than a smallest cross-section area of the dielectric layer portion of the hole. The conformal barrier layer covers surfaces of the dielectric layer and the buffer layer in the hole. The hole is a via hole or a contact hole that is later filled with a conductive material to form a conductive via or a conductive contact.

Abstract: The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.

Abstract: In a semiconductor device having a WCSP type construction package, to increase inductance without increasing further an area conventionally occupied by a coil. A pseudo-post part 27 comprising a magnetic body is extended in a direction perpendicular to a main surface 12a of a semiconductor chip 12, on a second insulating layer 21 of a WCSP 10. A first conductive part 15a and a second conductive part 15b constructed as square frames are respectively provided so as to surround the pseudo-post part, on respective top surfaces of a second insulation layer and a third insulating layer 22 which are separated parallel to each other, in an extension direction of the pseudo-post part. A coil 100 being a substantially spiral shape conductive path is formed from, the first conductive part, the second conductive part, and a connection part 26 which electrically connects the one ends of the first and second conductive parts.

Abstract: A monolithic three dimensional memory array comprising Schottky diodes components separated by antifuses is disclosed. The Schottky diodes are vertically oriented and disposed on alternating levels. Those on odd levels are “rightside-up” with antifuse over the metal, and those on even levels are “upside down” with metal over the antifuse. Both antifuses are preferably grown oxides.

Abstract: A semiconductor diode (30) has an anode (32), a cathode (33) and a semiconductor volume (31) provided between the anode (32) and the cathode (33). An electron mobility and/or hole mobility within a zone (34) of the semiconductor volume (31) that is situated in front of the cathode (33) is reduced relative to the rest of the semiconductor volume (31).

Abstract: A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity type of a pinned photodiode.

Abstract: In a semiconductor device including a switching element and a fuse element which is connected in series with the switching element and which melts and blows out as a result of an electric current flowing therethrough when the switching element is placed in an electrically conducting state, in which an electrostatic breakdown protection circuit for preventing electrostatic breakdown is connected to a control line which applies a control signal for controlling the switching element, the effect of electrostatic noise can be reduced.

Abstract: A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor configured with a number of inductive coils. The inductor also includes a semiconductor material having a contact with at least a portion of at least one of the coils. The semiconductor material is doped to form a diode with a first doped region of first conductivity type, a second doped region of second conductivity type, and a depletion region. A voltage across the diode changes lengths of the first doped region, the second doped region and the depletion region, and adjacent coils in contact with at least one of the doped regions are electrically shorted, thereby varying the inductance of the inductor. In various embodiments, the inductor is electrically connected to a resistor and a capacitor to provide a tunable RLC circuit. Other aspects and embodiments are provided herein.

Abstract: A MOSFET device that includes a first Zener diode connected between a gate metal and a drain metal of said semiconductor power device for functioning as a gate-drain (GD) clamp diode. The GD clamp diode includes multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above the MOSFET device, having an avalanche voltage lower than a source/drain avalanche voltage of the MOSFET device wherein the Zener diode is insulated from a doped region of the MOSFET device for preventing a channeling effect.

Abstract: Provided are a nonvolatile memory device having multi bit storage and a method of manufacturing the same.

Abstract: Embodiments of the invention relate to the construction of a dual die package with a high-speed interconnect. A package is created having a first die on a first side of a base substrate and a second die on a second side of the base substrate in opposed relation to the first die. A first copper plated interconnect is plated to the base substrate. Second copper interconnects are formed to connect the first copper plated interconnect to the first and second dice, respectively, such that the first and second dice are interconnected.