Abstract: In a protective circuit for a converter having a plurality of phases, for each phase current of the phases, a signal proportional to the respective phase current is applied to a transformer circuit that, below and in the area of a limiting frequency, functions as a low-pass filter with the limiting frequency, and above the limiting frequency, functions as a divider. The outputs of the transformer circuit are applied to a maximum generator for forming the absolute value maximum. This maximum is fed to a comparator in which the maximum is compared to a reference value.

Abstract: A power limiting circuit for controlling the power of the incandescent lamp not to overrun the rated power limit includes a sampling circuit that consists of two resistors connected in parallel. A control chip compares the received sample voltage with the standard voltage then outputs control signal to drive the conduction of a SCR (silicon controlled rectifier) to change the inner states of contacts of a relay so as to further control the on/off between the input and the output. Based on this control process and technique, this invention prevents the employment of incandescent lamps having a greater power than power rating. Besides, a bi-operational amplifier circuit is used to fulfill the whole examination and control perfectly.

Abstract: A protection circuit for protecting a device from destructive electrical conditions, such as ESD, over-voltage, and over-current, while keeping the output impedance of the device's I/O lines to a minimum, and self-regulating power dissipation. The device may comprise a first protection circuit and a second protection circuit coupled to each of one or more I/O lines for providing a primary and a secondary level of protection, respectively, for the I/O lines. The first protection circuit of the device may combine the use of Schottky diodes for voltage clamping, with a current limiting device for self-regulating the power dissipation. The current limiting device may be operable to function as a small, low impedance resistor in a normal operating range and as a controlled power dissipater outside the normal operating range. The device may be a data acquisition device comprised in a data acquisition system.

Abstract: A method for adding and connecting a remotely operated SPDT relay to an electric power circuit of an AC appliance connected to a manually actuated electrical SPDT switch for integrating said AC appliance into an home automation network, each said relay and said SPDT switch includes a pole terminal and dual traveler terminals and said relay is similar to a shape and a size of an AC switch fit for installation into a standard electrical box.

Abstract: The present invention relates to suppressing wear and contamination of the electrode needle as well as effectively removing the electricity from a charged body. An electricity removal mode in which the electrode needle is applied with a high voltage to produce ions and a halt mode in which the electrode needle is halted are provided, that are alternatively selected based on a selection of a user. The halt mode includes a halt period during which the high voltage is not basically applied on the electrode needle. When a self discharge occurs by approach of a charged body in this halt period and an absolute value of current that flows through the resistance exceeds the first threshold value, the electricity removal operation is initiated in which the high voltage is applied on the electrode needle to produce ions. Subsequently, after a predetermined time period passes, for example, the electricity removal operation is terminated and the halt period is resumed.

Abstract: The present invention generally comprises an electrostatic chuck base, an electrostatic chuck assembly, and a puck for the electrostatic chuck assembly. Precisely etching a substrate within a plasma chamber may be a challenge because the plasma within the chamber may cause the temperature across the substrate to be non-uniform. A temperature gradient may exist across the substrate such that the edge of the substrate is at a different temperature compared to the center of the substrate. When the temperature of the substrate is not uniform, features may not be uniformly etched into the various layers of the structure disposed above the substrate. A dual zone electrostatic chuck assembly may compensate for temperature gradients across a substrate surface.

Abstract: A wet electrolytic capacitor that includes a plurality of anodes, cathode, and working electrolyte that is disposed in electrical contact with the anodes and current collector is provided. Any number of anodes may generally be employed, such as from 2 to 40, in some embodiments from 3 to 30, and in some embodiments, from 4 to 20. The anodes are thin and typically have a thickness of about 1500 micrometers or less, in some embodiments about 1000 micrometers or less, and in some embodiments, from about 50 to about 500 micrometers. By employing a plurality of anodes that are relatively thin in nature, the resulting wet electrolytic capacitor is able to achieve excellent electrical properties.

Abstract: A power distribution module includes a housing having multiple channels, and a plurality of buss bars received within the housing for distributing power between multiple electrical components. The buss bars have terminals that are selectively positionable within respective ones of the channels based on a predetermined arrangement of the electrical components.

Abstract: A strap holding structure (200) for an electronic device (100) includes a body (10), a strap holder (22) and a latching element (24). The body defines a receiving portion (12). The receiving porting has a side board (1242). The side board with the receiving portion cooperatively surrounds a space (1244). The strap holder has a pole (228) at one end thereof and two opposite feet (223) extending from another end thereof. A block (226) radially extends from a circumferential wall of the strap holder, and the side board is received in the space. The latching element forms two concave portions (244). Each foot engages with a corresponding concave portion. A stopper (246) perpendicularly protrudes from the latching element, and resists a wall of the receiving portion.

Abstract: An image display device having an image display panel, the image display device including: as a casing, a base part mountable on a horizontal surface, a rising part rising from the base part in a state of being inclined frontward at a predetermined angle, and a panel retaining part connected to an upper part of the rising part, the panel retaining part retaining the image display panel; and a speaker disposed in an upper surface of the base part with an acoustic output surface of the speaker facing upward, sound output from the speaker being reflected by the rising part.

Abstract: A portable storage device which is used by being connected to terminals of an external apparatus, comprises a main body of a rectangular cover case, in which an opening is formed at a front and a fit opening is formed in a wall; a rectangular terminal enclosure supported inside said main body of the cover case, and having a terminal portion at a front for connection with the external terminals, and having a fit portion which is formed in a wall so as to be opposed to said fit opening when inserted into said main body of the cover case; a circuit board which is supported in said terminal enclosure and provided with connector terminals at a front; a semiconductor memory device which is mounted on said circuit board, sealed with resin and connected to said connector terminals; and a fitting member which is inserted into said fit opening of said main body of the cover case so as to be fitted to said fit opening, and to be fitted to said fit portion of said terminal enclosure to thereby fix said main body of the c

Abstract: A video signal output control method in an information processing apparatus which being to be locked to an external unit by a lock mechanism, the video signal output control method includes detecting the state of the lock mechanism, and stopping the output of the video signal to the external unit, when the lock mechanism is in the unlocked state.

Abstract: According to one embodiment, an electronic device includes a housing including an opening, a partition wall which partitions an interior part of the housing into a first chamber and a second chamber which is opened to the outside through the opening, first and second heat generating parts mounted in the first chamber, a first heat radiation member located in the second chamber, a heat transfer member which transfers heat generated by the first heat generating part, a cooling fan which draws outside air and exhausts the air against the first heat radiation member, a second heat radiation member which is exposed to the outside of the housing and is thermally connected to the second heat generating part, and a cover covering the opening and the second heat radiation member. The cover forms a gap between the cover and the housing. The gap communicates with the second chamber.

Abstract: The invention provides a technique enabling an image of high quality to be displayed while decreasing an effect of an outside light proceeding toward a back surface of PDP through a through hole for mounting an electric circuit on a chassis. A flat panel display of the invention includes a display panel, a metallic chassis having a through hole and joints for connecting the back surface of the display panel and the chassis to each other. The joints are on the back surface of the display panel distant from each other in a predetermined direction, and one of the joints is arranged at a position corresponding to the through hole of the chassis.

Abstract: An electronic device is provided with an enclosure having a side wall in which vent holes are formed, a heat generator stored in the enclosure, a radiator disposed adjacent to the vent holes, a heat receiver thermally connected to the heat generator, a heat transmission member having one end thermally connected to the heat receiver and the other end thermally connected to the radiator, a fan disposed adjacent to the radiator to generate cooling air toward the radiator, and a seal member that seals a gap formed between the radiator and the side wall having the vent holes formed therein.

Abstract: A circuit device having superior mechanical strength at the interface between a circuit board and heat sink and superior efficiency for radiating heat from a circuit element to the heat sink through the circuit board. The circuit device includes the metal-based insulation board for installing the circuit element, and the heat sink, over which the insulation board is installed with a paste arranged therebetween. The insulation board has a projection arranged on the surface facing the heat sink along a peripheral portion. At least part of the projection contacts the heat sink through the paste layer.

Abstract: In a stacked mounting structure At least a pair of a first connecting terminal and a second connecting terminal is formed, and further, the stacked mounting structure includes a protruding electrode which is provided on at least any one of the first connecting terminal and the second connecting terminal, and an electroconductive paste which is formed on a side surface of an intermediate substrate, and which electrically connects the first connecting terminal and the second connecting terminal. The first connecting terminal and the second connecting terminal are exposed by a recess in a surface of the intermediate substrate. The first connecting terminal and the second connecting terminal are electrically connected via the protruding electrode and the electroconductive paste in the recess which is provided in the intermediate substrate.

Abstract: A case structure for card-type electronic product includes an intermediate frame having insertion slots spaced thereon; a lower cover connected to a lower side of the intermediate frame by lower hooking members upward inserted into the insertion slots, and each of the lower hooking members including two spaced latch legs; and an upper cover connected to an upper side of the intermediate frame by upper hooking members downward inserted into the insertion slots corresponding to the lower hooking members, and each of the upper hooking members including two laterally outward extended latch hooks. When the upper and lower covers are assembled to the upper and lower sides of the intermediate frame, the latch hooks of the upper hooking members are abutted on lower edges of the latch legs of the lower hooking members to firmly hold the lower cover to the upper cover in three directions.

Abstract: A flash-memory drive replaces a hard-disk drive using an integrated device electronics (IDE) interface. The flash drive has a printed-circuit board assembly (PCBA) with a circuit board with flash-memory chips and a controller chip. The controller chip includes an input/output interface circuit to an external computer over the IDE interface, and a processing unit to read blocks of data from the flash-memory chips. The PCBA is encased inside an upper case and a lower case, with an IDE connector that fits through and opening between the cases. The cases can be assembled with the PCBA by a snap-together, ultrasonic-press, screw-fastener, or thermal-bond adhesive method. Center lines formed on the inside of the cases fit between rows of flash-memory chips to improve case rigidity. The connector has two rows of pins that straddle the center line of the circuit board for a balanced design.

Abstract: An open-frame flash-memory drive has a printed-circuit board assembly (PCBA) with flash-memory chips, a controller chip, and a Serial AT-Attachment (SATA) connector soldered to it. The PCBA is only partially encased by left and right frames or by a U-shaped bracket frame. The frames have PCBA supports and guide posts that fit near edges of the PCBA. The frames do not cover the top and bottom of the PCBA, allowing chips on the PCBA to be ventilated by unblocked air flow. Screws that attach the PCBA to the frame have metal collars that ground the frame to the PCBA's ground plane. The screws form a current path to draw any electro-static-discharge (ESD) current off the frame and onto a PCBA ground. When the SATA connector is inserted into a host, the host ground sinks ESD currents collected by the open frame.

Abstract: A handheld computing device and handheld music player are disclosed. The handheld computing device includes a seamless enclosure formed from an extruded tube. The extruded tube includes open ends and internal rails which serve as a guide for slidably assembling an operational assembly through the open ends of the extruded tube, a reference surface for positioning the operational assembly relative to an access opening in the seamless enclosure, and a support structure for supporting the operational assembly during use. The handheld music player includes an elongated extruded tube extending along a longitudinal axis. The elongated extruded tube has a first open end and a second open end opposite the first open end, and defines an internal lumen which is sized and dimensioned for slidable receipt of operational components of the handheld music player. The lumen includes rails for guiding the operational components to their desired position within the lumen.

Abstract: A circuit board may include first and second sides, a plurality of circuit board layers between the sides, and a plurality of signal traces located in respective circuit board layers. The circuit board layers and the signal traces may extend from a first component connection region at the first side of the circuit board to a second component connection region at the first side of the circuit board. The signal traces may thus form stubless signal paths through the circuit board between the component connection regions. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A semiconductor device with an inductor device is small, thin, and low-cost. A laminated inductor is adhered fixedly onto a supporting conductive plate by Ag paste, and a semiconductor chip is adhered fixedly onto the laminated inductor via an insulating DAF tape. One end of the supporting conductive plate and a terminal electrode of the semiconductor chip are connected by a metal wire, and a plurality of terminal electrodes of the semiconductor chip and a plurality of external lead-out terminals are connected respectively by laterally extending metal wires. The entire structure is then sealed by a resin mold. By employing a laminated inductor and forming the metal wires to extend laterally in this manner, the thickness of the semiconductor device with an inductor can be reduced.

Abstract: An IC device has a compact design. Capacitors, resistances and inductances are directly integrated in the IC device without packaging in advance. Thus, the IC device obtained has a slim size and an electric apparatus using the IC device has a big space for use.

Abstract: A multilayer printed wiring board includes a mounting portion supporting a semiconductor device and a layered capacitor portion including first and second layered electrodes and a ceramic high-dielectric layer therebetween. The first layered electrode is connected to a ground line and the second layered electrode is connected to a power supply line. The ratio of number of via holes, each constituting a conducting path part electrically connecting a ground pad to the ground line of a wiring pattern and passing through the second layered electrode in non-contact, to number of ground pads is 0.05 to 0.7. The ratio of number of second rod-shaped conductors, each constituting a conducting path part electrically connecting a power supply pad to the power supply line of the wiring pattern and passing through the first layered electrode in non-contact, to number of power supply pad is 0.05 to 0.7.

Abstract: A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film. The second interconnection is connected to the first interconnection via the via. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via, and the second interconnection are formed. The wiring substrate includes a warpage-controlling pattern on the base insulating film, with a warped shape such that when the wiring substrate rests on a horizontal plate, at least a central part of a plane surface of the substrate contacts the horizontal plate, with both ends of the side raised.

Abstract: A structure of a latch for an interface card is disclosed. The latch includes a positioning set and a board. The positioning set has a pillar formed at a bottom portion thereof, a protruded frontage with a protruded jointing portion and a connecting portion connected to a limiter, wherein the pillar has a pin positioned at a bottom portion thereof. A first interface card is adapted into the first connector by pressing down the first interface card to be secured by the positioning structure; and a second interface card is adapted into the second connector by pressing down the second interface card to fit the two holes with the jointing portion, and the limiter is covered onto the jointing portion to let the buckling portion of the hole of the limiter support in the hole of the jointing portion to prevent the limiter from coming loose.

Abstract: An alignment system for a mezzanine-type printed circuit board is provided. The alignment system includes tab portions formed from the insulating material of the printed circuit board, in which the tab portions engage receptacles and limit movement of the printed circuit board.

Abstract: A riser card module includes a riser card and a mounting rack. The riser card is inserted in a slot of a main board vertically and has a first hook member arranged on the side of the slot. The mounting rack includes an upright board and an engagement member. The upright board mounts the riser card in parallel. The engagement member has a mounted portion, a force portion, and a hook portion. The mounted portion is mounted on the upright board. The force portion and the mounted portion form a predetermined angle. The hook member is connected on the force portion and has a second hook member hooking on the first hook member. When the force portion is pressed toward a direction reducing the predetermined angle, the second hook member is disengaged from the first hook member.

Abstract: An exemplary embodiment of the disclosure pertains to a high-voltage AC-DC converter converting alternating input current into high-voltage direct current to be provided to a load, e.g. for use of powering an electrostatic precipitator. The converter includes at least one unit for the conversion of the alternating (AC) input current into high frequency alternating (AC) current, at least one transformer for adapting the high frequency alternating (AC) current to requirements of the load. A series loaded resonant tank is provided between the at least one unit and the at least one transformer. Modularizing of the topology is achieved in that there are at least two units for the conversion of the alternating (AC) input current into high frequency alternating (AC) current connected to the same transformer.

Abstract: The subject invention reveals a new three terminal canonical cell for non-isolated power conversion. The canonical cell achieves reduced semiconductor component stresses for applications with limited line voltage range for small step up and step down ratios or for large step up and step down ratios. Some of the canonical cells can be used to form buck, boost, and buck boost converters. The new canonical cell achieves zero voltage switching over a broad range of line and load voltages and is self limiting without the addition of additional components to sense and respond to over load current.

Abstract: The switched mode power supply contains a transformer, which has a primary winding and at least one secondary winding, a switching transistor in series with the primary winding and a control circuit for controlling an output voltage of the switched mode power supply. The control circuit contains an oscillator, whose oscillation frequency can be set via a terminal, and which is coupled to a secondary winding of the transformer. The wiring for the terminal is connected such that the switched mode power supply starts up at a relatively low oscillation frequency once it has been connected, and, during operation when an additional voltage is supplied to the input via the secondary winding, the oscillation frequency of the switched mode power supply is increased. The terminal is connected in particular via a bandpass filter to a voltage generated by the secondary winding.

Abstract: A method and apparatus for reducing common mode noise in a three phase pulse width modulated (PWM) system, the method comprising the steps of receiving the first, second and third modulating waveforms, identifying one of the modulating waveforms that is at least one of instantaneously the maximum and instantaneously the minimum of the modulating waveforms as a first identified waveform, wherein comparison of the first identified waveform to the carrier signal would generate a first on-off pulse sequence associated with a phase corresponding to the first identified waveform, generating switch control signals associated with the phase corresponding to the first identified waveform that cause a modified on-off pulse sequence that is phase shifted from the first pulse sequence, using the second and third modulating waveforms to generate second and third on-off pulse sequences corresponding to the second and third phases and providing the modified pulse sequence and the second and third pulse sequences to the one

Abstract: A flyback converter with a leakage-inductance energy recycling circuit includes a transformer and a leakage-inductance energy recycling circuit. The leakage-inductance energy recycling circuit includes a clamping circuit, an energy storage circuit, and a switch connected between the clamping circuit and the energy storage circuit. A power transistor is electrically connected to a primary winding of the transformer. The clamping circuit clamps the voltage of the power transistor at a predetermined voltage. The energy storage circuit stores the leakage-inductance energy of the primary winding. When the switch is turned off, the clamping circuit receives and stores the leakage-inductance energy of the primary winding, so as to clamp the voltage of the power transistor to a predetermined voltage; when the switch is turned on, the energy stored in the clamping circuit is stored in the energy storage circuit through the switch.

Abstract: A value of an AC reference waveform is obtained and converted to a d-q reference frame value. A phase estimate is generated responsive to the d-q reference frame value. An AC output of the power supply apparatus is controlled responsive to an output current of the power supply apparatus and the phase estimate. For example, an output current value may be obtained and converted to a d-q reference frame current value responsive to the phase estimate, and the AC output may be controlled responsive to the d-q reference frame current value.

Abstract: A technique is presented for implementing a content addressable memory (CAM) function using traditional memory, where the input data is serially loaded into a serial CAM. Various additions, which allow for predicting the result of a serial CAM access coincident with the completion of serially inputting the data are also presented.

Abstract: A semiconductor memory device having dummy sense amplifiers and a method of utilizing the same are provided. Embodiments of the semiconductor memory device may include at least one dummy cell block including dummy cells and memory cells. Normal bit lines connecting the memory cells in the dummy cell block in a first direction and dummy bit lines connecting the dummy cells in the first direction. A dummy sense amplifier is also included for connecting any two of the normal bit lines and the dummy bit lines. Some of the embodiments may improve the sensing margin and refresh margin in sensing memory cells in the dummy cell, as well as increasing the redundancy efficiency and utilization of the dummy cells.

Abstract: Shunt regions are formed at certain intervals in a memory cell array region as extending in a second direction. The shunt regions each include a contact formed to connect a word line or a signal line wired in the same direction to another metal wire. Extension regions are each formed of an extension of the shunt region in the data cache array region. Data input/output lines extend in a first direction and transfer data on bit lines simultaneously via a data cache array. Sense circuits are arranged around the data cache array and connected to the data input/output lines respectively. The data input/output lines are divided at a certain interval in the first direction. The divided portions are connected to respective leads formed in the extension region in the longitudinal direction thereof and connected to the sense circuits via the leads.

Abstract: Embodiments for an area efficient high performance memory cell comprising a transistor connected to one of a bit line and a bit line bar are disclosed.

Abstract: According to an aspect of the invention, there is provided a nonvolatile ferroelectric memory, including a ferroelectric capacitor composed of a ferroelectric film sandwiched by capacitor electrodes made of a conductive material, a cell capacitor block stacked a plurality of the capacitor electrodes and the ferroelectric film of the ferroelectric capacitor perpendicular to a main surface of a silicon substrate in layer, a cell transistor having a drain electrode and a source electrode, the drain electrode and the source electrode are electrically connected to the ferroelectric capacitor in parallel, a memory cell composed of the ferroelectric capacitor and the cell transistor, a cell block having the plurality of memory cells electrically connected in series, the drain electrode and the source electrode being as a terminals, a word line, a bit line connected to one end of the cell block, the bit line being arranged along orthogonal direction to the word line and a plate line connected to the other end of the

Abstract: A memory includes at least one write bit line and a plurality of memory cells. The at least one write bit line is configured to carry a write bit signal. The plurality of memory cells are arranged in a column and are configured to be selectively coupled to the at least one write bit line. The plurality of memory cells are configured to be selectively read or written in a first phase of a cycle and selectively read or written in a second phase of the cycle using the at least one write bit line.

Abstract: A magnetic memory cell in which a sensor is magnetically coupled to a magnetic media wherein the separation of the magnetic media from the sensor permits each to be magnetically optimized separate from the other, thus improving defect tolerance and minimizing the magnetic influence of neighboring cells in an array on one another. In an embodiment, the read circuitry is positioned so that no read current passes through the media during a read operation. In an alternative embodiment, processing is simplified but the read current is allowed to pass through the media.

Abstract: A magnetic storage device with a significant reduction in power consumption. The magnetic storage device includes: a yoke which is arranged to cover part of a line extending in an arbitrary direction; and a magneto-resistive element which is arranged in contact with the yoke, thereby forming a closed magnetic circuit. The magneto-resistive element is capable of writing information with a field emanating from the yoke. The magnetic storage device satisfies Iw?a·R, where R is the magnetoresistance of the yoke, Iw is the write current necessary for the line, and a (mA·H)=6E?11.

Abstract: A spin-injection magnetic random access memory of an aspect of the present invention includes a magnetoresistive element, a unit which writes data into the magnetoresistive element by use of spin-polarized electrons generated by a spin-injection current and which applies, to the magnetoresistive element, a magnetic field of a direction of a hard magnetization of the magnetoresistive element during the writing.

Abstract: A resistance memory element includes an elementary body and opposing electrodes separated by at least a portion of the elementary body. The elementary body is preferably made of a strontium titanate-based semiconductor ceramic expressed by the formula: (Sr1?xAx)v(Ti1?yBy)wO3 (where A represents at least one element selected from the group consisting of Y and rare earth elements, and B represents at least one of Nb and Ta), and satisfies the relationships 0.001?x+y?0.02 (where 0?x?0.02 and 0?y?0.02) and 0.87?v/W?1.030. This semiconductor ceramic changes the switching voltage depending on, for example, the number of grain boundaries in the portion between the opposing electrodes.

Abstract: Circuit arrays having cells with combinations of transistors and nanotube switches. Under one embodiment, cells are arranged as pairs with the nanotube switching elements of the pair being cross coupled so that the set electrode of one nanotube switching element is coupled to the release electrode of the other and the release electrode of the one nanotube switching element being coupled to the set electrode of the other. The nanotube articles are coupled to the reference line, and the source of one field effect transistor of a pair is coupled to the set electrode to one of the two nanotube switching elements and the source of the other field effect transistor of the pair is coupled to the release electrode to the one of the two nanotube switching elements.

Abstract: A programming matrix switches of one of n logical inputs to one of j outputs. The programming matrix includes at least one layer system with multiple magnetic elements situated at selected locations, in which case, during and/or after the formation of the layer system, in the case of at least one of the elements, the magnetic and/or electrical properties thereof can be altered or are altered by means of intervention at least one layer of the element.

Abstract: The present invention provides a method for decreasing program disturb in memory cells, comprising: finding an initial programming condition that ensures programming memory cell normally; selecting two parameters from the initial programming condition as variables for a program disturb test; performing the program disturb test to the memory cell for at least two combined values of the variables; obtaining a programming condition with minimum program disturb based on the result of the program disturb test; and applying the programming condition with minimum program disturb as the programming condition for memory cell. The method according to the present invention can minimize the program disturb in memory cells and can be performed easily.

Abstract: A method for programming a memory, which includes multiple multi-level cells each having a left half cell and a right half cell, includes the following steps. First, a target address corresponding to 2n-group data to be stored is provided, wherein n is a positive integer. Next, the 2n-group data is sequentially programmed into the multi-level cells based upon the target address in a programming loop so that the data stored in the left half cells and the data stored in the right half cells are from different groups of the 2n-group data.

Abstract: The invention relates to a row decoder circuit for non volatile memory devices of the electrically programmable and erasable type, for example of the Flash EEPROM type having a NOR architecture. The proposed row decoder circuit allows to carry out the erasing step very quickly, for example with a granularity emulating at least 16 kB and even overcoming by at least 2 kB Flash memories of the NAND type. The memory can thus maintain high performances in terms of random access speed but shows a high erasing speed typical of memory architectures of the NAND type.