Abstract: A memory unit includes a plurality of first blocks each having a first block size. Each of the first blocks stores data of a plurality of second blocks each having a second block size which is smaller than the first block size. A control unit writes the data of the second block in the first block. The control unit is configured such that in a case where the second block to be written is a block that is to be written in the same first block as the second block that is already written in the first block, the second block to be written is written in the same first block even if an address of the second block to be written is not consecutive to an address of the second block that is already written in the first block.

Abstract: A flash memory device includes; a plurality of layers, each one including memory cells arranged in a matrix of rows and columns, a layer decoder configured to select one of the plurality of layers to thereby define a selected layer and an unselected layer, a voltage generator configured to generate an erase voltage at a level higher than ground voltage, and an internal voltage, and a row select circuit configured to apply the erase voltage to the selected layer, and apply at least one of the erase voltage and the internal voltage to the unselected layer during an erase operation.

Abstract: According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory cell transistor that is written the latest in each of the NAND cell units; and a processor that sets a read voltage based on the writing information to readout data from the memory cell transistors connected to a first word line; wherein a row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating data stored in a memory cell transistors.

Abstract: A nonvolatile semiconductor memory includes a plurality of word lines WL; a plurality of bit lines BL; memory cell transistors having a charge storage layer arranged in the column whose charge storage state is controlled by one of the word lines; memory cell transistor rows MSGm, MSGn functioning as select gate lines by injecting a charge into the charge storage layer of a memory cell transistor to form an enhancement mode transistor. Any one of a first select gate transistor or a second transistor, or both may be formed by a memory cell transistor functioning as a select gate transistor.

Abstract: A method for accessing, in reading, programming, and erasing a semiconductor-integrated non-volatile memory device of the Flash EEPROM type with a NAND architecture having at least one memory matrix organized in rows or word lines and columns or bit lines, and wherein, for the memory, a plurality of additional address pins are provided. The method provides both an access protocol of the asynchronous type and a protocol of the extended type allowing to address, directly and in parallel, a memory extended portion by loading an address register associated with the additional pins in two successive clock pulses. A third multi-sequential access mode and a parallel additional bus referring to the additional address pins are also provided to allow a double addressing mode, sequential and in parallel.

Abstract: Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.

Abstract: A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Abstract: A memory device is disclosed. A reference device of the memory includes a trimmable current source and a fixed current source. Currents provided by each source are summed to provide a reference current to a sense amplifier. The sense amplifier senses the state of a bit cell by comparing a current from the bit cell, representative of a logic value, to the reference current. By basing the reference current on both a fixed and a trimmable current source, the reference device can be trimmed to compensate for process and operating characteristics of the device, while maintaining a minimum reference current in the event of a disturb mechanism that results in loss of the current provided by the trimmable current source.

Abstract: An erase operation in a non-volatile memory includes selecting a block on which to perform an erase operation, erasing the selected block, receiving test data corresponding to the selected block, determining a soft program verify voltage level based on the test data, and soft programming the erased selected block using the soft program verify voltage level. A non-volatile memory includes a plurality of blocks, a test block which stores test data corresponding to each of the plurality of blocks, and a flash control coupled to the plurality of blocks and the test block, the flash control determining a soft program verify voltage level for a particular block of the plurality of blocks based on the test data for the particular block when the particular block is being soft programmed.

Abstract: Apparatus, systems, and methods may operate to receive an external read command at a control circuit coupled to a memory array. Individual wordline activation may be delayed according to a delay period determined by a read level voltage magnitude associated with a plurality of memory cells included in the array.

Abstract: In a memory cell programming method, first through n-th programming operations are performed to program first through n-th bits of the n bits of data using the plurality of threshold voltage distributions. The first through n-th programming operations are performed sequentially. A threshold voltage difference between threshold voltage distributions used in the n-th programming operation is less than or equal to at least one threshold voltage difference between threshold voltage distributions used in the first through (n?1)-th programming operations.

Abstract: A flash memory device is disclosed and includes; a memory cell array, a high voltage generating circuit generating a high voltage applied to a selected word line to select one or more memory cells in the memory cell array, and a controller. The controller cuts off a discharge path between the high voltage generating circuit and ground during a first period wherein the high voltage is not applied to a word line. The controller also deactivates the high voltage generating circuit during this first period.

Abstract: A memory architecture includes at least one matrix of memory cells of the EEPROM type organized in rows or word lines and columns or bit lines. Each memory cell includes a floating gate cell transistor and a selection transistor and is connected to a source line shared by the matrix. The memory cells are organized in words, all the memory cells belonging to a same word being driven by a byte switch, which is, in turn, connected to at least one control gate line. The memory cells further have accessible substrate terminals connected to a first additional line.

Abstract: A memory circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Configurations of the plurality of memory cells are determined depending on the data (“high” or “low”) which is stored in the memory cells. Data array such as a program stored in the memory circuit is analyzed in advance. In the case where “high” is the majority data, memory cells storing “high” are formed with vacant cells in which a semiconductor element is not formed.

Abstract: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.

Abstract: A memory device includes a delay circuit and a delay selection unit. The delay circuit delays a pulse signal to generate a delayed pulse signal. The pulse signal is used to generate a write enable signal and a read enable signal. The delay selection unit selects one of the delayed pulse signal output from the delay circuit in a test mode and the pulse signal in a normal mode.

Abstract: A semiconductor memory device is provided that is capable of detecting a short circuit defect to be detected in a memory array without causing an error due to off-current of a sense amplifier circuit. Sense amplifier circuits amplify a potential between a pair of bit lines, which occurs based on potential of memory cells selected by driving word lines and bit lines. Selection transistors are provided between the bit lines and the sense amplifier circuits. A word-SE interval control circuit included in an X timing generating circuit turns off the selection transistors and disconnects the bit lines from the sense amplifier circuits based on a signal representing a test state for expanded time when a test to expand an interval between word line driving and activation of the sense amplifier circuits and detect defect sites of the bit lines is performed.

Abstract: A non volatile memory device architecture, suitable for speeding up and synchronize the programming steps of the cells in particular of the Flash-Nor type, of the type comprising a matrix of memory cells organized into rows and columns, at least one group of these columns being selected by at least one first enable signal by a second enable signal generated by a first decoder; the group of columns being associated with at least one Program Load PL controlled by a logic circuit comprising a first centralized portion and plural second portions associated with a respective program load sequentially updated and driven in a synchronous way to the first centralized portion.

Abstract: A sense amplifier according to an example of the present invention has first, second, third and fourth FETs with a flip-flop connection. A drain of a fifth FET is connected to a first input node, and its source is connected to a power source node. A drain of a sixth FET is connected to a second input node, and its source is connected to the power source node. A sense operation is started by charging a first output node from the first input node with a first current and by charging a second output node from the second input node with a second current. The fifth and sixth FET are turned on after starting the sense operation.

Abstract: Embodiments of the present invention provide channel estimation for multi-level memories using pilot signals. A memory apparatus includes a memory block comprising a plurality of memory cells and adapted to operate with at least two levels of signals for writing data into and reading data from the memory cells. At least two memory cells are employed as reference cells to output a plurality of pilot signals. The memory apparatus also includes a channel block operatively coupled to the memory block, and adapted to facilitate the writing and reading of data into and from the memory cells. The channel block is also adapted to receive the pilot signals and determine one or more disturbance parameters based at least in part on the pilot signals and to compensate the read back signals based at least in part on the determined one or more disturbance parameters during said reading of data from the memory cells. Other embodiments may be described and claimed.

Abstract: A wear leveling method under limited system resources is provided, the wear levelling method is suitable for a non-volatile memory, the non-volatile memory is substantially divided into a plurality of blocks, and the blocks are at least grouped into a data area, a spare area and a substitution-transient area. The blocks within the data area may be divided into a plurality of lately-used blocks and a plurality of lately-unused blocks. The method includes only recording erase times of the lately-used blocks and blocks within the spare area and selecting a block used for the substitution-transient area is selected from the spare area according to a judgment condition of erase times of another block within the spare area plus a first threshold value. The method also includes performing a wear leveling procedure. Wherein, the selected block and the other block are selected in a random mode or a sequential mode.

Abstract: A memory system with a flexible serial interface and a memory accessing method thereof are provided. The memory system includes at least one of memories and a memory controller. The memory controller flexibly sets up serial link connection with each of the memories through serial ports regardless of a physical location and an order of the serial ports. The memory controller also transmits and receives memory data in a serial mode through the serial link connection.

Abstract: A semiconductor memory has a memory cell array having dynamic memory cells. An access control circuit accesses the memory cells in response to an access command which is supplied externally. A refresh control circuit generates, during a test mode, a test refresh request signal in synchronization with the access command so as to execute a refresh operation of the memory cells when a refresh mask signal is at an invalid level. Also, the refresh control circuit prohibits generation of the test refresh request signal when the refresh mask signal is at a valid level. The test refresh request signal is generated or prohibited from being generated according to the level of the refresh mask signal. Thus, only a refresh operation needed for a test can be executed, and hence test efficiency can be improved.

Abstract: A refresh control circuit in a semiconductor memory device includes a refresh controller, a voltage generator and a word line enable circuit. The refresh period controller generates a control signal in response to a self-refresh signal, the control signal indicating a nominal initiation of a refresh period. The voltage generator generates an output voltage in response to the control signal. The output voltage is boosted from a low voltage to a high voltage during the refresh period. The word line enable circuit generates a word line enable signal in response to the control signal, wherein the word line enable signal is activated following a delay after the nominal initiation of the refresh period, and the delay allows the voltage generator to fully boost the output voltage.

Abstract: Herein described is a method of implementing one or more native NMOS antifuses in an integrated circuit. Also described is a method for programming one or more native NMOS antifuses used within a memory device. The method further comprises verifying one or more states of the one or more native NMOS antifuses after the programming has been performed. In a representative embodiment, the one or more native NMOS antifuses are implemented by blocking the implantation of a dopant into a substrate of an integrated circuit. In a representative embodiment, an integrated circuit incorporates the use of one or more native NMOS antifuses. In a representative embodiment, the integrated circuit comprises a memory device, such as a one time programmable memory.

Abstract: This semiconductor memory device comprises a plurality of sub-arrays with a plurality of memory cells arranged in matrix form. Each local bit line is connected to a plurality of memory cells that are arranged in column direction in the sub-arrays. In addition, a global bit line is connected to the plural local bit lines. A column decoder is connected to the global bit line. The global bit line extends from the column decoder toward the plurality of sub-arrays, and it is cut before the furthest sub-array formed in the furthest region from that column decoder.

Abstract: Disclosed is a logic circuit which includes first and second MOS transistors which are connected in series between a first signal-input terminal and GND. The gates of the first and second MOS transistors are connected in common to a second signal-input terminal and a connection node between the drains of the first and second MOS transistors is connected to an output terminal. When the first and second MOS transistors are both in an off state, the output terminal is less than or equal to a low level.

Abstract: The present invention relates to a column decoder for low power consumption in a semiconductor memory apparatus. The semiconductor device according to the present invention includes a column select signal decoder, which has a driving voltage input node and uses a driving voltage, for producing a plurality of column select signals by decoding a column select control signal; and a driving voltage supply controller for controlling a supply of the driving voltage to the driving voltage input node.

Abstract: Disclosed is a method for controlling a time point for data output in a synchronous memory device, which varies a time point of an internal read command of the synchronous memory device, which is generated in response to an external read command according to the CAS latency of the synchronous memory device. In other words, the time point to generate the internal read command when CAS latency corresponds to 2N+2 (N=0, 1, 2, . . . ) is delayed by 1tCK as compared with the time point to generate the internal read command when CAS latency corresponds to 2N+1, and the 1tCK is a period of an external clock applied to the synchronous memory device.

Abstract: A method for retrieval of self-contained, autonomous ocean bottom seismic data acquisition units secured to a non-rigid, non-conducing cable, wherein the cable is retrieved over the trailing edge of a working vessel on the surface of the water so as to permit the cable to billow out in the water column behind the vessel, thereby reducing stress on the cable and permitting greater control in cable handling.

Abstract: Determination of in-situ rock yield stress state of a geological formation surrounding a borehole includes determining a profile for each of an axial effective, a radial effective, and a hoop effective stress within at least one axial plane containing a borehole axis. A predicted radial shear response radial profile is calculated from the effective stresses within the at least one axial plane. A measurement-based estimate of a shear response radial profile within the at least one axial plane is determined from measured data. A maximum radial distance at which a difference between the predicted and measurement-based shear response radial profiles is identified within the at least one axial plane as being greater than a difference threshold. The respective axial, radial, and hoop stresses, are determined at the identified maximum radial distance. The identified stresses are indicative of an in-situ yield stress state of the rock.

Abstract: This invention pertains to the extraction of the slowness dispersion characteristics of acoustic waves received by an array of two or more sensors by the application of a continuous wavelet transform on the received array waveforms (data). This produces a time-frequency map of the data for each sensor that facilitates the separation of the propagating components thereon. Two different methods are described to achieve the dispersion extraction by exploiting the time frequency localization of the propagating mode and the continuity of the dispersion curve as a function of frequency. The first method uses some features on the modulus map such as the peak to determine the time locus of the energy of each mode as a function of frequency. The second method uses a new modified Radon transform applied to the coefficients of the time frequency representation of the waveform traces received by the aforementioned sensors.

Abstract: The initial detection of a signal of interest in a data stream involves transmitting a signal received by a sonar or a radar to signal detection equipment wherein a signal of interest is characterized by a state model x(t) with values in a finite set {x1, . . . , xN}, to which there corresponds a finite set {?1, . . . , ?N} of N values of an observation variable ?, characteristic of this signal. To detect the signal of interest a detection criterion ?n(t) is simultaneously calculated in two different ways. The larger of the two calculated values is assigned to the criterion of ?n(t) which is then compared with a detection threshold.

Abstract: Method for locating an impact on a surface (9), in which acoustic sensors (6) pick up acoustic signals ski (t) generated by the impact and the impact is located by calculating, for a number of reference points of index j, a validation parameter representative of a function: PRODkji1i2. . . i2P(?)=?Ski1(?) ?Rji1(?)*?Ski2(?)*?Rji2(?) . . . ?Ski2p(?)*?Rji2p(?) where: ?Ski(?) and ?Rji(?)* are complex phases of Ski(?) and of Rji(?), for i=i1, i2, . . . , i2p, indices denoting sensors, Ski(?) and Rji(?) being the Fourier transform of ski(t) and rji(t), rji(t) being a reference signal corresponding to the sensor i for an impact at the reference point j, p being a non-zero integer no greater than NSENS/2.

Abstract: A distance measuring system comprising: a transmitter that simultaneously emits an infrared radiation and an ultrasonic wave; and a receiver that include a table showing a relationship between an arrival time, indicative of a period from detection of the received infrared radiation to detection of the received ultrasonic wave, and a required received signal strength of the ultrasonic wave corresponding to the arrival time when the ultrasonic wave is directly received, that compares the received signal strength of the ultrasonic wave with a required received signal strength corresponding to the arrival time retrieved from the table, and that calculates the distance to the transmitter based on the arrival time when the received signal strength of the ultrasonic wave is higher than the required received signal strength corresponding to the arrival time retrieved from the table.

Abstract: A method for achieving omnidirectional transmission using of a towed linear antenna of length L greater than the wavelength ? of the signal transmitted. The antenna has a plurality of P projectors. The spacing between projectors is substantially less than ?/2. The method includes applying, to each projector, a transmit signal coming from a common transmit signal. The common signal is assigned a delay based upon a calculation that includes a non-linear term as a function of the position of the projector in the antenna, thereby allowing the angular aperture of the transmission pattern to be modulated. the method permits sonar detection systems comprising transmit and receive antennas having substantially identical diameters, which thereby can be reeled onto the same winch without it being necessary to separate them.

Abstract: A tamper resistant hourmeter is provided for an engine powered lawn mower. The hourmeter has a first pin connected to a positive voltage from a battery through a key actuated switch, a second pin to ground, a third pin to a magneto ignition, and a fourth pin to a fuel shutoff solenoid. The tamper resistant hourmeter connects the positive voltage from the battery to the fuel shutoff solenoid. The fuel shutoff solenoid opens a fuel line to the engine only if the key actuated switch is in either of the run or start positions.

Abstract: The invention concerns a timepiece including a dial (12) fitted with an aperture (16) behind which is mounted a moon phase disc (18) driven in rotation by a moon phase train (24). According to the invention said disc (18) is mounted so as to move in rotation about a fixed sun pinion (36). Moreover, two planetary wheels (44a, 44b), secured in rotation to representations of the moon (19a, 19b), are mounted so as to move in rotation on the disc (18), at least indirectly meshed with the sun pinion (36), so as to form a planetary train with the sun pinion (36).

Abstract: A time adjustment device having a reception unit that receives satellite signals transmitted from positioning information satellites; a time information generating unit that generates internal time information; a time information adjustment component that corrects the internal time information; and a reception controller that controls operation of the reception unit; wherein the satellite signal contains satellite time information that is kept by the positioning information satellite; the reception unit can select a first reception mode for receiving first information including the hour, minute, and second data in the satellite signal, and a second reception mode for receiving second information including the hour, minute, and second data, week information for the current year, month, and day, and satellite health information in the satellite signal; the time information adjustment component includes a time adjustment recording component that records whether or not the time was adjusted using the second infor

Abstract: Audio-centered information is stored on a unitary medium by a Table-of-Contents (TOC) mechanism for specifying an actual configuration of various audio items on the medium. In addition to the TOC mechanism a file-based access mechanism to the information is assigned through a ROOT directory that contains a highest level TOC directory pointing at various audio items.

Abstract: An optical pickup has a lens that is resiliently supported in such a manner as to be displaceable in different directions by pairs of a first wire, a second wire, and a third wire which are attached to a fixing portion by attaching means. The optical pickup includes a lens holder for holding the lens, and a printed circuit board secured to the lens holder. The first, second, and third wires have the same length and are formed of the same material, and are soldered to the printed circuit board at different distances from the attaching means.

Abstract: In a repetitive control device used for processing a servo signal, a memory (7) is used as a delay element for a filter (6), and a filtering process by the filter (6) is carried out using a clock signal that is an integral multiple of an operation frequency of a driving signal. Therefore, the gain can be increased without generating phase rotation with respect to a compensated signal, and high followability can be achieved to fluctuations in the track position which are caused by the shape of a disc such as decentering or surface wobbling, during recording and playback in an optical disc device.

Abstract: When “buffer under run” (BUR) occurs during recording of a visible image on an optical disk, recording operation is interrupted. As in the case of type A, when BUR1 occurs after data have been transferred through an integral multiple of one revolution, data are recorded continuously from a reference angle position without host device discarding data. As in the case of type B, when BUR2 occurs after data have been transferred in a value which is other than the integral multiple of one revolution, data corresponding to a duration from the position where BUR occurs to the start of the next revolution are discarded, data are continuously recorded from the reference angle position. Thereby, rendering can be spliced in a visually-smooth manner.

Abstract: A method and an apparatus for recording and/or reproducing data in which a recording and/or reproduction velocity is be reduced when a data recording and/or reproduction error occurs due to a defect of an optical disc during recording of data on and/or reproduction of data from the optical disc. The method includes: recording data on an optical disc that is rotating at a predetermined constant angular velocity; determining whether a data recording error occurs; and if it is determined that a data recording error has occurred, recording data on the optical disc that is rotating at a constant angular velocity which is lower than the predetermined constant angular velocity.

Abstract: An optical recording apparatus uses a method of searching for a recording power, where the method includes: searching for a first optimum recording power; recording data on an optical disc at the first optimum recording power; determining whether recording environments are changed when a user desires to re-record the data after recording the data in the optical recording apparatus; re-searching for the optimum recording power when the recording environments are changed, and determining the researched optimum recording power to be a second optimum recording power; and recording the data at the second optimum recording power.

Abstract: Disclosed herein are a high-density recording medium and a method and apparatus for controlling data playback thereof. Playback control information, such as channel bit length information, is recorded in a burst cutting area (BCA) of a high-density optical disc in a wobble type. When the high-density optical disc is reproduced, the playback control information is detected in a push-pull signal detection mode and the optimum data playback operation corresponding to the recording capacity of the optical disc is performed on the basis of the detected playback control information. Alternatively, bit error rates (BERs) are calculated while a plurality of predetermined bit detection modes are sequentially performed, one of the bit detection modes corresponding to the smallest one of the calculated BERs is selected and the data playback operation is performed in the selected bit detection mode.

Abstract: The method of detecting defect signals includes: setting a default pit length range; inputting a data signal including a plurality of pits with different pit lengths; transferring the data signal into NRZ signal and counting the pit length of each pit; accumulating the number of the pits whose pit length are within the default pit length range, and accumulating the number of the pits whose pit lengths are outside the default pit length range but within the corresponding ranges; changing the logic state of a defect flag signal when one of the accumulative value reaches a corresponding threshold. The present invention also provides an apparatus for detecting defect signals.

Abstract: The number of the layers of a disk is determined based on focus search to be performed after at least two kinds of spherical aberration correction quantities are set.

Abstract: A recording/reproducing apparatus is provided which can write continuously a file of large-capacity at high-speed. A record area of HDD is provided with a disk cache area for temporarily storing data to be written. The disk cache area is defined as a area that is not used by a host apparatus (3) in an LBA space, and the disk cache area is disposed in an area with a high transfer rate such as an outer circumferential area of a disk (10). A file transferred from the host apparatus (3) is written in the disk cache area, and the file is transferred from the disk cache area to a usual user area during an idle period to release the disk cache area and prepare for next transfer data write.

Abstract: A recording and reproducing system is broken down into a recording unit for producing a digital audio data signal from MIDI music data words asynchronously produced at irregular intervals and a playback unit for reproducing the MIDI music data codes from the digital audio data signal, wherein synchronous data nibbles are supplemented in the irregular intervals among the MIDI music data words for producing a data stream, and the digital audio data signal is produced from the data stream through a differential phase shift keying and a phase code modulation so as to record the MIDI messages in a digital versatile disk at high dense.