Abstract: [PROBLEMS] To provide an organic transistor in which high-resolution patterning can be performed, favorable contact can be achieved, and a leakage current can be prevented. [SOLVING MEANS] An organic transistor includes a substrate 1, a gate electrode 2 formed on the substrate 1, a gate insulating layer formed on the gate electrode 2, a source electrode 4 and a drain electrode 5 formed on the gate insulating layer 3, an organic semiconductor layer 6 provided between the source electrode 2 and the drain electrode 3 and opposite to the gate electrode 2 with the gate insulating layer 3 interposed between them, and an insulating layer 7 having an opening portion 7a which defines the area where the organic semiconductor layer 6 is formed. The organic semiconductor layer 6 is formed through evaporation by using a low-molecular organic semiconductor material such as pentacen.

Abstract: An organic EL element which has no layer that prevents penetration of holes and electrons to the counter electrode. The organic EL element includes: an anode, a hole injecting and transporting layer formed on the anode, a light emitting layer formed on the hole injecting and transporting layer, an electron injecting and transporting layer formed on the light emitting layer, and a cathode formed on the electron injecting and transporting layer. Ip2?Ip3 is established when an ionization potential of a constituent material for the light emitting layer is Ip2 and an ionization potential of a constituent material for the electron injecting and transporting layer is Ip3. Ea1?Ea2 is established when an electron affinity of a constituent material for the hole injecting and transporting layer is Ea1 and an electron affinity of the constituent material for the light emitting layer is Ea2.

Abstract: In one embodiment of the invention, a method of fabricating a SAM device comprises the steps of: (a) providing a substrate having a top surface and a first metal electrode disposed on the top surface, (b) annealing the first metal electrode, (c) forming a SAM layer on a major surface of the first electrode, the SAM layer having a free surface such that the SAM is disposed between the free surface and the major surface of the first electrode, and (d) forming a second metal electrode on the free surface of the molecular layer. Forming step (d) includes the step of (d1) depositing the second metal electrode in at least two distinct depositions separated by an interruption period of time when essentially no deposition of the second metal takes place. SAM FETs fabricated using this method are also described.

Abstract: An organic electroluminescent device (1) including: an emitting layer (14) between a pair of electrodes that are an anode (12) and a cathode (17), and a suppressing layer arranged between an electrode and the emitting layer (14), the suppressing layer regulating the amount of electrons or holes supplied to the emitting layer (14). For example, the electroluminescent device wherein the electron-injection-suppressing layer (15) or a hole-injection-suppressing layer is formed as the suppressing layer. The organic electroluminescent device is improved in emission efficiency.

Abstract: This organic field effect transistor comprises a semiconductor layer made of an organic semiconductor material. The mobility ?lsup of the charge carriers in the first portion of the semiconductor layer is X times greater than the mobility ?inf of the charge carriers in the second portion of the semiconductor layer, with the first portion corresponding to 10% of the volume of the semiconductor layer closest to the gate electrode and the second portion corresponding to 10% of the volume of the semiconductor layer closest to the drain and source electrodes.

Abstract: An organic light emitting device includes a transistor having gate, source, and drain electrodes, and first electrode connected to one of the source or drain electrodes. The device also includes an emitting layer positioned on the first electrode and a second electrode positioned on the emitting layer. Each of the source and drain electrodes includes first, second, and third layers having different tapered angles. The first electrode may include a metallic layer and a conductive layer, with a tapered angle of the metallic layer being different from a tapered angle of the conductive layer.

Abstract: A light-emitting element is disclosed that can drive at a low driving voltage and that has a longer lifetime than the conventional light-emitting element, and a method is disclosed for manufacturing the light-emitting element. The disclosed light-emitting element includes a plurality of layers between a pair of electrodes; and at least one layer among the plurality of layers contains one compound selected from the group consisting of oxide semiconductor and a metal oxide, and a compound having high hole transportation properties. Such the light-emitting element can suppress the crystallization of a layer containing one compound selected from the group consisting of oxide semiconductor and a metal oxide, and a compound having high hole transportation properties. As a result, a lifetime of the light-emitting element can be extended.

Abstract: Provided is a multi-layered memory apparatus including an oxide thin film transistor. The multi-layered memory apparatus includes an active circuit unit and a memory unit formed on the active circuit unit. A row line and a column line are formed on memory layers. A selection transistor is formed at a side end of the row line and the column line.

Abstract: The invention provides a multi-chip module. In one embodiment, the multi-chip module comprises a serial flash die and a primary die, and the primary die comprises a built-in self-test controller and a serial flash controller. The built-in self-test controller generates a write command to write first data to a memory location of the serial flash die, generates a read command to read second data from the memory location of the serial flash die, and compares the second data with the first data to determine whether the memory location is defective for generating failed address information about the serial flash die. The serial flash controller accesses the serial flash die according to the write command and the read command.

Abstract: A bottom-gate thin film transistor includes a gate electrode, a gate insulating layer and a microcrystalline silicon layer. The gate electrode is disposed on a substrate. The gate insulating layer is made up of silicon nitride and disposed on the gate electrode and the substrate. The microcrystalline silicon layer is disposed on the gate insulating layer and corresponds to the gate electrode, in which a contact interface between the gate insulating layer and the microcrystalline silicon layer has a plurality of oxygen atoms, and concentration of the oxygen atoms ranges between 1020 atoms/cm3 and 1025 atoms/cm3. A method of fabricating a bottom-gate thin film transistor is also disclosed herein.

Abstract: A thin film transistor includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode; a semiconductor layer which includes a plurality of crystalline regions in an amorphous structure and which forms a channel formation region, in contact with the gate insulating layer; a semiconductor layer including an impurity element imparting one conductivity type, which forms source and drain regions; and a buffer layer including an amorphous semiconductor between the semiconductor layer and the semiconductor layer including an impurity element imparting one conductivity type. The crystalline regions have an inverted conical or inverted pyramidal crystal particle which grows approximately radially in a direction in which the semiconductor layer is deposited, from a position away from an interface between the gate insulating layer and the semiconductor layer.

Abstract: A second insulation layer which is formed by stacking a plurality of layers made of different materials in a mutually contact manner is formed such that the second insulation layer covers a source region and a drain region and also covers a gate electrode from above. A first contact hole which reaches one of the source region and the drain region and a recessed portion which is arranged above the gate electrode but is not communicated with the gate electrode are simultaneously formed on the second insulation layer by dry etching. A first line layer is formed so as to cover the first contact hole. After forming the first line layer, a bottom surface of the recessed portion is etched by dry etching thus forming a second contact hole which reaches the gate electrode in the first and second insulation layers. A second line layer is formed on the second contact hole.

Abstract: It is an object to provide a flexible light-emitting device with long lifetime in a simple way and to provide an inexpensive electronic device with long lifetime using the flexible light-emitting device. A flexible light-emitting device is provided, which includes a substrate having flexibility and a light-transmitting property with respect to visible light; a first adhesive layer over the substrate; an insulating film containing nitrogen and silicon over the first adhesive layer; a light-emitting element including a first electrode, a second electrode facing the first electrode, and an EL layer between the first electrode and the second electrode; a second adhesive layer over the second electrode; and a metal substrate over the second adhesive layer, wherein the thickness of the metal substrate is 10 ?m to 200 ?m inclusive. Further, an electronic device using the flexible light-emitting device is provided.

Abstract: Provided may be a panel structure, a display device including the panel structure, and methods of manufacturing the panel structure and the display device. Via holes for connecting elements of the panel structure may be formed by performing one process. For example, via holes for connecting a transistor and a conductive layer spaced apart from the transistor may be formed by performing only one process.

Abstract: Improved thin film transistor array panels are provided. In one embodiment, a panel includes a plurality of gate lines, data lines, and a plurality of switching elements connected to the gate lines and the data lines. An interlayer insulating layer is formed between the gate lines and the data lines. A passivation layer covering the gate lines, the data lines, and the switching elements is also provided having a plurality of first contact holes exposing portions of the data lines, wherein the switching elements and the pixel electrodes are connected through the first contact holes. A plurality of contact assistants are formed on the passivation layer and are connected to the data lines through a plurality of second contact holes in the passivation layer. A plurality of auxiliary lines are connected to the data lines through a plurality of third contact holes in the interlayer insulating layer.

Abstract: A thin film transistor array comprising a substrate, a plurality of scan lines, a plurality of data lines, a plurality of thin film transistors, a plurality of common lines, a plurality of top electrodes, a plurality of connection lines and a plurality of pixel electrodes is provided. Wherein, each thin film transistor is disposed in one of the pixel areas and driven through the corresponding scan line and data line. Each thin film transistor includes a gate, a source and a drain. The drain of the thin film transistor is electrically connected to the corresponding top electrode by the corresponding connection line. Besides, the drain of the thin film transistor is electrically connected to the pixel electrode, and a portion of the connection line is not covered by the pixel electrode.

Abstract: Off current of a thin film transistor is reduced, and on current of the thin film transistor is increased, and variation in electric characteristics is reduced. As a structure of semiconductor layers which form a channel formation region of a thin film transistor, a first semiconductor layer including a plurality of crystalline regions is provided on a gate insulating layer side; a second semiconductor layer having an amorphous structure is provided on a source region and drain region side; an insulating layer with a thickness small enough to allow carrier travel is provided between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer is in contact with the gate insulating layer. The second semiconductor layer is provided on an opposite side to a face of the first semiconductor layer which is in contact with the gate insulating layer.

Abstract: A thin film transistor substrate that includes a substrate, first and second gate electrodes that are formed on the substrate, a gate insulating layer that is formed on the first and second gate electrodes, a first semiconductor and a second semiconductor that are formed on the gate insulating layer, and that overlap the first gate electrode and the second gate electrode, respectively, a first source electrode and a first drain electrode that are formed on the first semiconductor, and positioned opposed to and spaced from each other, a source electrode connected to the first drain electrode and a second drain electrode positioned opposed to and spaced from the second source electrode, wherein the second source and second drain electrodes are formed on the second semiconductor, and a pixel electrode that is electrically connected to the second drain electrode, a method of manufacturing the same, and a display apparatus having the same.

Abstract: The active-matrix substrate (100) of the present invention satisfies d2>d1 and d2+A1/2>d3+L1/2, where d1 is the length of the shortest line segment that connects together a channel region (134) and a gettering region (112) as measured by projecting the line segment onto a line that connects together the channel region (134) of a TFT (130) and a source contact portion, d2 is the distance from the channel region (134) to the source contact portion (132c), d3 is the distance from the channel region (134) to a first end portion (110a), L1 is the length of the first end portion (110a), and A1 is the length of the source contact portion (132c).

Abstract: Optical analysis system fluidically self-assembled using shape-coded freestanding optoelectronic components and a template having shape-coded recessed binding sites connected by an embedded interconnect network. Also includes methods of manufacture and use for optical analyses.

Abstract: A light emitting device according to an embodiment is provided. The light emitting device comprises a second electrode layer, a third conductive semiconductor layer comprising a schottky contact region and an ohmic contact region on the second electrode layer, a second conductive semiconductor layer on the third conductive semiconductor layer, an active layer on the second conductive semiconductor layer, a first conductive semiconductor layer on the active layer, and a first electrode layer on the first conductive semiconductor layer.

Abstract: The present invention relates to a packaging structure for high-power light emitting diode (LED) chip, comprising a metal plate, insulators and a cover plate. The metal plate comprises a containing slot and isolating slots formed on the surface by working, and the insulators can be embedded in the isolating slot. After forming a hollow slot and notches on the surface of the cover plate by working, the cover plate is combined with the metal plate and insulators and at the same time, the hollow slot and the notches are corresponding to the containing slot and the isolating slots on the metal plate to form a hollowness state, followed by application of surface treatment to form soldering portions and an anti-soldering layer at the bottom of the metal plate.

Abstract: The present invention is a semiconductor light source 100 for illuminating physical spaces including a lead frame with multiple facets 101. Each facet can have one or more semiconductor light emitting devices 108, such as LEDs, located on it. The light source is disclosed in threaded 100, surface mounted 400, and bar light 700 configurations.

Abstract: Disclosed are a light emitting device package and a light emitting apparatus. The light emitting device package comprises a package body comprising a light emitting surface inclined at an oblique angle with respect to a bottom surface, a plurality of lead electrodes in the package body, and at least one light emitting device electrically connected to the lead electrodes.

Abstract: A manufacturing method of a display device and a display device which can reduce the number of times that an insulation substrate is put into a CVD device and is taken out from the CVD device are provided.

Abstract: Embodiments relate to a semiconductor light emitting device and a light emitting apparatus comprising the same. The semiconductor light emitting device according to embodiments comprises a plurality of light emitting cells comprising a plurality of compound semiconductor layers; a plurality of ohmic contact layers on the light emitting cells; a first insulating layer on the ohmic contact layer; a second electrode layer electrically connected to a first light emitting cell of the light emitting cells; and a plurality of interconnection layers connecting the light emitting cells in series.

Abstract: A light output device comprises a substrate arrangement comprising first and second light transmissive substrates (1,2) and an electrode arrangement (3a,3b) sandwiched between the substrates. A plurality of light source devices (4) are integrated into the structure of the substrate arrangement and connected to the electrode arrangement. The electrode arrangement comprises an at least semi-transparent conductor arrangement of spaced non-transparent wires, the wires comprising a conductive ink.

Abstract: The present invention relates to an AC light emitting diode. An object of the present invention is to provide an AC light emitting diode wherein various designs for enhancement of the intensity of light, prevention of flickering of light or the like become possible, while coming out of a unified method of always using only one metal wire with respect to one electrode when electrodes of adjacent light emitting cells are connected through metal wires. To this end, the present invention provides an AC light emitting diode comprising a substrate; bonding pads positioned on the substrate; a plurality of light emitting cells arranged in a matrix form on the substrate; and a wiring means electrically connecting the bonding pads and the plurality of light emitting cells, wherein the wiring means includes a plurality of metal wires connecting an electrode of one of the light emitting cells with electrodes of other electrodes adjacent to the one of the light emitting cells.

Abstract: A semiconductor light emitting device of double hetero junction includes an active layer and clad layers. The clad layers include an n-type layer and p-type layer. The clad layers sandwich the active layer. A band gap energy of the clad layers is larger than that of the active layer. The band gap energy of the n-type clad layer is smaller than of the p-type clad layer.

Abstract: Provided is a nitride semiconductor light emitting element capable of producing an emission spectrum having two peaks with stable ratio of emission peak intensity. The nitride semiconductor light emitting 1 comprises an active layer 12 disposed between an n-type nitride semiconductor layer 11 and a p-type nitride semiconductor layer 13. The active layer 12 comprises a first well layer 14, second well layers 15 interposing the first well layer 14 and disposed at outermost sides among the well layers, and barrier layers 16, 17 disposed between each of the well layers. The second well layer 15 comprises a nitride semiconductor having a larger band gap energy than the band gap energy of a nitride semiconductor constituting the first well layer 14, and the nitride semiconductor light emitting element 1 has peaks in the emission spectrum respectively corresponding to the first well layer 14 and the second well layer 15.

Abstract: The present disclosure relates to a III-nitride semiconductor light-emitting device including a substrate with a first groove and a second groove formed therein, the substrate including a first surface and a second surface opposite to the first surface, a plurality of III-nitride semiconductor layers including a first semiconductor layer formed over the first surface of the substrate, a second semiconductor layer formed over the first III-nitride semiconductor layer, and an active layer disposed between the first and second III-nitride semiconductor layers and generating light by recombination of electrons and holes, a first opening formed on the first groove, a second opening formed on the second groove, a first electrode electrically connected from the second surface to the first III-nitride semiconductor layer through the first groove, and a second electrode electrically connected from the second surface to the second III-nitride semiconductor layer through the second groove and the second opening.

Abstract: The present invention provides a semiconductor light emitting device including a conductive substrate, a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer which are sequentially stacked, wherein an area where the first electrode layer and the first semiconductor layer are in contact with each other is 3 to 13% of an area of the semiconductor light emitting device.

Abstract: A side-view type light emitting diode package for emitting light, emitted from a light emitting diode chip, toward a side surface is disclosed. The side-view type light emitting diode package comprises a package body having an opening portion for exposing the light emitting diode chip in a light emitting direction; and a light-transmittable resin covering the light emitting diode chip, wherein at least a portion of an inner wall of the opening portion is formed with a step projection for partitioning the opening portion into upper and lower sections, and the lower section of the opening portion below the step projection is filled with the light-transmittable resin. Accordingly, the light-transmittable resin with the convex lens shape may be easily formed, so that the light emission efficiency thereof can be improved.

Abstract: The light-emitting display device comprises first and second thin film transistors. The first thin film transistor includes a first gate electrode; a first oxide semiconductor film; and a first electrode and a second electrode which are electrically connected to the first oxide semiconductor film. The second thin film transistor includes a second gate electrode electrically connected to the second electrode; a second oxide semiconductor film; a third electrode; a light-emitting layer and a fourth electrode over the second oxide semiconductor film. A work function of the second oxide semiconductor film is higher than a work function of the fourth electrode.

Abstract: An organic electroluminescent device includes a first substrate including a plurality of pixel regions; a thin film transistor on the first substrate and in each pixel region; a second substrate facing the first substrate; an organic electroluminescent diode on the second substrate and connected to the thin film transistor; a seal pattern at edges of the first and second substrates; and an adhesive layer including a plurality of conductive balls, an inner space defined by the first substrate, the second substrate and the seal pattern filled with the adhesive layer.

Abstract: Counter anions having oxidative properties alter the performance of solution processed multilayer polymer light emitting diodes (PLEDs) that use cationic conjugated polyelectrolytes (CPEs) as electron injection layers (EILs). In some versions, PLEDs with poly(2-methoxy-5-(2?-ethylhexyloxy)-1,4-phenylene vinylene) (MEH-PPV) emissive layers and cationic CPE EILs are altered with halide counter anions to exhibit a systematic increase in device performance. Exemplary oxidative counter anions are halide counter anions with F?>Cl?>Br?>I? in terms of device performance.

Abstract: The disclosure provides a light-emitting device comprising a substrate, an intermediate layer formed on the substrate, a first doped semiconductor layer with first conductivity-type formed on the intermediate layer, a second doped semiconductor layer with second conductivity-type formed on the first doped semiconductor layer, an active layer formed between the first doped semiconductor layer and the second doped semiconductor layer, and a patterned surface having a plurality of ordered pattern units; wherein the patterned surface is substantially not parallel to the corresponding region of the surface of the active layer.

Abstract: An improved structure of light emitting diode comprises that a copper clad laminate is made with a rectangular type slot thereon and a ring type slot on the outside boundary to enclose the rectangular type slot, while side wall of the slot form a natural guide angle with the surface of the copper clad laminate to further form an island type platform; a conductor being made between rectangular type slot and ring type slot is penetrated through the copper clad laminate and externally enclosed by the insulator thereby allowing conductor to be insulated; a light emitting diode chip is installed thereon; a fluorescent glue is optionally installed on the light emitting diode with a covering range smaller than the natural guiding angle of the rectangular type slot, wherein the copper clad laminate is installed on the printed circuit board.

Abstract: The invention is directed to providing a smaller semiconductor device having a light emitting element with a low manufacturing cost and a method of manufacturing the same. An adhesive layer 9 and conductive pastes 10a, 10b are selectively applied to a front surface of a semiconductor substrate 6. Then, a light emitting element (a LED die 4) is formed on the semiconductor substrate 6. A P type semiconductor layer 3 is connected to the conductive paste 10a, and an N type semiconductor layer 2 is connected to the conductive paste 10b. The LED die 4 is thus electrically connected to pad electrodes 8a, 8b through the conductive pastes 10a, 10b. Then, a protection layer 12 having openings in the positions corresponding to the pad electrodes 8a, 8b is formed on the semiconductor substrate 6. Electrode connection layers 13 and conductive terminals 14 are then formed on the pad electrodes 8a, 8b, 8c in the openings.

Abstract: Disclosed are a semiconductor light emitting device. The semiconductor light emitting device comprises a light emitting structure comprising a plurality of compound semiconductor layers, a passivation layer at the outside of the light emitting structure, a first electrode layer on the light emitting structure, and a second electrode layer under the light emitting structure.

Abstract: Provided an LED module comprising a metallic thin film having a flexibility; a circuit pattern printed on the metallic thin film so as to be insulated from the metallic thin film; one or more LEDs mounted on the metallic thin film on which the circuit pattern is not formed; wire for electrically connecting the LED and the circuit pattern; and a fluorescent body formed on the LED.

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The heat spreader includes a thermal post and a base. The thermal post extends upwardly from the base into a first opening in the adhesive, and the base extends laterally from the thermal post. The conductive trace includes a pad, a terminal and a signal post. The signal post extends upwardly from the terminal into a second opening in the adhesive.

Abstract: A material for a microlens having heat resistance, high resolution and high light-extraction efficiency is provided. A positive resist composition comprises an alkali-soluble polymer (A) containing a unit structure having an aromatic fused ring or a derivative thereof, and a compound (B) having an organic group which undergoes photodecomposition to yield an alkali-soluble group. The positive resist composition has coating film properties of a refractive index at a wavelength of 633 nm of 1.6 or more and a transmittance at wavelengths of 400 to 730 nm of 80% or more. A pattern forming method comprises applying the positive resist composition, drying the composition, exposing the composition to light, and developing the composition.

Abstract: A semiconductor device includes: a first semiconductor layer; a first electrode provided on a first surface side of the first semiconductor layer; a first insulating layer; and a second semiconductor layer. The first insulating layer is provided between the first semiconductor layer and the first electrode and configured to constrict current flowing between the first semiconductor layer and the first electrode. The second semiconductor layer has a first conductivity type and is provided at least on a path of the current constricted by the first insulating layer. The second semiconductor layer is in contact with the first electrode. The second semiconductor layer contains first impurities at a concentration higher than a concentration of impurities contained in the first semiconductor layer.

Abstract: Embodiments of detectors made using lattice matched photoabsorbing layers are disclosed. A photodiode apparatus in accordance with one or more embodiments of the present invention comprises an indium phosphide substrate, and a photoabsorbing region comprising at least an indium gallium arsenide antimonide nitride (InGaAsSbN) layer, wherein the InGaAsSbN layer has a thickness of at least 100 nanometers and is nominally lattice-matched to the indium phosphide substrate.

Abstract: An object of the present invention is to provide a ferroelectric element having excellent properties, which includes a monocrystalline film of ?-Al2O3 formed as a buffer layer on a silicon substrate. The monocrystalline ?-Al2O3 film 6 is formed on the silicon substrate 4 which is the lowermost layer of an MFMIS structure 2. On the monocrystalline ?-Al2O3 film 6, there is formed an electrically conductive oxide in the form of a LaNiO3 film 8 as a lower electrode. On the LaNiO3 film 8, there is formed a PZT thin film 10 which is a ferroelectric material. ON the PZT thin film 10, there is formed a Pt film as an upper electrode.

Abstract: There is provided a technique for reducing the occurrence of higher harmonics which occur from a field effect transistor, particularly a field effect transistor configuring a switching element of an antenna switch. In a transistor having a meander structure, the gate width of a partial transistor closest to a gate input side is increased. More specifically, a comb-like electrode is made longer than the other comb-like electrodes. In other words, a finger length is made greater than any other finger length. In particular, the comb-like electrode has the greatest length in all the comb-like electrodes.

Abstract: A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a <100> silicon layer, an insulator layer over the <100> silicon layer, and a P type conductivity <111> silicon layer over the insulator layer.

Abstract: An integrated circuit including a memory cell array comprises transistors being arranged along parallel active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines.

Abstract: Methods and devices yielding an improved semiconductor device with interface circuit are disclosed. Configuring a semiconductor with parallel device features reduces process variation (e.g., lithographically-induced process variation or other defects). Embodiments of the present invention provide semiconductor devices with I/O cell device features (e.g., I/O gates or core gates) laid out in parallel. Additionally, embodiments of the present invention can allow patterning devices to be made to more exacting tolerances because some patterning devices may have a higher capability along one axis than another. Embodiments of the present invention also include a semiconductor device having like-functioned I/O cells arranged such that their layouts and rotational orientations with respect to their corresponding core remain constant.