Abstract: A method is disclosed for controlling a semiconductor component which includes a voltage controlled gate. The method includes determining and storing, prior to use of the semiconductor component, reference values of a gate voltage to be given to the gate of the semiconductor component during a change of operating states. The method also includes providing a pulse width modulated voltage from a driver circuit to a resistor connected to the gate of the semiconductor component according to the stored reference values of the gate voltage when a change in operating states of the semiconductor component is desired.

Abstract: Photosensor circuits include a relay coil configured to control application of an alternating current (AC) power source to a load. The circuit includes a pulse width modulator circuit configured to generate a pulse width modulated signal having a pulse width that varies responsive to an average voltage across the relay coil. A drive transistor is coupled between the relay coil and a neutral bus that controls the average voltage across the relay coil responsive to the pulse width modulated signal. A photo control circuit is configured to control application of the pulse width modulated signal to the drive transistor responsive to a detected light level. A power circuit includes a half-wave rectifier coupled to the power source that is configured to provide a power signal to the pulse width modulator circuit and a regulated power signal to the photo control circuit.

Abstract: A keep alive circuit for recharging bootstrap capacitors in multiple totem-pole switching power stages using N-channel field effect transistor or NPN bipolar junction transistor switching devices during 100% or substantially 100% duty cycle operation of one of the totem pole pairs.

Abstract: Provided is a method of operating a semiconductor device, wherein an operating mode is set by adjusting timing of a voltage pulse or by adjusting a voltage level of the voltage pulse.

Abstract: An integrated circuit for a charge pump with a charge stage and a pump stage and a single High-Voltage PMOS (HVPMOS) transistor as the main switch for each stage and two times two minimum HVPMOS transistors in series as a bulk switch with fixed bulk connections, where the minimum HVPMOS transistors are smaller sized transistors than the transistors of the main switch. The bulk of the main switch is switched synchronously to the voltage node of the HVPMOS transistor of the main switch to force the bulk voltage (VB) to be equal or larger than either the source voltage (VS) or the drain voltage (VD). Two non-overlapping clock signals are used to trigger the HVPMOS transistors of the charge and pump stage.

Abstract: A charge pumping circuit comprises: a charging pump capacitance; a charging unit; a discharging unit; a detection resistor having one terminal and the other terminal, the one terminal being connected between a first node and a second node in a second mode; a voltage source for supplying a reference voltage to the other terminal of the detection resistor; a correction unit for correcting a charging current output from the charging unit and a discharging current that is to be sunk by the discharging unit to equalize the charging current and the discharging current in the second mode, based on a difference between a voltage of the one terminal of the detection resistor and the reference voltage when the charging unit outputs the charging current to the one terminal of the detection resistor and the discharging unit sinks the discharging current from the one terminal of the detection resistor.

Abstract: A voltage supply circuit includes a booster circuit and a ripple filter circuit. The ripple filter circuit has a first resistor connected to a first output terminal at one end thereof. The ripple filter circuit also has a first switch circuit connected between the other end of the first resistor and a second output terminal. In addition, the ripple filter circuit has a second switch circuit connected between the first output terminal of the booster circuit and the first switch circuit.

Abstract: A semiconductor integrated circuit (1) comprises a substrate voltage control circuit (10A), a drain current adjuster (E1), a MOS device characteristic detection circuit (20), and a drain current compensator (E2). The substrate voltage control circuit (10A) has at least one substrate voltage supply MOS device (m1) for controlling the supply of the substrate voltage of the semiconductor integrated circuit (1). The drain current adjuster (E1) adjusts the drain current of the substrate voltage supply MOS device (m1) by controlling the substrate voltage of the substrate voltage supply MOS device (m1). The MOS device characteristic detection circuit (20) has a characteristic detection device (m2) for detecting the characteristics of the substrate voltage supply MOS device (m1).

Abstract: There is provided an output stage circuit including such MOSTs (M) that when their gates and sources are respectively set to an equal voltage, subthreshold leakage currents substantially flow between their drains and sources, wherein upon its deactivation, a voltage is applied to the gate of each of the MOSTs (M) in such a manner than a reverse bias is applied between the gate and source of the MOST (M). That is, when the MOST (M) is of a p channel type, a voltage higher than that of a p type source is applied to its gate. When the MOST (M) is of an n channel type, a voltage lower than that of an n type source is applied to its gate. Upon activation of the circuit, the MOST is held in a reverse bias state or controlled to a forward bias state according to an input voltage. A CMOS circuit and a semiconductor device can be realized each of which is small in leakage current even though its threshold voltage is low and which is operated at high speed and with a small voltage amplitude.

Abstract: A circuit unit is provided. The circuit unit has an intermittent operation circuit. The intermittent operation circuit is set in an operation state and in a stand-by state periodically. An operation mode control unit generates a test mode control signal to designate either an operation test mode or an intermittent operation test mode of the intermittent operation circuit. The operation test mode corresponds to one of a continuous operation or a predetermined time period operation of the intermittent operation circuit. An operation timing generation unit receives the test mode control signal. The operation timing generation unit produces an operation control signal based on the test mode control signal. The operation control signal is outputted to the intermittent operation circuit to operate or wait the intermittent operation circuit.

Abstract: Multiple techniques are disclosed for hardening a self-clocking circuit against glitches. Glitch filters are placed in some portions of a digital design. In some embodiments the glitch filter is dynamically tunable. In one embodiment the inputs are locked out by the outputs. Methods for evaluating code symbols are presented, as is a circuit for differential signaling.

Abstract: Systems and methods for filtering analog signals corresponding to sensed parameters are provided. In this regard, a representative method includes: sampling the analog signal to acquire a sequential series of data points; determining a first cumulative change in value with respect to a first of the data points relative to at least two subsequent data points in the series, the subsequent data points including a second of the data points; determining a second cumulative change in value with respect to the second of the data points relative to at least two data points adjacent to the second of the data points in the series, the at least two adjacent data points including an immediately preceding and an immediately succeeding one of the data points relative to the second of the data points; comparing the first cumulative change and the second cumulative change to respective data thresholds; and outputting a filtered analog signal based, at least in part, on results of the comparing.

Abstract: An iterative method for generating a series of output signal values from a series of input signal values is described. Iterations of the method comprise the steps of obtaining a current input signal value for the current iteration, comparing the current input signal value with an output signal value determined in a previous iteration, updating a counter value determined in the previous iteration based on the result of the comparison between the current input signal value and the previous output signal value such that the updated counter value replaces the counter value determined in the previous iteration, determining a slew value based on the counter value; and adding the slew value to the previously determined output signal value to generate a new current output signal value. Thus different slew values may be added to the previous output signal to obtain a new output signal. The counter value is updated so that its value reflects recent trends in the input signals. E.g.

Abstract: An apparatus for generating a correction signal for linearizing an output signal of a non-linear element includes a correction signal generator. The correction signal generator is configured to generate a correction signal on the basis of a superposition of a digital reference signal and a superposed output signal. The superposed output signal is based on a superposition of the output signal and an analog reference signal.

Abstract: A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).

Abstract: In an A/D converter provided with an A/D converter circuit 101 for operationally amplifying an input signal and outputting an amplified signal, the A/D converter circuit 101 includes an initial value setting circuit 4a in addition to an amplifier 1a, a sub-A/D converter 2a, a sub-D/A converter 3a and capacitors C11 and C12. To ensure that the initial value of the output voltage of the amplifier 1a is a given voltage value close to the target value of operational amplification at the start of the operational amplification by the amplifier 1a, the initial value setting circuit 4a applies a given bias value equal to the given voltage value close to the target value to a next-stage capacitor C13 to be connected to the output side of the amplifier 1a. Such an A/D converter circuit 101 that can perform speedy convergence to the target value of operational amplification is used at each stage of a pipeline A/D converter.

Abstract: A lookup table generation method for a predistorter comprises sending a first single tone signal with a maximum expected amplitude to a channel simulation device including the power amplifier, estimating a closed loop gain and a closed loop phase of the power amplifier according to the first single tone signal and a first simulation output signal generated outputted by the channel simulation device, sending a plurality of single tone signals to the channel simulation device, each single tone signal having an amplitude different from all others of the plurality of single tone signals and lower than the maximum expected amplitude, generating a plurality of predistortion parameters according to the closed loop gain, the closed loop phase, the plurality of single tone signals and a plurality of simulation output signals outputted by the channel simulation device, and storing the plurality of predistortion parameters in a lookup table of the predistorter.

Abstract: Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.

Abstract: The present invention relates to a method for correcting for a source of non-linearity and noise introduced in a switching power amplification stage during power amplification of a pulse-modulated reference signal from a pulse modulator, where the method comprises the following steps: —providing an output stage embedded in an analogue self-oscillating control loop able to receive a pulse-referenced input signal; —generating a feedback signal from the switching power amplification stage or after a demodulation filter; —deriving an error signal by comparing the feedback signal with the reference signal; —filtering the error signal by a low pass filter for reducing the higher harmonics of the carrier; —adding a compensator for generating high loop gain in the audio band; —feeding the compensator output to a zero cross detector or comparator, thus providing a carrier for re-modulation or re-timing by feeding the filtered signal to a zero cross detector or comparator, which controls the output stage.

Abstract: An amplification apparatus comprising first amplification circuitry having first shunt-peak circuitry and second amplification circuitry having second shunt-peak circuitry, wherein the amplification apparatus is arranged to provide an operational bandwidth over which the first and second amplification circuitry amplify signals, and wherein the second shunt-peak circuitry is arranged to use at least part of the first shunt-peak circuitry.

Abstract: A current mirror circuit provided in an emitter follower configuration achieves linear output currents over a range of input currents by operating in response to a bias current that is a replica of the input current. The current mirror may include a pair of transistors and a pair of resistors, in which: a first resistor and a base of a first transistor are coupled to a first input terminal for a first input current, an emitter of the first transistor and a base of the second transistor are coupled to a second input terminal for a second input current, the first and second input currents being replicas of each other, an emitter of the second transistor being coupled to the second resistor, a collector of the second transistor being coupled to an output terminal of the current mirror, and a collector of the first transistor and the two resistors are coupled to a common node.

Abstract: The invention discloses a driving circuit system and a method of elevating a slew rate of an operational amplifier. The driving circuit system comprises an operational amplifier, a judging module and a bias enhancing module. The operational amplifier has an input stage driven by a bias current. The bias enhancing module is electrically connected to the judging module and the input stage of the operational amplifier respectively. The judging module is used to generate a bias enhancing signal according to an edge-trigger of a control signal. When the bias enhancing module receives the bias enhancing signal, the bias enhancing module provides an additional current, which cooperates with the bias current, for driving the input stage of the operational amplifier, so as to elevating a slew rate of the operational amplifier.

Abstract: An RF detector configured to provide two outputs, one being a function of the true RMS power level of an RF input signal, and the other being a function of the instantaneous/peak power of the RF input signal, normalized to the average power level. The RF detector includes a variable gain detection subsystem including a single detector or detector array that provides a representation of the power level of the RF input signal. The detector or detector array is common to both the RMS power detection channel and the instantaneous/peak power detection channel of the RF detector. A method of RF detection includes providing representations of the RF input signal at different gain levels, selecting one or more of the representations, and averaging the selected signals. The gain levels of the selected representations is adjusted to provide information about the average power level of the RF input signal.

Abstract: Aspects of a method and system for polar modulating OFDM signals with discontinuous phase may include amplifying a normalized OFDM signal via a plurality of amplifiers such that a combined gain of the plurality of amplifiers comprises a coarse amplitude gain and an amplitude offset gain. A gain of one or more of the plurality of amplifiers may be adjusted to set the coarse amplitude gain, and a gain of one or more remaining ones of the plurality of amplifiers may be adjusted to set the amplitude offset gain adaptively and/or dynamically. The setting of the coarse amplitude gain and/or the amplitude offset gain may be adjusted dynamically and/or adaptively via an amplitude control.

Abstract: An apparatus is provided. The apparatus includes an amplifier, differential amplifiers, and FETs. The amplifier has an intermediate node and an output node, and the amplifier is adapted to receive an audio signal. Each differential amplifier amplifies the difference between an output voltage from the output node with a reference voltages. The FETs are coupled in series with one another between a first and a second voltage, and each FET receives an output from at least one of the differential amplifiers. Additionally, the intermediate node is coupled to a node between at least two FETs.

Abstract: This invention provides a low-current consumption type signal amplification circuit, which limits the output voltage to fix a lower-limit (upper-limit) saturation voltage of the amplification circuit at a predetermined lower-limit (upper-limit) limiting voltage. The signal amplification circuit comprises a negative feedback amplification circuit, a lower-limit voltage limiting circuit and an upper-limit voltage limiting circuit. The lower-limit voltage limiting circuit increases a resistance between an output terminal of the negative feedback amplification circuit and a ground terminal when the output voltage of the negative feedback amplification circuit falls below the lower-limit limiting voltage. The upper-limit voltage limiting circuit increases a resistance between the output terminal of the negative feedback amplification circuit and a high-potential side of a power supply when the output voltage of the negative feedback amplification circuit rises above the upper-limit limiting voltage.

Abstract: Multiple unit transistors each having the same gate length are arranged in a gate-lengthwise direction to form a group of unit transistors. At least one unit transistor included in the group of unit transistors is used as a part of a gate bias circuit and acts as unit transistor (102) that is used for the bias circuit, and all of or part of the other unit transistors are connected in parallel and used as amplifier (101).

Abstract: A class G headphone amplifier circuit with improved power efficiency and low EMI. It may use an automatic signal level detector to detect the signal level of incoming signals and determine positive and negative power supplies for headphone amplifiers accordingly. A voltage generator may generate pairs of differential output voltages at a plurality of amplitude steps, and supply to headphone amplifiers the pair with the amplitude determined by the automatic signal level detector. As a result, headphone amplifiers are biased according to the input signal level, and the multiple voltage rails may improve power efficiency and avoid clipping.

Abstract: Apparatuses, methods, systems, algorithms, and circuits for reference clock frequency determination are disclosed. In one embodiment, a circuit for detecting a reference clock frequency can include a clock counter configured to count a number of cycles of the reference clock over a predetermined portion of a sleep clock to provide a reference clock cycle count, where the sleep clock has a known frequency and a predetermined accuracy; a frequency estimator configured to estimate the reference clock frequency from the reference clock cycle count and the known frequency of the sleep clock; and a frequency selector configured to select a closest frequency to the estimated reference clock frequency from a plurality of allowed frequencies.

Abstract: A technique for suppressing quantization noise generated due to digitizing an analog circuit in a PLL circuit is provided. The PLL circuit comprises: a digital phase frequency detector which detects (compares) phases and frequencies of a reference signal and a frequency-divided signal and converts the same to a digital value; a digital loop filter which eliminates high-frequency noise components from an output of the digital phase frequency comparator; a digital-analog converter which converts a digital value of an output of the digital loop filter to an analog value; an analog filter which eliminates a high-frequency noise component from an output of the digital-analog converter; a voltage controlled oscillator whose frequency is controlled based on an output of the analog filter; and a frequency divider which divides the frequency of the voltage controlled oscillator and outputs the frequency-divided signal.

Abstract: A phase noise correction device having a function for accurately detecting a phase noise component and capable of reducing a load on a reception device is provided. A phase noise correction device for correcting a phase noise generated in a local oscillator includes: a division section that divides a signal generated in the local oscillator; a reference signal generation section that generates a signal of the same frequency as that of the divided signal; a phase difference detection section that detects a phase difference between the divided signal and the generated reference signal; and a phase noise correction section that gives a phase rotation to a baseband signal in the direction that cancels the phase noise according to the detected phase difference as a phase noise component.

Abstract: An apparatus includes a filter and a gain control circuit. The filter receives and filters an input signal and provides an output signal in a first mode and operates as part of an oscillator in a second mode. The gain control circuit varies the amplitude of an oscillator signal from the oscillator in the second mode, e.g., by adjusting at least one variable gain element within the oscillator to obtain a target amplitude and/or non rail-to-rail signal swing for the oscillator signal. The apparatus may further include a bandwidth control circuit to adjust the bandwidth of the filter in the second mode. The bandwidth control circuit receives the oscillator signal, determines a target oscillation frequency corresponding to a selected bandwidth for the filter, and adjusts at least one circuit element within the filter to obtain the target oscillation frequency.

Abstract: Switch-modulation of a radio-frequency power amplifier by-representing the input signal by the I-signal (1) and Q-signal (9) of the complex components (I+j?Q), and pulse width modulating the I-signal and the Q-signal separately to create a modulated I-signal pulse sequence (3a) and a modulated Q-signal pulse sequence (3b). Further, the pulses corresponding to negative sample values are time-shifted relative the pulses corresponding to positive sample values, and each pulse of the I-signal pulse sequence is delayed by introducing a delaying time shift.

Abstract: A broadband active balun configuration is provided. According to embodiments, the subject active balun can include a cascade and cascade transistor pair using a shared input transistor. In a further implementation, a low-pass bias-feedback mechanism for maintaining stable bias conditions can be provided.

Abstract: According to one embodiment, a balun includes one or more transformers configured to block DC power between a line and a device at microwave frequencies. The one or more transformers block DC power between the line and the device by electromagnetically coupling the device to the line.

Abstract: A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.

Abstract: A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.

Abstract: A coaxial transition includes a first conductor aligned along a first axis. The transition also includes a ground shield surrounding the first conductor such that a first gap exists between the first conductor and the ground shield. An electric field radiates between the first conductor and the ground shield through the first gap. The transition further includes a second conductor aligned along a second axis and coupled to the first conductor. The second conductor forms a second gap between the second conductor and a portion of the ground shield. A first portion of the electric field radiates between the second conductor and the ground shield through the second gap. The transition also includes a top ground plane aligned substantially parallel to the second conductor. A third gap exists between the top ground plane and the second conductor. The second gap and the third gap are substantially parallel with the second conductor therebetween.

Abstract: There are provided a semiconductor device and a semiconductor chip, in which the interconnection is made to be highly reliable by stacking three or more layers of chips without contact therebetween. A semiconductor chip of the present invention comprises a first signal transmission circuit, a silicon substrate on which a first changeover switch is formed, and an interconnection layer on which a first capacitive-coupling upper electrode is formed, wherein a first capacitive-coupling lower electrode is additionally formed on the rear surface of the silicon substrate through a first via hole that penetrates the silicon substrate and, whereas the first capacitive-coupling upper electrode is directly connected to the first signal transmission circuit, the first capacitive-coupling lower electrode is connected to the first signal transmission circuit through the first via hole and through the first changeover switch.

Abstract: A directional coupler capable of improving a directionality of a directional coupler body including four terminals. The directional coupler includes a directional coupler body including the four terminals of an input port, an output port, a coupling port, and an isolation port; and a combiner for combining powers of an output signal of the coupling port and an output signal of the isolation port of the directional coupler body; and a directionality improving circuit for amplifying or attenuating at least one of the output signal of the coupling port and the output signal of the isolation port before outputting the same, and the combiner combines powers of the output signals amplified or attenuated by the directionality improving circuit.

Abstract: A surface acoustic wave filter comprised of a plurality of surface acoustic wave resonators having different resonance frequencies, the filter comprising a substrate made of a lithium niobate, comb electrodes (1201 and 1202) formed on the substrate, and a thin dielectric film covering the comb electrodes (1201 and 1202), wherein the surface acoustic wave resonator having a lower resonance frequency is formed to have a metallization ratio larger than a metallization ratio of the surface acoustic wave resonator having a higher resonance frequency, thereby providing the surface acoustic wave filter and an antenna duplexer featuring superior characteristics with insignificant ripples while suppressing spurious responses of the surface acoustic wave resonators.

Abstract: An apparatus for coupling a combline resonator and a ceramic resonator, including one or more of the following: a housing; a combline resonator in the housing; a ceramic resonator in the housing, the ceramic resonator having a stem portion and a mushroom portion; a ridge extending between the combline resonator and the ceramic resonator, the ridge passing between the mushroom portion of the ceramic resonator and the housing, wherein a coupling is obtained between an electrical field of the combline resonator and an electrical field of the ceramic resonator.

Abstract: A resonator having a three dimensional Defected Ground Structure (DGS) in the transmission line includes a substrate installed at the center of the resonator floating in the air through supporting members installed on both ends of the substrate; a transmission line for transmitting signals installed on the upper surface of the substrate; an upper ground plane member installed on the upper surface of the substrate with predetermined interval from the surface of the substrate, wherein a DGS pattern with a predetermined shape is formed on each portion of the body of the ground plane member symmetrically with respect to the transmission line to form a resonator; a lower ground plane member installed on the lower surface of the substrate with predetermined interval from the surface of the substrate, wherein a DGS pattern with a predetermined shape is formed on each portion of the body of the ground plane member symmetrically with respect to the transmission line to form a resonator; an upper cover installed closel

Abstract: A double tuned circuit includes: a primary tuning circuit connected to an input terminal; and a secondary tuning circuit connected to an output terminal. The primary tuning circuit has a primary capacitor connected between the input terminal and a ground and a primary inductor connected between the input terminal and the ground and formed of a first coupling line having a spiral shape. The secondary tuning circuit has a secondary capacitor connected between the output terminal and the ground and a secondary inductor connected between the output terminal and the ground and formed of a second coupling line having the same spiral shape as the first coupling line, arranged alternately with the first coupling line, and having an M-coupling with the first coupling line.

Abstract: A solenoid assembly includes a solenoid having a coil provided with a passageway and a plunger movable within the passageway upon application of electrical power to the coil. A frame holds the solenoid and includes a backstop movably mounted in the frame extending into the coil passageway. The backstop is selectively engaged by the plunger such that the backstop and the plunger are subjected to an impact therebetween. A resilient dampening element is positioned between the frame and the backstop for cushioning the impact between the backstop and the plunger.

Abstract: The invention refers to a solenoid with a coil which can be current-fed, the resulting magnetic field moving an armature. The armature acts, if necessary, on an actuator. Furthermore, the solenoid has at least one pyrotechnic actuation for the armature or the actuator.

Abstract: In one aspect, the present invention provides a dielectric fluid for use in electrical equipment comprising a vegetable oil or vegetable oil blend. In another aspect the invention provides devices for generating and distributing electrical energy that incorporate a dielectric fluid comprising a vegetable oil or vegetable oil blend. Methods of retrofilling electrical equipment with vegetable oil based dielectric fluids also are provided.

Abstract: A cladding (cover) element (32) includes a reception unit which is integrated therein. The reception unit contains a receiving coil (10) for the contactless transfer of electric energy and a plurality of flux-conducting elements (15a, 15b; 16a, 16b) that are associated with the receiving coil (10) for concentrating the field strength. The cover element (32) is made of a fiber-reinforced plastic. The flux-conducting elements (15a, 15b; 16a, 16b) and the receiving coil (10) are arranged in a base body (18) that is used to position the elements and coil and are embedded with the base body (18) in the cladding element (32). A process is also provided for producing the cladding element (32).

Abstract: A multiphase inductor assembly includes an elongate conductor assembly including a plurality of bus bars that are arranged in parallel. A plurality of magnetic core material rings (e.g., ferrite or mu metal rings) surround the conductor assembly and are distributed along a length thereof. Terminals are electrically coupled to the bus bars and disposed between spaced apart ones of the magnetic core material rings. In some embodiments, the conductor assembly, in cross-section, includes respective ones of the bus bars disposed in respective quadrants. For example, each of bus bars may have a quarter-cylinder shape and may be arranged such that the conductor assembly has a circular cross-section. In other embodiments, each of the bus bars may have a polygonal cross-section, e.g., may be formed from standard rectangular bar stock.

Abstract: A linear motor coil includes a first coil portion, a second coil portion, the first coil portion and the second coil portion being arranged across a partition wall, a first connecting portion provided between the first coil portion and the second coil portion and by means of which the conductive wire crosses to the first coil portion from the second coil portion while a winding direction of the conductive wire is reversed, and a second connecting portion by means of which the conductive wire crosses to the second coil portion from the first coil portion while the winding direction of the conductive wire is reversed. The conductive wire is formed by a single wire and of which a winding start point and a winding end point are provided at an end portion of the first coil portion at a side opposite from a side where the partition wall is provided.