Abstract: A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an under channel region formed under the channel region in the protruding structure and containing Si and Ge atoms, the Ge composition ratio among Si and Ge atoms contained in the under channel region continuously changing from the channel region side to the semiconductor substrate side; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film on the channel region.

Abstract: A display device includes an insulating substrate including a display region, at least one pad disposed in a non-display region on the insulating substrate which applies a voltage to the display region, a connecting part which is electrically connects at least two pads or at least two portions of the pad; and a power supply unit which applies the voltage to the pad.

Abstract: A light emitting device which is capable of suppressing deterioration by diffusion of impurities such as moisture, oxygen, alkaline metal and alkaline earth metal, and concretely, a flexible light emitting device which has light emitting element formed on a plastic substrate. On the plastic substrate, disposed are two layers and more of barrier films comprising a layer represented by AlNxOy which is capable of blocking intrusion of moisture and oxygen in a light emitting layer and blocking intrusion of impurities such as an alkaline metal and an alkaline earth metal in an active layer of TFT, and further, a stress relaxation film containing resin is disposed between two layers of barrier films.

Abstract: Provided is a 2-terminal semiconductor device that uses an abrupt MIT semiconductor material layer. The 2-terminal semiconductor device includes a first electrode layer, an abrupt MIT semiconductor organic or inorganic material layer having an energy gap less than 2eV and holes in a hole level disposed on the first electrode layer, and a second electrode layer disposed on the abrupt MIT semiconductor organic or inorganic material layer. An abrupt MIT is generated in the abrupt MIT semiconductor material layer by a field applied between the first electrode layer and the second electrode layer.

Abstract: An array substrate for a liquid crystal display device includes a substrate having a display area and a driving circuit area, a first semiconductor layer formed on the substrate in the display area, the first semiconductor layer having an active region and source and drain regions at opposing sides of the active region, a gate insulating layer formed on the first semiconductor layer, a gate electrode formed on the gate insulating layer and over the active region, the gate electrode being wider than the gate insulating layer, and an interlayer insulating layer formed over the substrate including the gate electrode, wherein the interlayer insulating layer, the gate electrode, the gate insulating layer, and the active region define a first cavity.

Abstract: A thin film transistor array panel for an X-ray detector includes a dummy pixel including a photo diode and a TFT for detecting leakage current. The photo diode includes first and second electrodes (178,195) facing each other and a photo-conductive layer (800) disposed between the first electrode and the second electrode. The TFT includes a semiconductor layer (150), a gate electrode (123), a source electrode (173) connected to a data line, a drain electrode (175) connected to the photo diode. The dummy pixel further includes a light blocking layer (196) for blocking light incident on the photo diode. Alternatively, the semiconductor layer is disconnected between the source electrode and the drain electrode.

Abstract: A CMOS imager having reduced dark current and methods of forming the same. A nitrided gate oxide layer having approximately twice the thickness of a typical nitrided gate oxide is provided over the photosensor region of a CMOS imager. The gate oxide layer provides an improved contaminant barrier to protect the photosensor, contains the p+ implant distribution in the surface of the p+ pinned region of the photosensor, and reduces photon reflection at the photosensor surface, thereby decreasing dark current.

Abstract: A thin film transistor array panel including a substrate, a gate line and a gate-layer signal transmitting line of a gate driving circuit portion formed on the substrate, a gate insulating layer formed on the gate line and the gate-layer signal transmitting line and having a first contact hole exposing a portion of the gate-layer signal transmitting line, a semiconductor layer formed on the gate insulating layer, a data line including a source electrode, and a drain electrode formed on the gate insulating layer and the semiconductor layer, a data-layer signal transmitting line of the gate driving circuit portion formed on the gate insulating layer and connected to the gate-layer signal transmitting line through the first contact hole, a pixel electrode connected to the drain electrode, and a passivation layer formed on the data line, the drain electrode, and the data-layer signal transmitting line of the driving circuit portion.

Abstract: It is an object of the present invention to manufacture a semiconductor device easily and to provide a semiconductor device whose cost is reduced. According to the present invention, a thin film integrated circuit provided over a base insulating layer can be prevented from scattering by providing a region where a substrate and the base insulating layer are attached firmly after removing a peeling layer. Therefore, a semiconductor device including a thin film integrated circuit can be manufactured easily. In addition, since a semiconductor device is manufactured by using a substrate except a silicon substrate according to the invention, a large number of semiconductor devices can be manufactured at a time and a semiconductor device whose cost is reduced can be provided.

Abstract: A new class of light emitting and laser diodes is disclosed wherein ballistic (without collisions) electron propagation along the nanotubes, grown normally to the substrate plane on the common metal electrode, provides conditions for the light emission from the nanotubes. The electrons, tunneling from the input contact into high energy states in the nanotubes, emit light via electron energy relaxation between the quantum energy levels existing in the nanotubes due to quantum size effect. In the disclosed devices, planar layer deposition technology is used to form a diode structure with two electrodes attached to the nanotubes ends.

Abstract: A TFT is manufactured using at least five photomasks in a conventional liquid crystal display device, and therefore the manufacturing cost is high. By performing the formation of the pixel electrode 127, the source region 123 and the drain region 124 by using three photomasks in three photolithography steps, a liquid crystal display device prepared with a pixel TFT portion, having a reverse stagger type n-channel TFT, and a storage capacitor can be realized.

Abstract: In an SiC vertical MOSFET comprising a channel region and an n-type inverted electron guide path formed through ion implantation in a low-concentration p-type deposition film, the width of the channel region may be partly narrowed owing to implantation mask positioning failure, and the withstand voltage of the device may lower, and therefore, the device could hardly satisfy both low on-resistance and high withstand voltage. In the invention, second inverted layers (41, 42) are provided at the same distance on the right and left sides from the inverted layer (40) to be the electron guide path in the device, and the inverted layers are formed through simultaneous ion implantation using the same mask, and accordingly, the length of all the channel regions in the device is made uniform, thereby solving the problem.

Abstract: An exemplary light emitting diode (LED) assembly includes a cover, a substrate, a LED unit, a first electrode terminal, and a second electrode terminal. The substrate includes a first surface and a second surface on an opposite side of the substrate thereto. The substrate and the cover cooperatively define a cavity. The LED unit is received in the cavity. The first and the second electrode terminals extend from the second surface. The first electrode terminal is electrically connected to one of a positive lead and a negative lead of the LED unit and the second electrode terminal is electrically connected to the other. The second electrode terminal includes a first electrode portion and a second electrode portion symmetrically arranged at opposite sides of the first electrode terminal. The first and the second electrode portions are at least partially symmetrical with respect to the first electrode terminal.

Abstract: A nitride semiconductor light emitting device including: a first nitride semiconductor layer, an active layer formed on the first nitride semiconductor layer and including at least one barrier layer grown under hydrogen atmosphere of a high temperature; and a second nitride semi conductor layer formed on the active layer, and a method of fabricating the same are provided. According to the light emitting device and method of fabricating the same, the light power of the light emitting device is increased and the operation reliability is enhanced.

Abstract: A micromechanical structure is described. A region of semiconductor material has a first surface, a second surface opposite to the first surface, and a lateral surface that surrounds the region of semiconductor material. Insulative material covers the first surface and the lateral surface of the region of semiconductor material to provide electrical isolation to the region of semiconductor material by forming a boundary. To form the micromechanical structure, a trench is etched in a semiconductor substrate to surround a region of the semiconductor substrate. A surface of the semiconductor substrate and the trench are oxidized to form a top oxide and a lateral oxide region. A backside of the semiconductor substrate is etched to expose a backside of the region of the semiconductor substrate and a portion of the lateral oxide.

Abstract: A light-emitting diode has: a substrate; a light-emitting layer having a first conductivity type cladding layer, an active layer, and a second conductivity type cladding layer stacked sequentially on a front side of the substrate; a first current-blocking portion partially formed in the middle on the light-emitting layer; a current-conducting portion formed on the second conductivity type cladding layer and the first current-blocking portion; a lower electrode formed on the back side of the substrate, a light-reflecting layer formed between the substrate and the light-emitting layer; a partial electrode formed on the surface of the light-reflecting layer and in a portion positioned below the first current-blocking portion; and a second current-blocking portion formed over the surface of the light-reflecting layer excluding the portion in which is formed the partial electrode.

Abstract: In accordance with the invention, an illumination device comprises a highly thermally conductive substrate having a surface, a plurality of light emitting diodes (LEDs) supported by the surface and arranged in an array to provide illumination. At least one reflective barrier at least partially surrounds each LED. The reflective barrier is shaped to reflect away from the LED light emitted by other LEDs in the array. Advantageously the LEDs and reflective barrier are thermally coupled to a heat spreader to dissipate heat generated by the LEDs. The substrate preferably comprises an LTTC-M heat spreader, and the reflective thermal barriers preferably comprise metal ridges or cups.

Abstract: A light emitting apparatus including a substrate, at least one light emitting diode chip mounted on the substrate, a light-transmitting member disposed on the substrate to form a space between the light-transmitting member and the substrate, and a resin disposed in the space to seal the light emitting diode chip, the light-transmitting member including at least one resin-injection inlet and at least one air vent, the space being filled with the resin injected into the space through the resin-injection inlet.

Abstract: A light source apparatus is configured to generate light efficiently from a light-emitting device. The light source apparatus includes a substrate having a pair of electrodes, a light-emitting device and a transparent resin for sealing the light-emitting device. A white resist layer is formed on the substrate. The white resist layer is formed to cover apart of the electrodes. The white resist layer 6 includes an opening corresponding to the light-emitting device. A white member for controlling a shape of the transparent resin is formed on the white resist layer.

Abstract: A light emitting diode includes a reflective cup, an LED chip, and many electrodes, a first light scattering layer, and a phosphor layer. The reflective cup includes a bottom and a sidewall extending from the bottom. The LED chip is received in the reflective cup and mounted on the bottom thereof for emitting first light of a first wavelength. The electrodes each has a first end electrically connected to the LED chip and an opposite second end exposed at an outer surface of the reflective cup. The first light scattering layer formed in the reflective cup on the bottom thereof and covering the LED chip, which has a concave surface at an opposite side thereof to the LED chip. The phosphor layer formed on the concave surface of the light scattering layer for converting part of the first light into second light of a second wavelength.

Abstract: A semiconductor light source for illuminating physical spaces can include a lead frame with multiple facets. Each facet can have one or more semiconductor light emitting devices located on it.

Abstract: An LED illumination device can include a bridge connection circuit that includes five LED chips. The LED chips can be installed such that four LED chips, through which half-wave rectified current flows, are disposed in a generally cross-shaped opposed arrangement with the remaining LED chip interposed therebetween. The remaining LED chip can also have a full-wave rectified current flowing therethrough. Half-wave rectified currents having phases shifted by 180° (half the period) can flow through respective LED chips installed at a generally right angle. The placement range for the five LED chips can be limited, and the LED chips can be sealed with a wavelength conversion material.

Abstract: A ZnO layer is provided which can obtain emission at a wavelength longer than blue (e.g., 420 nm) and has a novel structure. A transition energy narrower by 0.6 eV or larger than a band gap of ZnO can be obtained by doping S into a ZnO layer.

Abstract: There is provided a method of producing a thin GaN film-joined substrate, including the steps of: joining on a GaN bulk crystalline body a substrate different in type or chemical composition from GaN; and dividing the GaN bulk crystalline body at a plane having a distance of at least 0.1 ?m and at most 100 ?m from an interface thereof with the substrate different in type, to provide a thin film of GaN on the substrate different in type, wherein the GaN bulk crystalline body had a surface joined to the substrate different in type, that has a maximum surface roughness Rmax of at most 20 ?m. Thus a GaN-based semiconductor device including a thin GaN film-joined substrate including a substrate different in type and a thin film of GaN joined firmly on the substrate different in type, and at least one GaN-based semiconductor layer deposited on the thin film of GaN, can be fabricated at low cost.

Abstract: A silicon rectifier semiconductor device with selectable trigger and holding voltages includes a trigger element. A first well region of a first conductivity type formed within a semiconductor body. A first region of the first conductivity type is formed within the first well region. A second region of a second conductivity type is formed with the first well region. A second well region having the second conductivity type is formed within the semiconductor body adjacent the first well region. A third region of the first conductivity type is formed within the second well region. A fourth region of the second conductivity type is formed within the second well region. The trigger element is connected to the first region and alters a base trigger voltage and a base holding voltage into an altered trigger voltage and an altered holding voltage. A first terminal or pad is connected to the second region. A second terminal is connected to the third region, the fourth region, and the trigger element.

Abstract: One aspect of this disclosure relates to a memory cell. In various embodiments, the memory cell includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential line. The diode includes an anode, a cathode, and an intrinsic region between the anode and the cathode. A charge representative of a memory state of the memory cell is held across the intrinsic region of the diode. In various embodiments, the memory cell is implemented in bulk semiconductor technology. In various embodiments, the memory cell is implemented in semiconductor-on-insulator technology. In various embodiments, the diode is gate-controlled. In various embodiments, the diode is charge enhanced by an intentionally generated charge in a floating body of an SOI access transistor. Various embodiments include laterally-oriented diodes (stacked and planar configurations), and various embodiments include vertically-oriented diodes.

Abstract: An image sensor provides enhanced integration of transistor circuitry and photo diodes. The image sensor simultaneously improves resolution and sensitivity. An image sensor an a method for manufacturing prevents defects in a photo diode by adopting a vertical photo diode structure. An image sensor includes a substrate which may include at least one circuit element. A bottom electrode and a first conductive layer may be sequentially formed over the substrate. A strained intrinsic layer may be formed over the first conductive layer. A second conductive layer may be formed over the strained intrinsic layer. An upper electrode may be formed over the second conductive layer.

Abstract: A damascene approach may be utilized to form an electrode to a lower conductive line in a phase change memory. The phase change memory may be formed of a plurality of isolated memory cells, each including a phase change memory threshold switch and a phase change memory storage element.

Abstract: A semiconductor device includes a mask layer having openings on a substrate, a GaN-based semiconductor layer selectively formed on the substrate with the mask layer that serves as a mask, a gate electrode and either a source electrode or an emitter electrode formed on the GaN-based semiconductor layer, and a drain electrode or a collector electrode connected on a surface of the first semiconductor layer that faces the GaN-based semiconductor layer or an opposite side of the first semiconductor layer.

Abstract: A semiconductor device includes: a first semiconductor layer of p-type AlxGa1-xN (0?x?1); a second semiconductor layer of n-type AlyGa1-yN (0<y<1, x<y) formed on the first semiconductor layer; a control electrode formed on the second semiconductor layer; a first main electrode connected to the first semiconductor layer and the second semiconductor layer; and a second main electrode connected to the second semiconductor layer. An interface between the first semiconductor layer and the second semiconductor layer has a surface orientation of (1-101) or (11-20).

Abstract: An N-polar III-nitride heterojunction JFET which includes a P-type III-nitride body under the gate electrode thereof.

Abstract: An enhancement mode High Electron Mobility Transistor (HEMT) comprising a p-type nitride layer between the gate and a channel of the HEMT, for reducing an electron population under the gate. The HEMT may also comprise an Aluminum Nitride (AlN) layer between an AlGaN layer and buffer layer of the HEMT to reduce an on resistance of a channel.

Abstract: The object of the present invention is to provide a heterojunction bipolar transistor with high breakdown tolerance which can be manufactured at a high reproducibility and a high yield, the heterojunction bipolar transistor includes: a sub-collector layer; a collector layer formed on the sub-collector layer; a base layer formed on the collector layer; and an emitter layer, which is formed on the base layer and is made of a semiconductor that has a larger bandgap than a semiconductor of the base layer, in which the collector layer includes: a first collector layer formed on the sub-collector layer; a second collector layer formed on the first collector layer; and a third collector layer formed between the second collector layer and the base layer, a semiconductor of the first collector layer differs from semiconductors of the third collector layer and the second collector layer, and an impurity concentration of the second collector layer is lower than an impurity concentration of the sub-collector layer and hi

Abstract: The semiconductor device, which provides reduced electric current leakage and parasitic resistance to achieve stable current gain, is provided. A first polycrystalline semiconductor layer is grown on a p-type polycrystalline silicon film exposed in a lower surface of a visor section composed of a multiple-layered film containing a p-type polycrystalline silicon film and a silicon nitride film, while growing the first semiconductor layer on a n-type collector layer, and then the first polycrystalline semiconductor layer is selectively removed.

Abstract: In a nitride semiconductor based bipolar transistor, a contact layer formed so as to contact an emitter layer is composed of n-type InAlGaN quaternary mixed crystals, the emitter layer and the contact layer are selectively removed so that the barrier height with the emitter formed thereon is small, and the ohmic electrode contact resistance can be lowered on the InAlGaN quaternary mixed crystals, for example, so that a WSi emitter electrode becomes an eave. A base electrode is formed by a self-aligned process using the emitter electrode as a mask. By such a configuration, the distance between the emitter and the edge of the base electrode is sufficiently shortened, and the base resistance can be lowered. As a result, a bipolar transistor having favorable high-frequency characteristics can be realized.

Abstract: A multiple-gate transistor structure which includes a substrate, source and drain islands formed in a portion of the substrate, a fin formed of a semi-conducting material that has a top surface and two sidewall surfaces, a gate dielectric layer overlying the fin, and a gate electrode wrapping around the fin on the top surface and the two sidewall surfaces separating source and drain islands. In an alternate embodiment, a substrate that has a depression of an undercut or a notch in a top surface of the substrate is utilized.

Abstract: In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing.

Abstract: Using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise having a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.

Abstract: A protective structure for a semiconductor sensor integrated in a semiconductor substrate for use in a state that is in direct contact with a measuring medium has a semiconducting layer that is applied to the semiconductor substrate, a metal layer and an insulating layer. The insulating layer is disposed between the semiconducting layer and the metal layer and electrically insulates same.

Abstract: The present invention provides structures and methods for a transistor formed on a V-shaped groove. The V-shaped groove contains two crystallographic facets joined by a ridge. The facets have different crystallographic orientations than what a semiconductor substrate normally provides such as the substrate orientation or orientations orthogonal to the substrate orientation. Unlike the prior art, the V-shaped groove is formed self-aligned to the shallow trench isolation, eliminating the need to precisely align the V-shaped grooves with lithographic means. The electrical properties of the new facets, specifically, the enhanced carrier mobility, are utilized to enhance the performance of transistors. In a transistor with a channel on the facets that are joined to form a V-shaped profile, the current flows in the direction of the ridge joining the facets avoiding any inflection in the direction of the current.

Abstract: A CMOS image sensor (CIS) process is described. A semiconductor substrate is provided, and then a gate dielectric layer, a gate material layer and a thickening layer are sequentially formed on the substrate, wherein the thickening layer includes at least a hard mask layer. The thickening layer is defined to form a transfer-gate pattern, and then the transfer-gate pattern is used as an etching mask to pattern the gate material layer and form a transfer gate. Ion implantation is then conducted to form a PN diode in the substrate with the transfer-gate pattern and the transfer gate as a mask.

Abstract: A Schottky photodiode includes a semiconductor layer and a conductive film provided in contact with the semiconductor layer. The conductive film has an aperture and a periodic structure provided around said aperture for producing a resonant state by an excited surface plasmon in a film surface of the conductive film by means of the incident light to the film surface. The photodiode detects near-field light that is generated by at the interface between the conductive film and semiconductor layer the excited surface plasmon. The aperture has a diameter smaller than the wavelength of the incident light.

Abstract: This invention comprises plurality of edge illuminated photodiodes. More specifically, the photodiodes of the present invention comprise novel structures designed to minimize reductions in responsivity due to edge surface recombination and improve quantum efficiency. The novel structures include, but are not limited to, angled facets, textured surface regions, and appropriately doped edge regions.

Abstract: According to an aspect of the invention, there is provided a semiconductor device including a semiconductor substrate, a lower electrode film formed on the semiconductor substrate, a dielectric film formed on the lower electrode film, and an upper electrode film formed on the dielectric film, wherein the lower electrode film, the dielectric film and the upper electrode film construct a capacitor in a predetermined region on the semiconductor substrate, the dielectric film is separated from the upper electrode film outside the predetermined region, and the dielectric film is formed continuously with respect to an adjacent cell.

Abstract: A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line, and a floating channel layer comprising a N-type drain region, a P-type channel region and a N-type source region is formed on the insulating layer. Then, a ferroelectric layer is formed on the floating channel layer, and a word line is formed on the ferroelectric layer. As a result, the resistance state induced to the channel region is controlled depending on the polarity of the ferroelectric layer, thereby regulating the read/write operations of the memory cell array.

Abstract: A stacked film of a first insulation film being a silicon oxide film with an extremely low moisture content, and a second insulation film being a silicon oxide film with a higher moisture content than the first insulation film, therefore, with a low in-plane film thickness distribution rate is formed, and this is polished by CMP. Polishing is performed until the second insulation film is wholly removed directly above a ferroelectric capacitor structure and a surface of the first insulation film is exposed to some extent. At this time, surface flattening is performed for a top surface of a first portion in the first insulation film and a top surface of the second insulation film, and an interlayer insulation film constituted of the first insulation film and the second insulation film remaining on a second portion of the first insulation film is formed.

Abstract: An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.

Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.

Abstract: A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

Abstract: An embedded memory device solves the problem of the low reliability of the circuit due to the unstable power source. The embedded memory includes a metal-oxide semiconductor (MOS) capacitor and a metal-insulator-metal (MIM) capacitor to increase the stability of the power source ring to stabilize the voltage of the embedded memory and stabilize the voltage for the peripheral circuit of the embedded memory.