Abstract: Example embodiments relate to a semiconductor memory device and a method of forming the semiconductor memory device. The semiconductor memory device may include a first interlayer insulating layer on a semiconductor substrate. A bit line may be arranged in a first direction on the first interlayer insulating layer. A bit line contact pad may be disposed in the first interlayer insulating layer and electrically connected to the bit line. A storage contact pad may be disposed in the first interlayer insulating layer. A top surface of the bit line contact pad may be lower than a top surface of the storage contact pad.

Abstract: HfO2 films and ZrO2 films are currently being developed for use as capacitor dielectric films in 85 nm technology node DRAM. However, these films will be difficult to use in 65 nm technology node or later DRAM, since they have a relative dielectric constant of only 20-25. The dielectric constant of such films may be increased by stabilizing their cubic phase. However, this results in an increase in the leakage current along the crystal grain boundaries, which makes it difficult to use these films as capacitor dielectric films. To overcome this problem, the present invention dopes a base material of HfO2 or ZrO2 with an oxide of an element having a large ion radius, such as Y or La, to increase the oxygen coordination number of the base material and thereby increase its relative dielectric constant to 30 or higher even when the base material is in its amorphous state. Thus, the present invention provides dielectric films that can be used to form DRAM capacitors that meet the 65 nm technology node or later.

Abstract: Parallel plate tunable varactors having a bulk capacitance contribution to a total capacitance increased compared to a fringing capacitance contribution are disclosed. The contribution of the bulk capacitance to the total capacitance of an exemplary BST varactor is increased by increasing the area/perimeter ratio of the active region, thereby improving the tunability and other properties of the varactor. In an exemplary embodiment, an active region of the varactor has a lateral shape with a perimeter that is less than a perimeter of an equivalent area square. In various exemplary embodiments, the shape of the active region may be substantially circular or substantially octagonal. Methods for fabricating and designing such varactors are also disclosed.

Abstract: A nonvolatile semiconductor memory device capable of improving injection efficiency and simplifying manufacturing process is provided. The device comprises a memory cell having second conductive type of first impurity diffusion area and second impurity diffusion area on a first conductive type of semiconductor substrate, between the first and second impurity diffusion areas, a first laminate section formed by laminating a first insulating film, a charge storage layer, a second insulating film and a first gate electrode in this order from the bottom, and a second laminate section formed by laminating a third insulating film and a second gate electrode in this order from the bottom, wherein an area sandwiched between the first and second laminate sections is the second conductive type of a third impurity diffusion area having impurity density lower than that of the first and second impurity diffusion areas and not higher than 5×1012 ions/cm2.

Abstract: A semiconductor device includes: a semiconductor layer; an insulating film provided on the semiconductor layer; and a charge storage layer provided on the insulating film. The semiconductor layer has a channel formation region in its surface portion. The insulating film contains silicon, germanium, and oxygen. The charge storage layer is capable of storing charge supplied from the semiconductor layer through the insulating film. A method of manufacturing a semiconductor device includes: forming a silicon oxide film on a surface of a semiconductor layer; introducing germanium into the silicon oxide film; forming an insulating film containing silicon, germanium, and oxygen by heat treatment under oxidizing atmosphere; and forming a charge storage layer on the insulating film, the charge storage layer being capable of storing charge supplied from the semiconductor layer through the insulating layer.

Abstract: Embodiments relate to a semiconductor device. In embodiments, a semiconductor device may include a semiconductor substrate having isolation layers and a well region, a gate electrode formed within a trench having a predetermined depth in the well region, source/drain regions formed at both sides of the trench, respectively, an interlayer dielectric layer formed on the semiconductor substrate to have predetermined contact holes, and metal interconnections formed within the contact holes, respectively.

Abstract: A semiconductor device is fabricating using a photoresist mask pattern, and selectively removing portions of a liner nitride layer in a cell region and a peripheral circuit region. A modified FinFET is formed to reduce the influence of signals transmitted by adjacent gate lines in a cell region. A double FinFET and a substantially planar MOSFET are formed in a core region and in a peripheral region, respectively, concurrently with the formation of the modified FinFET.

Abstract: A semiconductor device includes: a semiconductor substrate including a first conductive type layer; a plurality of IGBT regions, each of which provides an IGBT element; and a plurality of diode regions, each of which provides a diode element. The plurality of IGBT regions and the plurality of diode regions are alternately arranged in the substrate. Each diode region includes a Schottky contact region having a second conductive type. The Schottky contact region is configured to retrieve a minority carrier from the first conductive type layer. The Schottky contact region is disposed in a first surface portion of the first conductive type layer, and adjacent to the IGBT region.

Abstract: To provide a thin film integrated circuit at low cost and with thin thickness, which is applicable to mass production unlike the conventional glass substrate or the single crystalline silicon substrate, and a structure and a process of a thin film integrated circuit device or an IC chip having the thin film integrated circuit. A manufacturing method of a semiconductor device includes the steps of forming a first insulating film over one surface of a silicon substrate, forming a layer having at least two thin film integrated circuits over the first insulating film, forming a resin layer so as to cover the layer having the thin film integrated circuit, forming a film so as to cover the resin layer, grinding a backside of one surface of the silicon substrate which is formed with the layer having the thin film integrated circuit, and polishing the ground surface of the silicon substrate.

Abstract: A magnetic random access memory (MRAM) cell comprises a MRAM device and a single crystal self-aligned diode. The MRAM device and the single crystal self-aligned diode are connected through a contact. Only one metal line is positioned above the MRAM device of the MRAM cell. A first and second spacers positioned adjacent to the opposite sidewalls of the contact define the size of the single crystal self-aligned diode. A first and second metal silicide lines are positioned adjacent to the first and second spacers, respectively. The single crystal self-aligned diode, defined in a silicon substrate, includes a bottom implant (BI) region and a contact implant (CI) region. The CI region is surrounded by the BI region except for a side of the CI region that aligns the surface of the silicon substrate. A fabrication method, a read method, two programming methods for the MRAM cell are also disclosed.

Abstract: A device structure is disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process was found to cause the gate oxide damage before. The present invention structure includes a semiconductor substrate having an active area and a termination area; numerous trench MOSFET cells disposed in the active area; numerous electrostatic discharge (ESD) diodes disposed above the semiconductor substrate in the termination area; and an insulation layer comprising Oxide/Nitride/Oxide (ONO) sandwiched between the ESD diodes and the semiconductor substrate. In one embodiment, the active area does not contain the ONO insulation layer.

Abstract: The invention provides a CMOS integrated circuit capable of carrying out an operation at a comparatively high supply voltage, comprising a first MOS type transistor having a drain profile to come in contact with a gate through a low concentration region having an impurity concentration which is equal to or lower than a predetermined concentration at a drain end, and a second MOS type transistor and transfer gate having the same polarity which is connected to a gate of the first MOS type transistor, wherein a gate voltage is applied to the gate of the first MOS type transistor through the second MOS type transistor and transfer gate to which a predetermined potential (a shielding voltage) is applied.

Abstract: Various semiconductor devices and methods of manufacture are employed. According to an example embodiment of the present invention, a MOS-compatible semiconductor device exhibits high channel mobility and low leakage. The device includes a channel region having a high-mobility strained material layer and a tunneling mitigation layer on the strained material layer to mitigate tunnel leakage. The strained material has a lattice structure that is strained to match the lattice structure of the tunneling mitigation layer. An insulator layer is on the tunneling mitigation layer, and an electrode is over the insulator and adapted to apply a voltage bias to the channel region to switch the device between conductive and nonconductive states. Current is transported in the conductive state as predominantly facilitated via the mobility of the strained material layer, and wherein tunneling current in the nonconductive state is mitigated by the tunneling mitigation layer.

Abstract: A power semiconductor device includes a P type silicon substrate; a deep N well in the P type silicon substrate; a P grade region in the deep N well; a P+ drain region in the P grade region; a first STI region in the P grade region; a second STI region in the P grade region, wherein the first and second STI region isolate the P+ drain region; a third STI region in the deep N well; a gate electrode overlying an area between the second and third STI regions and covering a portion of the second STI region; a gate dielectric layer between the gate electrode and the P type silicon substrate; a P well formed at one side of the third STI region; and a P+ source region in the P well.

Abstract: A semiconductor device and a fabrication method for the semiconductor device which can remove the sacrifice layer deposited on the semiconductor device surface in a short time and whose manufacturing yield can be improved are provided. The semiconductor device and the fabrication method for the semiconductor device includes a field effect transistor 4 including a gate electrode 1, a drain electrode 2, and a source electrode 3 formed on a semiconductor substrate; and a hollow protective film 5 for covering the gate electrode 1, the drain electrode 2, and the source electrode 3, and being provided on the semiconductor substrate 4A.

Abstract: A method for preventing arcing during deep via plasma etching is provided. The method comprises forming a first patterned set of parallel conductive lines over a substrate and forming a plurality of semiconductor pillars on the first patterned set of parallel conductive lines and extending therefrom, wherein a pillar comprises a first barrier layer, an antifuse layer, a diode, and a second barrier layer, wherein an electric current flows through the diode upon a breakdown of the antifuse layer. The method further comprises depositing a dielectric between the plurality of semiconductor pillars, and plasma etching a deep via recess through the dielectric and through the underlying layer after the steps of forming a plurality of semiconductor pillars and depositing a dielectric. An embodiment of the invention comprises a memory array device.

Abstract: The present invention discloses a small-pitch three-dimensional mask-programmable memory (SP-3DmM). It is an ultra-low-cost and ultra-high-density semiconductor memory. SP-3DmM comprises a mask-programmable memory level stacked above the substrate. This memory level comprises diodes but no transistors or antifuses. Its minimum line pitch is smaller than the minimum gate pitch of the substrate transistors.

Abstract: An SRAM semiconductor device includes: at least a first and a second field effect transistor formed on a same substrate, each of the transistors including a gate stack, each gate stack including a semiconductor layer disposed on a metal layer, the metal layer being disposed on a high-k dielectric layer located over a chemical region, wherein the metal layer of the first gate stack and the metal layer of the second gate stack have approximately a same work function, and wherein each channel region has approximately a same band gap.

Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. The semiconductor device may include a semiconductor substrate, a gate insulation layer and a gate electrode, a first spacer, a second spacer, an epitaxial pattern, and/or source/drain regions. The gate insulation layer and the gate electrode may be formed on the semiconductor substrate. The first spacer may be formed on sidewalls of the gate electrode. The second spacer may be formed on sidewalls of the first spacer. The epitaxial pattern may be formed between the second spacer and the semiconductor substrate such that an outside profile of the epitaxial pattern is aligned with an outside profile of the second spacer. The source/drain regions may include primary source/drain regions that are aligned with the first spacer. The primary source/drain regions may be formed in the epitaxial pattern and the semiconductor substrate.

Abstract: A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.

Abstract: Provided is a micro-mechanical structure and method for manufacturing the same, including a hydrophilic surface on at least a part of a surface of the micro-mechanical structure, so as to prevent generation of an adhesion phenomenon in the process of removing a sacrificial layer to release the micro-mechanical, wherein the sacrificial layer comes into contact with the surface of the micro-mechanical structure.

Abstract: A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate. A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed without removing the semiconductor monitor structure, by using the material layer as an etch protection layer. A mask for the method is also provided. The mask includes a clear area and a dark area. The dark area prevents a semiconductor monitor structure from being subjected to exposure so as to form a material layer covering the semiconductor monitor structure and prevent removal of the semiconductor monitor structure from the substrate while a part of a semiconductor structure is removed.

Abstract: A nano-resonating structure constructed and adapted to couple energy from a beam of charged particles into said nano-resonating structure and to transmit coupled energy outside the nano-resonating structure. A plurality of the nano-resonant substructures may be formed adjacent one another in a stacked array, and each may have various shapes, including segmented portions of shaped structures, circular, semi-circular, oval, square, rectangular, semi-rectangular, C-shaped, U-shaped and other shapes as well as designs having a segmented outer surface or area, and arranged in a vertically stacked array comprised of one or more ultra-small resonant structures. The vertically stacked arrays may be symmetric or asymmetric, tilted, and/or staggered.

Abstract: A semiconductor chip constituting an image pickup device is provided on a substrate and includes a connection terminal and an image pickup portion. A lens sheet having a lens portion is provided on the semiconductor chip. A groove is formed in at least the substrate to expose the connection terminal. A conductor pattern is formed in the groove and has one end electrically connected to the connection terminal.

Abstract: Apparatuses and methods directed to an integrated circuit package having an optical component are disclosed. The package may include an integrated circuit die having at least one light sensitive region disposed on a first surface thereof. By way of example, the die may be a laser diode that emits light through the light sensitive region, or a photodetector that receives and detects light through the light sensitive region. An optical concentrator may be positioned adjacent the first surface of the first die. The optical concentrator includes a lens portion positioned adjacent the light sensitive region and adapted to focus light.

Abstract: An electro-optical device includes semiconductor layers disposed between a first substrate and an electro-optical layer. The semiconductor layers are provided at positions corresponding to crossover regions of scanning lines and data lines. Island light shielding films are disposed between the second substrate and the electro-optical layer. The island light shielding films are isolated from each other and at least partially overlapping a corresponding one of the semiconductor layers in plan view.

Abstract: A thin-film semiconductor device comprises a temperature sensor formed of a thin-film semiconductor and sensing a temperature as current, and a current-voltage converter formed of a thin-film semiconductor and having temperature dependence in which its current-voltage characteristic is different from that of the temperature sensor. A temperature sensed by the temperature sensor is converted to a voltage by the current-voltage converter.

Abstract: A semiconductor device includes a semiconductor layer having a first conductivity type, a metal contact on the semiconductor layer and forming a Schottky junction with the semiconductor layer, and a semiconductor region in the semiconductor layer. The semiconductor region and the semiconductor layer form a first p-n junction in parallel with the Schottky junction. The first p-n junction is configured to generate a depletion region in the semiconductor layer adjacent the Schottky junction when the Schottky junction is reversed biased to thereby limit reverse leakage current through the Schottky junction. The first p-n junction is further configured such that punch-through of the first p-n junction occurs at a lower voltage than a breakdown voltage of the Schottky junction when the Schottky junction is reverse biased.

Abstract: A semiconductor device of unipolar type has Schottky-contacts (6) laterally separated by regions in the form of additional layers (7, 7?) of semiconductor material on top of a drift layer (3). Said additional layers being doped according to a conductivity type being opposite to the one of the drift layer. At least one (7?) of the additional layers has a substantially larger lateral extension and thereby larger area of the interface to the drift layer than adjacent such layers (7) for facilitating the building-up of a sufficient voltage between that layer and the drift layer for injecting minority charge carriers into the drift layer upon surge for surge protection.

Abstract: A semiconductor device includes a substrate of a first conductivity type, and a first semiconductor region that includes a plurality of sub-regions of the first conductivity type that have a first doping concentration and a further semiconductor region of a second conductivity type opposite to the first conductivity type. The further semiconductor region separates the sub-regions from each other and the first semiconductor region is located on the substrate. The semiconductor device further includes a second semiconductor region of the first conductivity type located on the first semiconductor region, a third semiconductor region of the second conductivity type located on the second semiconductor region, and a fourth semiconductor region of the first conductivity type located on the third semiconductor region.

Abstract: An integrated circuit including a memory cell and methods of manufacturing the integrated circuit are described. The memory cell includes a resistive memory element including a top contact, a bottom contact, and a carbon storage layer disposed between the top contact and the bottom contact. The memory cell operates at a voltage in a range of approximately 0.5V to approximately 3V, and at a current in a range of approximately 1 ?A to approximately 150 ?A.

Abstract: A semiconductor device of the present invention comprises: a substrate; a plurality of wiring layers formed over the substrate; a fuse formed in an uppermost one of the plurality of wiring layers; a first insulating film made up of a single film and formed on the uppermost wiring layer such that the first insulating film is in contact with a surface of the fuse; and a second insulating film formed on the first insulating film; wherein the second insulating film has an opening therein formed above a fuse region of the uppermost wiring layer such that only the first insulating film exists above the fuse region, the fuse region including the fuse and being irradiated with a laser beam when the fuse is blown.

Abstract: A semiconductor device includes a semiconductor substrate, and an electrical fuse including a first conductor including a first cutting target region, and a second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on the semiconductor substrate, wherein a flowing-out region is formed of the first conductor flowing toward outside between the first cutting target region and the second cutting target region in a condition of cutting the electrical fuse.

Abstract: A vertical BJT which has a maximal current gain for a photodiode area. According to embodiments, since the BJT can be formed together with the photodiode, and collector current flows up and down based on the double base structure, the magnitude of the current may be increased.

Abstract: A semiconductor device formed by decreasing thickness of a substrate by grinding, and performing ion implantation. In a diode in which a P anode layer and an anode electrode are formed at a side of a right face of an N? drift layer, and an N+ cathode layer and a cathode electrode are formed at a side of a back face of the N? drift layer, an N cathode buffer layer is formed thick compared with the N+-type cathode layer between the N?-type drift layer and the N+ cathode layer, the buffer layer being high in concentration compared with the N? drift layer, and low compared with the N+ cathode layer. When a reverse bias voltage is applied, a depletion layer is stopped in the middle of the N cathode buffer layer, and thus prevented from reaching the N+ cathode layer, so that the leakage current is suppressed.

Abstract: A semiconductor device includes a semiconductor element, a light-blocking region enclosing the semiconductor element, a plurality of contacts disposed in a staggered arrangement in a first region of the light-blocking region, and a linear contact formed to extend along at least a first direction in a second region of the light-blocking region differing from the first region.

Abstract: A method of fabricating a semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package may include one or more semiconductor die having die attach pads along a single side. The leadframe may include a plurality of elongated electrical leads, extending from a first side of the leadframe, beneath the die, and terminating at a second side of the leadframe adjacent to the bond pads along the single edge of the die. The leadframe may further include a dielectric spacer layer on the elongated leads. Spacing the semiconductor die from the elongated leads using the spacer layer reduces the parasitic capacitance and/or inductance of the semiconductor package formed thereby.

Abstract: A method of making a semiconductor device including a semiconductor chip having a plurality of pads, and a lead frame having a plurality of leads. Each of the plurality of leads has a mounting surface for mounting the semiconductor device, a wire connection surface having a thick portion, and a thin portion whose thickness is thinner than the thick portion. The length of each wire connection surface was furthermore formed shorter than the mounting surface, by arranging so that the thin portion of each lead dives below the semiconductor chip, securing the length of the mounting surface of each lead, a distance from the side face of the semiconductor chip to the side face of a molded body of the semiconductor device being shortened as much as possible, and the package size is brought close to chip size, with miniaturization of QFN.

Abstract: A semiconductor device includes: a semiconductor element; a metallic plate having a heat radiation surface; a terminal connecting to the element; and a resin mold covering the element, the plate and the terminal. The metallic plate provides an electrode of the semiconductor element. The heat radiation surface is capable of radiating heat generated in the element. The heat radiation surface and a part of the terminal are exposed from the resin mold. The resin mold includes a concavity/convexity portion between the heat radiation surface and the part of the terminal in order to lengthen a creepage distance therebetween. The concavity/convexity portion is disposed on a surface of the resin mold.

Abstract: A power QFN package includes signal leads, a die pad, support leads, and an adhesive for die bonding. These elements are encapsulated with a resin encapsulant. The lower parts of the signal leads are exposed from the resin encapsulant to function as external electrodes. A middle part of the die pad is formed at a higher level than a peripheral part thereof. This permits the formation of through holes in a thin part of the die pad. This enhances the degree of flexibility in the size of a semiconductor chip and the moisture resistance thereof.

Abstract: A power semiconductor component stack, using lead technology with surface-mountable external contacts, includes at least two MOSFET power semiconductor components each having a top side and an underside. The underside includes: a drain external contact area, a source external contact area and a gate external contact area. The top side includes at least one source external contact area and a gate external contact area. The gate external contact areas on the top side and the underside are electrically connected to one another. The power semiconductor component stack is a series circuit or a parallel circuit of MOSFET power semiconductor components arranged one above another in a plastic housing composition.

Abstract: A novel semiconductor device high in both heat dissipating property and connection reliability in mounting is to be provided. The semiconductor device comprises a semiconductor chip, a resin sealing member for sealing the semiconductor chip, a first conductive member connected to a first electrode formed on a first main surface of the semiconductor chip, and a second conductive member connected to a second electrode formed on a second main surface opposite to the first main surface of the semiconductor chip, the first conductive member being exposed from a first main surface of the resin sealing member, and the second conductive member being exposed from a second main surface opposite to the first main surface of the resin sealing member and also from side faces of the resin sealing member.

Abstract: A method of manufacture of an integrated circuit package system which includes providing a substrate and attaching a first device to the substrate. Attaching a shield to the substrate. Processing the shield to form apertures and configuring the shield to block electromagnetic energy that passes through the apertures.

Abstract: A semiconductor device includes a plurality of chips comprising a plurality of first moisture-proof rings individually surrounding said plurality of chips, a second moisture-proof ring surrounding the entire plurality of chips, and a wire for connecting said plurality of chips to each other.

Abstract: A semiconductor package includes a semiconductor chip provided with a first surface having a bonding pad, a second surface opposing to the first surface and side surfaces; a first redistribution pattern connected with the bonding pad and extending along the first surface from the bonding pad to an end portion of the side surface which meets with the second surface; and a second redistribution pattern disposed over the first redistribution pattern and extending from the side surfaces to the first surface. In an embodiment of the present invention, in which the first redistribution pattern connected with the bonding pad is formed over the semiconductor chip and the second redistribution pattern is formed over the first redistribution pattern, it is capable of reducing a length for signal transfer since the second redistribution pattern is used as an external connection terminal.

Abstract: A semiconductor package that includes a lead frame riveted to pillars electrically connect to an electrode of a semiconductor die.

Abstract: Plural via portions formed on a package substrate of a BGA include a first through-hole portion extended in the plane direction by an extension wiring connected to a land portion and a second through-hole portion that is arranged on the land portion serving as pad-on-via, whereby high-density wiring and multi-function of the BGA can be realized by using the package substrate having a two-layer wiring structure. Accordingly, cost for the package substrate can be reduced, and hence, cost for the BGA can be reduced, compared to a multi-layer wiring structure having four or six wiring layers.

Abstract: One embodiment of a semiconductor package described herein includes a substrate having a first through-hole extending therethrough; a conductive pattern overlying the substrate and extending over the first through-hole; a first semiconductor chip facing the conductive pattern such that at least a portion of the first semiconductor chip is disposed within the first through-hole; and a first external contact terminal within the first through-hole and electrically connecting the conductive pattern to the first semiconductor chip.

Abstract: A plurality of IC regions are formed on a semiconductor wafer, which is cut into individual chips incorporating ICs, wherein wiring layers and insulating layers are sequentially formed on a silicon substrate. In order to reduce height differences between ICs and scribing lines, a planar insulating layer is formed to cover the overall surface with respect to ICs, seal rings, and scribing lines. In order to avoid occurrence of breaks and failures in ICs, openings are formed to partially etch insulating layers in a step-like manner so that walls thereof are each slanted by prescribed angles ranging from 20° to 80°. For example, a first opening is formed with respect to a thin-film element section, and a second opening is formed with respect to an external-terminal connection pad.

Abstract: A semiconductor device including: a semiconductor substrate having an electrode; a resin protrusion formed on a surface of the semiconductor substrate on which the electrode is formed, the resin protrusion extending along a straight line and having a sloping region of which a height decreases along the straight line as a distance from a center of the resin protrusion increases; and an interconnect electrically connected to the electrode and extending over the sloping region of the resin protrusion.