Abstract: Various serial interface implementations and related methods are provided for establishing serial data links with programmable logic devices (PLDs). In one example, a PLD includes a plurality of programmable logic blocks adapted to be programmed to configure the PLD for its intended function. The PLD also includes a serial interface comprising a transmit port, a microcontroller, a transmit register, and transmit logic. The microcontroller is adapted to adjust pre-emphasis settings associated with the transmit port to tune a serial data link between the PLD and an external device. The transmit register is adapted to receive a data signal from the programmable logic blocks. The data signal comprises transmit data to be provided over the serial data link through the transmit port. The transmit logic is adapted to prepare a serial signal for transmission from the transmit port over the serial data link. The serial signal comprises the transmit data.

Abstract: Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the insulator nanolaminate layers.

Abstract: A power sequencing method may use a state machine in a programmable sequencer to program relative timing of signals to activate different power rails attached to an integrated circuit. Input lines may specify the sequencing program. Alternatively, the programmable sequencer may use an EEPROM or other computer-readable medium to program itself with a particular image of the sequencing program. The programmable sequencer may be implemented by a Field Programmable Gate Array (FPGA).

Abstract: The present invention discloses a level shift circuit which comprises: a basic level shift circuit for receiving inputs of first high and low operational voltage levels and generating outputs of second low and high operational voltage levels at a first node; and an output circuit for outputting a signal of one of the second operational voltage levels according to a voltage level switching at the first node.

Abstract: A buffer circuit uses (e.g., active) inductors for driving capacitive loads. In one embodiment, the buffer circuit has one or more stages, each stage having one CMOS inverter. Each CMOS inverter has one NMOS transistor and one PMOS transistor and is coupled to a stage input and a stage output. Additionally, at least one stage of the buffer circuit has two inductors, each coupled between a different voltage reference for the buffer circuit and the stage output. One inductor has a PMOS transistor coupled to the gate of an NMOS transistor and the other inductor has an NMOS transistor coupled to the gate of a PMOS transistor. When driving capacitive loads, the inductors partially tune out the apparent load capacitance CL, thereby improving the charging capabilities of inverter and enabling quicker charge and discharge times. Furthermore, partially tuning out apparent load capacitance facilitates the driving of larger capacitive loads.

Abstract: A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.

Abstract: A phase frequency detector comprising a detection circuit and a reset circuit. The phase frequency detector may receive a feedback signal having a predetermined pulse width. The detection circuit may generate a first control signal based on a reference signal, and a second control signal based on the feedback signal. The reset circuit may generate a reset signal used for resetting the detection circuit based on the first control signal, the second control signal, and the feedback signal. The feedback signal may be tied to the generation of the reset signal such that, during a locked state, the pulse width of the second control signal is approximately equal to the pulse width of the feedback signal, which helps reduce the sensitivity of the circuit to nonlinearities.

Abstract: An integrated circuit comparator includes a pair of differential input transistors having gate terminals configured to receive a pair of differential input signals and a comparator output circuit electrically coupled to the pair of differential input transistors. A pair of differential offset compensation transistors are also provided. This pair of differential offset compensation transistors, which is electrically coupled to the pair of differential input transistors, has gate terminals that are configured to receive a pair of unequal dc offset voltages.

Abstract: A window comparator of an A.C. input voltage, including, between two terminals of application of a voltage representative of the voltage to be measured, two first transistors of a first type, each first transistor being assembled as a current mirror on the second transistor having a first conduction terminal connected to one of the application terminals, the two second transistors having a second common conduction terminal; and two third transistors of a second type assembled as a current mirror between the common conduction terminal of the second transistors and a current source, a D.C. voltage being applied on a first terminal of the current source and an output signal being provided by a second terminal of the current source.

Abstract: A frequency synthesizer includes a first clock running at a frequency fCLK1, a second clock running at a frequency fCLK2, wherein frequency fCLK2 is higher than frequency fCLK1, the frequencies having a fixed ratio QFB=fCLK2/fCLK1; and a counter driven by the first clock. A decoder for produces QFB output values in parallel for each cycle of the first clock, and parallel-serial converter serially outputs these QFB output values at the frequency of the second clock.

Abstract: A plurality of output drive devices are capable of tolerating an overvoltage produced by an electrical connection with an external device operating in a high-voltage supply realm. The drive devices are capable of sustaining a continuous electrical connection to the elevated voltage levels and produce communications at an output voltage level equal to the supply voltage indigenous to the device. A high-voltage tolerant driver includes a plurality of output drive devices capable of tolerating an overvoltage, sustaining an electrical connection to an elevated voltage level, and producing an output voltage at an indigenous supply level. An initial pullup drive circuit is coupled to the plurality of output drive devices and produces an initial elevated drive voltage to the plurality of output drive devices. A sustain pullup circuit is coupled to the plurality of output drive devices and produces a sustained output voltage at the indigenous supply level.

Abstract: One aspect relates to a clock signal synchronizing device, in particular to a delayed locked loop (DLL) with capability to correct static duty-cycle offset and to filter clock-jitter. One aspect relates to a clock signal synchronizing method with capability to correct static duty-cycle offset and to filter clock-jitter. In accordance one aspect, there is provided a clock signal synchronizing device including a delay circuit having a variable delay time and delaying an incoming clock signal or a signal generated therefrom to output a delayed clock signal. Also included is a negator for inverting the delayed clock signal to output an inverted delayed clock signal. Also included is a delay control circuit for controlling the delay circuit to adjust the phase relation between the incoming clock signal and the inverted delayed clock signal and a phase interpolator.

Abstract: A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.

Abstract: One embodiment provides an electronic system including a delay locked loop and a control circuit. The delay locked loop is configured to be enabled and update lock state data and to be disabled and store the locked state data. The control circuit is configured to periodically enable the delay locked loop in standby mode at an update interval and for an enable period. The control circuit controls the length of the update interval and the length of the enable period to adjust lock state acquisition time for the delay locked loop in exiting the standby mode.

Abstract: Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay line), the reference clock as trimmed by a delay Tref, and the feedback clock as trimmed by a delay Tfb. By using these three phases at the appropriate time, the measurement is aware of the Tac trim for both positive (Tref) and negative (Tfb) trims. Specifically, measurement ‘start’ and ‘stop’ signals each pass through only one of delays Tref and Tfb, such that error in the measurement is a function of both Tref and Tfb. This improves the accuracy of the measurement such that additional shifting of the DLL is not necessary after initialization, and allows a wide trim range even for high clock frequencies.

Abstract: A DLL circuit according to an embodiment of the present invention includes: a delay line configured to output a plurality of delayed signals of a reference signal, the delay line including, a plurality of first delay units connected in series with each other, each of the first delay units being configured to output a delayed signal of the reference signal, a blocking circuit inserted between the first delay units, the blocking circuit being capable of switching between passing and blocking an input delayed signal of the reference signal, and the delay time of the blocking circuit being integer times as large as each of the delay time of the first delay units, and one or more second delay units connected in parallel with the blocking circuit, the same signal as the delayed signal that is input in the blocking circuit being input in the second delay units, each of the second delay units being configured to output a delayed signal of the reference signal, and the delay time of each of the second delay units bein

Abstract: An apparatus for outputting data of a semiconductor memory apparatus, which is capable of varying the slew rate and the data output timing, includes a bias generator that generates a bias having a level corresponding to a set value, a slew rate controller that controls a pull-up slew rate or a pull-down slew rate of input data on the basis of the bias generated by the bias generator, and a data outputting unit that outputs data on the basis of the slew rate controlled by the slew rate controller. Therefore, it is possible to satisfy various operational conditions without changing the structure of the circuit and to correspond rapidly and appropriately with a change of the system, which enables the applied range of the products to be extended.

Abstract: A programmable delay line includes a first oscillator that is enabled and generates a plurality of clock cycles of a clock signal in response to a transition of the input signal. A first programmable ripple counter is coupled to the first oscillator, counts with each successive clock cycle to a programmed count, and generates a first signal in response to reaching the programmed count. A control circuit is coupled to the first oscillator and to the first programmable ripple counter. The control circuit transitions the output signal and disables the first oscillator in response to the first signal.

Abstract: A delay circuit that includes a logic gate through which an input signal passes, a capacitor configured to be charged and discharged at an output terminal of the logic gate and delaying the input signal, and a mirroring unit configured to constantly maintain current output by the logic gate by mirroring current output by a constant current source.

Abstract: The present invention describes a skew compensation circuit that can compensate for changes in signal skew in response to changes in external environments and processes. The skew compensation circuit includes a controller for outputting a control signal according to whether an external power supply is supplied and its operation mode. The skew compensation circuit also includes a signal output unit which selects either a normal path or a skew reduction path according to the control signal and outputs an input signal through the selected path.

Abstract: A pulse generator includes a pulse command register and a digital differential analyzer (DDA). The pulse command register includes a first register, a second register, and an adder. The first register receives and stores a pulse command from a CPU in an operating cycle. The second register receives and stores the pulse command shifted from the first register when the first register receives a second pulse command from the CPU in the operating cycle. The adder sums the pulse commands of the first register and the second register and the result is transmitted to the DDA. The DDA determines whether a pulse is to be generated after calculation according to the result from the adder of the pulse command register.

Abstract: A source follower includes first through third switches, first and second transistors, and a first capacitor. The first switch is used to determine whether or not to couple the source of the first transistor with an input signal. The second switch is used to determine whether or not to couple a gate and a drain of the first transistor with a first voltage. A first end of the first capacitor is coupled with a first control signal, and a second end of the first capacitor is coupled to the drain of the first transistor and a gate of the second transistor. The third switch is used to determine whether to or not couple a drain of the second transistor with the first voltage, and a source of the second transistor serves as an output of the source follower.

Abstract: Compensation for an RF detector includes components having different order temperature functions. The components are combined and may be adjusted by various numbers of user-accessible terminals to provide individual adjustment for factors such as operating frequency. In some embodiments, first and second-order temperature functions are generated independently and combined to provide a polynomial function of temperature with coefficients that may be adjusted. In other embodiments, the outputs of the function generators may be more complex functions of temperature with various adjustable parameters.

Abstract: A semiconductor device chip, semiconductor device system, and a method. One embodiment provides a semiconductor device chip including a device for determining whether the semiconductor device chip is to be placed in a current saving operating mode.

Abstract: An integrated analog switch including first and second semiconductor devices and a current mirror. The first device is a switching device having first and second current terminals coupled between first and second switch terminals. When turned off, the body of the first device is pulled to a bias voltage, and a first leakage current flows between its body and the first switch terminal. The second device is a reduced-size replica of the first device having one current terminal coupled to the first switch terminal and having its body pulled to about the bias voltage when turned off. The second device provides a second leakage current which is proportional to the leakage current of the first device. The current mirror circuit mirrors and amplifies the second leakage current to provide a cancellation current which is applied to the first switch terminal to cancel leakage current.

Abstract: Switches with passive bootstrap that can achieve good sampling performance are described. In one design, a sampling circuit with passive bootstrap includes first and second filters and a switch. The first filter filters an input signal and provides a filtered input signal. The second filter filters a clock signal and provides a filtered clock signal. The switch receives a control signal formed based on the filtered input signal and the filtered clock signal and either passes or blocks the input signal based on the control signal. The first filter may be a lowpass filter having a first corner frequency that is higher than the bandwidth of the input signal. The second filter may be a highpass filter having a second corner frequency that is lower than the fundamental frequency of the clock signal. The first and second filters may both be implemented with one resistor and one capacitor.

Abstract: The first control transistor is connected between a first input node for receiving a first input signal swinging between a first voltage and a second voltage and an intermediate node for outputting an output signal, and receives the second voltage at its gate. The second control transistor is connected between a second input node for receiving a second input signal swinging between a third voltage and a fourth voltage in synchronization with the first input signal and the intermediate node, and receives the third voltage at its gate. The voltage difference between the first voltage and the third voltage is smaller than or equal to the source-drain breakdown voltage of the second control transistor, and the voltage difference between the second voltage and the fourth voltage is smaller than or equal to the source-drain breakdown voltage of the first control transistor.

Abstract: The present invention provides a charge pump circuit capable of achieving desired boosting operation even when a high-side switch for precharge or a low-side switch for driving output is constructed by a low-withstand-voltage transistor. The high level of a drive input signal for driving a high-side switch for precharge and a low-side switch for driving output in response to a clock signal is set to the level of a boosted output voltage. The low level of the drive input signal is set to the level of an input voltage, not ground potential.

Abstract: A transistor causes fluctuation in the threshold and mobility due to the factor such as fluctuation of the gate length, the gate width, and the gate insulating film thickness generated by the difference of the manufacturing steps and the substrate to be used. As a result, there is caused fluctuation in the current value supplied to the pixel due to the influence of the characteristic fluctuation of the transistor, resulting in generating streaks in the display image. A light emitting device is provided which reduces influence of characteristics of transistors in a current source circuit constituting a signal line driving circuit until the transistor characteristics do not affect the device and which can display a clear image with no irregularities. A signal line driving circuit of the present invention can prevent streaks in a displayed image and uneven luminance.

Abstract: A current generator, including a chopper stabilization operational amplifier, a transistor, and an impedance unit is provided. The chopper stabilization operational amplifier includes a first input terminal, a second input terminal, and an output terminal. The transistor includes a gate coupled to the output terminal of the chopper stabilization operational amplifier, a first source/drain coupled to the first input terminal of the chopper stabilization operational amplifier, and a second source/drain serving as a current output terminal of the current generator. The impedance unit includes a first terminal coupled to the first source/drain of the transistor, and a second terminal coupled to a first voltage.

Abstract: A current limiting load switch for bridging supply Vss and load with a reference voltage VRdt dynamically generated by a VRdt-generator is proposed. It includes: A pair of power FET and sense FET interconnected in split-current configuration. The FET pair develops a load voltage while limiting load current Iload to a preset maximum Imax. The FET pair is sized to draw device currents Ipower and Is with RATIOI=Is/Ipower<<1. The sense FET high-side terminal is coupled to Vss through a sense resistor Rsense developing a sense voltage Vs=Is×Rsense. A current limiting amplifier with inputs connected to VRdt and Vs and output controlling FET pair closing a current limiting feedback loop. The VRdt-generator dynamically adjusts VRdt concurrent and compensatory with an undesirable effect of changing RATIOI caused by the sense FET operational transition thus eliminating a transitional overshoot of Iload beyond Imax.

Abstract: A circuit for breaking a signal path has not only a switching means but also a low-pass or bandpass filter whose frequency characteristic is switchable or bypassable. The insulation between the input and the output when the switching means is open, which decreases with frequency in the case of ordinary switching means, is compensated for by the filter which is then connected. In one embodiment of the circuit, an out-of-band signal is applied to the circuit in addition to the useful signal. The out-of-band signal is intended to be supplied permanently to an evaluation circuit, regardless of the switching position of the switching means. To this end, the out-of-band signal is tapped off downstream of the filter, and the filter is designed such that the out-of-band signal can pass through the filter. In the case of a circuit for selecting one of two inputs, at least one of the inputs is provided with a switchable or bypassable filter, and the switching means is a selection means.

Abstract: A Phased Locked Loop (PLL) circuit includes: a clock signal generating unit for generating a first clock signal and a second clock signal of which the phase differs from the first clock signal by ?/2; a computing unit for computing first phase comparison results showing the results of comparing the phases of a signal wherein the first clock signal is subjected to phase shifting with the PSK modulation signal and second phase comparison results showing the results of comparing the phases of a signal wherein the second clock signal is subjected to phase shifting with the PSK modulation signal based on first and second parameters, the first clock signal, the second clock signal, and the PSK modulation signal; a control direction setting unit for virtually controlling the control angle; a parameter control unit; and a reading control unit for controlling the timing of reading data from the PSK modulation.

Abstract: Systems and methods for performance improvements in digital switching amplifiers using low-pass filtering to reduce noise and distortion. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low-pass filter configured to filter audio signals output by the plant. The filtered output of the plant is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.

Abstract: A pulse-width modulation (PWM) amplifier comprises a feedback loop for reshaping the pulses of the PWM input signal to correct timing and amplitude errors in the class D output stage of the amplifier by means of an error correction signal. In such an amplifier the feedback loop gives a substantial amount of base-band noise when the pulse-period of the PWM input signal is not constant, which is especially the case when the PWM signal originates from a noise shaper. The invention reduces this noise by modifying the reshaping gain of the amplifier with a pulse-period proportional signal.

Abstract: An audio signal processing system and method is disclosed. In a particular embodiment, the audio signal processing system includes a first electrical path responsive to a power supply of an audio amplifier. The first electrical path can include a low pass filter to filter a direct current (DC) component of the power supply and a first analog-to-digital converter (ADC) responsive to the low pass filter. The audio signal processing system also includes a second electrical path responsive to the power supply. The second electrical path can include a high pass filter to filter an alternating current (AC) component of the power supply and a second ADC responsive to an output of the high pass filter. The audio signal processing system includes compensation logic to modify an audio signal based on a first signal generated from the first electrical path and a second signal generated from the second electrical path.

Abstract: In one embodiment, the present invention includes multiple gain stages and an output network coupled to the gain stages. Each of the gain stages can be independently controlled to amplify a radio frequency (RF) signal to an output power level for transmission from a mobile wireless device. When controlled to be inactive, at least one of the gain stages can be placed into a low impedance state.

Abstract: A power amplifier circuit includes two amplifier subsections and delay elements coupled in parallel. An input received by the second amplifier subsection is a delayed version of the input received by the first amplifier subsection. The output of the first amplifier subsection is delayed such that the delayed output of the first amplifier subsection is in phase with the output of the second amplifier subsection. For low output power operation, only the first amplifier subsection is enabled. For high output power operation, both the first and the second amplifier subsections are enabled. The first and the second amplifier subsections operate as saturated amplifiers. A first variable output power control signal controls the output power of the first amplifier subsection, and a second variable output power control signal controls the output power of the second amplifier subsection.

Abstract: A collector boost circuit is disclosed for providing a first voltage in a first mode of operation to a power amplifier, and another voltage in a second mode of operation to the power amplifier. The collector boost circuit uses an indicator signal derived by an RF detector to switch between the first and the second mode of operation. The another voltage is a boosted voltage greater than the first voltage and is provided when required during peak excursions to prevent amplifier clipping through a boost capacitor. The another voltage is continuous and varies in accordance with the detected peak signal amplitude.

Abstract: Satellite set-top boxes (STB) are increasingly being designed with multiple tuners, making them capable of receiving more than one program at a time. In addition, satellite STBs are increasingly being designed with multiple inputs, to permit reception of additional channels that will not fit within the conventional satellite intermediate frequency (IF) band (950-2150 MHz). Often, the STB must route these multiple inputs to the multiple tuners with some form of switching function, to allow each tuner to receive all channel bands. Accordingly, the invention includes an RFIC with two RF inputs and three RF outputs, and a crossbar switch that can route any input to any output. The two inputs are amplified by low-noise amplifier stages.

Abstract: The distortion compensation apparatus includes: a branching unit to branch a part of the output signal of an amplifier to a signal path to a distortion compensating unit; a switch to pass the output signal of the amplifier to the interference or branching unit; and a controlling unit to control an amount of the compensation of the distortion under a pass-permitted state in which the switch passes the output signal in response to a result of measurement of a signal transmitted through the signal path under a state where the switch is in an interruption state.

Abstract: The present invention discloses a Class-D power amplifier and control method thereof. In one embodiment, the amplifier feeds back the signal at the output node to the inverting input of the comparator, and provides a high frequency triangular wave signal to the non-inverting input of the comparator. In addition, the non-inverting input of the comparator may be coupled to an offset voltage, while the inverting input of the comparator may be coupled to a fixed-frequency rectangular wave signal, a feedback signal which is derived from the output stage and an input signal. In use, the switching frequency may be at least substantially fixed, so as to reduce the influence on the system caused by electromagnetic interruption (EMI). Further, the control circuit is simple, and some devices can be integrated.

Abstract: A differential amplifier is constituted of first emitter-follower transistors, second emitter-follower transistors, and amplification transistors whose bases are alternately connected to the emitters of the second emitter-follower transistors and whose collectors are connected to the emitters of the first emitter-follower transistors, as well as emitter resistors and constant current sources, whereby it is possible to reduce distortions of output signals in response to large-amplitude input signals, thus ensuring high-speed operation. It is possible to further incorporate base-grounded transistors and diodes, by which substantially the same collector-emitter voltage is applied to the emitter-follower transistors and amplification transistors, thus achieving the same power consumption and the same temperature variations with respect to these transistors.

Abstract: Disclosed herein is a variable-gain amplification circuit, wherein the sources of first and second MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are tied to a common connection point connected to a current source. An input signal is supplied to the gates of the first and second MOSFETs. The drains of the first and second MOSFETs are connected to the sources of third and fourth MOSFETs respectively whereas the drains of the third and fourth MOSFETs are connected to two output terminals respectively, a gain control voltage is supplied to the gates of both the third and fourth MOSFETs. When control is executed in order to lower the gain control voltage supplied to the gates of both the third and fourth MOSFETs, other control is also executed in order to raise a bias voltage applied to the gates of both the first and second MOSFETs.

Abstract: The present invention relates to an output stage circuit and an operational amplifier thereof. In the output stage circuit, one of a gate of a transistor is coupled to a gate of a bias transistor and a level shifter in response to a small signal outputted from an amplifying circuit in the operational amplifier. In addition, a gate voltage of the bias transistor is controlled by a voltage generating circuit to control a DC bias of the transistor of the output stage circuit. Therefore, extra frequency compensating components for compensating the transistor of the output stage circuit is no longer necessary, and saving circuit layout area and cost can be achieved by the present invention.

Abstract: An amplifier including complementary push and pull components, a bias component and a quiescent current balancer. The complementary push and pull components are serially coupled to one another between an electrical source and sink to generate an output signal at a common output terminal responsive to the input signal source. The bias component is coupled between the input signal source and the complementary push-pull components to bias the input signal to the push component and the input signal to the pull component by discrete amounts which reduce cross-over clipping exhibited in the output signal. The quiescent current balancer is coupled to the output terminal to balance quiescent currents in the push and the pull component at discrete levels which equilibrate amplification levels of the input signal generated by the push component and the pull component in the output signal at the output terminal.

Abstract: An RF power circuit comprises a power transistor having a gate and drain, an output matching network coupled to the drain and an input matching network coupled to the gate. A closed-loop bias circuit is integrated with the power transistor on the same die and coupled to the gate for biasing the RF power transistor based on a reference voltage applied to the bias circuit.

Abstract: Provided is a radio frequency (RF) amplifier. The RF amplifier includes an amplification circuit amplifying an RF signal, a bias voltage generation circuit supplying a bias voltage of the amplification circuit, and a first bias resistor connected between the amplification circuit ad the bias voltage generation circuit, and having a predetermined resistance allowing the bias voltage to be affected by the RF signal.

Abstract: An active balun with Darlington pairs obtains a wideband operation. With differential output signals, a size of the active balun is minimized. The present invention can be applied to a transceiver. With a wideband amplitude match and 180° out of phase, the performance of the transceiver is improved by the present invention for a few wide applications.

Abstract: Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.