Abstract: An organic light emitting diode (OLED) and a manufacturing method thereof are provided. The OLED includes a substrate, and a first electrode serving as an anode, an organic material layer, a second electrode serving as a cathode, and a sealing layer are formed on the substrate in sequence, and the second electrode is a composite transparent structure layer realizing light emission at the top portion. By forming the composite transparent cathode with a light-transmissive top portion, the OLED emits lights from the top portion, so as to effectively enhance a light utilization ratio and a light transmission ratio, and thus not only an aperture ratio of a display screen is enhanced, but also an excellent displaying effect is obtained.

Abstract: A semiconductor device having semiconductor elements disposed with higher density and a method for manufacturing the same are provided. An image display device employing the semiconductor device is also provided. A semiconductor device comprises a resin film having a through hole; and a semiconductor element comprising a gate electrode disposed on the inner wall of the through hole, an insulating layer that covers the gate electrode within the through hole, an organic semiconductor disposed on the insulating layer within the through hole, and a source electrode and a drain electrode which are electrically connected to the organic semiconductor.

Abstract: Disclosed is an organic EL display panel which includes: a substrate; a linear first bank which is disposed over the substrate and defines a linear region; a second bank which defines two or more pixel regions arranged in the linear region; a pixel electrode disposed in the pixel region; a linear organic layer which is formed by coating method in the linear region over the pixel electrode and second bank; and a counter electrode over the organic layer, wherein the first bank is larger in height than the second bank, the first and second banks are made of resin, anisole contact angle at the top of the first bank is 30-60°, and anisole contact angle at the top of the second bank is 5-30°.

Abstract: An organic electroluminescent element includes an electron-transport layer composed of a heterocyclic compound, a negative electrode composed of a metal material, and a transition-metal-complex layer arranged between the electron-transport layer and the negative electrode.

Abstract: An organic light emitting device with improved light emitting efficiency, the organic light emitting device includes a substrate, a first electrode arranged on the substrate, a second electrode arranged to face the first electrode, an organic light-emitting layer arranged between the first electrode and the second electrode, an electron transport layer arranged between the organic light-emitting layer and the second electrode, wherein the electron transport layer includes a multi-layer structure that includes at least one first layer and at least two second layers, wherein ones of said at least one first layer and ones of said at least two second layers are alternately stacked, wherein ones of the at least two second layers are arranged at both opposite ends of the electron transport layer, each of the at least two second layers having a lower electron mobility than that of each of the at least one first layer.

Abstract: A light-emitting element includes a first electrode, a first light-emitting layer formed over the first electrode, a second light-emitting layer formed on and in contact with the first light-emitting layer to be in contact therewith, and a second electrode formed over the second light-emitting layer. The first light-emitting layer includes a first light-emitting substance and a hole-transporting organic compound, and the second light-emitting layer includes a second light-emitting substance and an electron-transporting organic compound. Substances are selected such that a difference in LUMO levels between the first light-emitting substance, the second light-emitting substance, and the electron-transporting organic compound is 0.2 eV or less, a difference in HOMO levels between the hole-transporting organic compound, the first light-emitting substance, and the second light-emitting substance is 0.

Abstract: A thin film transistor using an oxide semiconductor as an active layer, and its method of manufacture. The thin film transistor includes: a substrate; an active layer formed of an oxide semiconductor; a gate insulating layer formed of a dielectric on the active layer, the dielectric having an etching selectivity of 20 to 100:1 with respect to the oxide semiconductor; a gate electrode formed on the gate insulating layer; an insulating layer formed on the substrate including the gate electrode and having contact holes to expose the active layer; and source and drain electrodes connected to the active layer through the contact holes. Since the source and drain electrodes are not overlapped with the gate electrode, parasitic capacitance between the source and drain electrodes and the gate electrode is minimized. Since the gate insulating layer is formed of dielectric having a high etching selectivity with respect to oxide semiconductor, the active layer is not deteriorated.

Abstract: The invention relates to a printable precursor comprising an organometallic zinc complex which contains at least one ligand from the class of the oximates and is free from alkali metals and alkaline-earth metals, for electronic components and to a preparation process. The invention furthermore relates to corresponding printed electronic components, preferably field-effect transistors.

Abstract: A semiconductor device including a thin film transistor which includes an oxide semiconductor layer and has high electric characteristics and reliability. Film deposition is performed using an oxide semiconductor target containing an insulator (an insulating oxide, an insulating nitride, silicon oxynitride, aluminum oxynitride, or the like), typically SiO2, so that the semiconductor device in which the Si-element concentration in the thickness direction of the oxide semiconductor layer has a gradient which increases in accordance with an increase in a distance from a gate electrode is realized.

Abstract: An electrode structure comprises a semiconductor junction comprising an n-type semiconductor layer and a p-type semiconductor layer; a hole exnihilation layer on the p-type semiconductor layer; and a transparent electrode layer on the hole exnihilation layer. The electrode structure further comprises a conductive layer between the hole exnihilation layer and the transparent electrode layer. In the electrode structure, one or more of the hole exnihilation layer, the conductive layer and the transparent electrode layer may be formed by an atomic layer deposition. In the electrode structure, a transparent electrode formed of a degenerated n-type oxide semiconductor does not come in direct contact with a p-type semiconductor, and thus, annihilation or recombination of holes generated in the p-type semiconductor can be reduced, which increases the carrier generation efficiency.

Abstract: Provided is a semiconductor device that may prevent a test pad planned not to be wire bonded from being wire bonded. The semiconductor device may include a bonding pad planned to be wire bonded and a test pad planned not to be wire bonded, and a passivation layer including a first opening portion exposing part of the bonding pad and a second opening portion exposing part of the test pad, wherein the diameter of the first opening portion is greater than the diameter of a tip of a bonding wire, and the diameter of the second opening portion is less than the diameter of the tip of the bonding wire.

Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2), a plurality of integrated circuits (1) formed lattice-like in rows and columns on the wafer substrate (2), and first and second saw lines (4, 5) separating the integrated circuits (1). The first saw lines (4) run parallel and equidistant with respect to each other in a first direction (x) defined by the rows and the second saw lines (5) run parallel and equidistant with respect to each other in a second direction (y)defined by the columns. The integrated circuits (1) on the wafer further comprise a plurality of process control modules (3) formed on the wafer substrate (2) such that a given process control module (3) of the plurality of process modules (3) is bounded by two consecutive first saw lines (4) as well as by two consecutive second saw lines (5).

Abstract: A display device for preventing misalignment of data lines and pixel electrodes, and a manufacturing method of the display device are provided. The display device includes an insulation substrate, line wiring formed on the insulation substrate, an organic insulating pattern covering the top surface and side surfaces of a portion of the line wiring, a first insulating layer formed on the organic insulating pattern and the insulation substrate, and transparent conductive patterns formed on the first insulating layer, wherein boundaries of the transparent conductive patterns are positioned on inclined surfaces of the first insulating layer in a portion thereof corresponding to the organic insulating pattern.

Abstract: An active matrix substrate in which variations in output characteristics of photodiodes are reduced, and a display device using this active matrix substrate, are provided. An active matrix substrate (1) having an n-TFT (20), a p-TFT (30), and a photodiode (10) is used. The photodiode (10) includes a p-layer (7), an i-layer (8), and an n-layer (9). The i-layer (8) includes a p-type semiconductor region (8a) at a position adjacent to the player (7), said p-type semiconductor region (8a) having a diffusion concentration of p-type impurities that is set at the same level as that of a diffusion concentration of p-type impurities in the channel region (23) of the n-TFT (20); and an n-type semiconductor region (8b) at a position adjacent to the n-layer (9), said n-type semiconductor region (8b) having a diffusion concentration of n-type impurities that is set at the same level as that of a diffusion concentration of n-type impurities in the channel region (33) of the p-TFT (30).

Abstract: A laminate structure is disclosed that has a region having high surface free energy and a region having low surface free energy that are well separated, has high adhesiveness between an underlying layer and a conductive layer, and can be formed easily with low cost. The laminate structure includes a wettability-variable layer including a first surface free energy region of a first film thickness and a second surface free energy region of a second film thickness, and a conductive layer formed on the second surface free energy region of the wettability-variable layer. The second film thickness is less than the first film thickness and the surface free energy of the second surface free energy region is made higher than the surface free energy of the first surface free energy region by applying a predetermined amount of energy on the second surface free energy region.

Abstract: A data line and an amorphous silicon pattern are formed on a substrate. The first electrode pattern is extended from the data line and overlaps an edge of the amorphous silicon pattern. The second electrode pattern is made of the same metal as the first electrode pattern and overlaps the edge of the amorphous silicon pattern at an opposite side of the first electrode pattern. Edges of the first and the second electrode patterns are sharply formed so that a tunneling effect easily occurs through the amorphous silicon pattern. An indium-tin-oxide pattern for a capacitor is formed at the end of the second electrode pattern. The capacitor is formed between the ITO pattern and a common electrode.

Abstract: A diode has a first contact of a material having a first conductivity type, a second contact of a material having a second conductivity type arranged co-planarly with the first contact, a channel arranged co-planarly between the first and second contacts, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A diode has a layer of material arranged on a substrate, a first region of material doped to have a first conductivity type, a second region of material doped to have a second conductivity type, a channel between the first and second regions formed of an undoped region, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate.

Abstract: A system for displaying images. The system includes a thin film transistor (TFT) device including a first insulating layer covering a first region and a second region of a substrate. A first polysilicon active layer is disposed in the first region and between the substrate and the first insulating layer. A second polysilicon active layer is disposed on the first insulating layer in the second region. A polysilicon gate layer is disposed above the first polysilicon active layer. A second insulating layer covers the polysilicon gate layer and the second polysilicon active layer. A metal gate layer is disposed above the second polysilicon active layer. A method for fabricating the system for displaying images including the TFT device is also disclosed.

Abstract: A semiconductor device includes at least one thin-film transistor 116, which includes: a crystalline semiconductor layer 120 including a region 110 to be a channel region and source and drain regions 113; a gate electrode 107 for controlling the conductivity of the region 110 to be a channel region; a gate insulating film 106 arranged between the semiconductor layer 120 and the gate electrode 107; and source and drain electrodes 115 connected to the source and drain regions 113, respectively. At least one of the source and drain regions 113 contains an element to be a donor or an acceptor and a rare-gas element, but the region 110 to be a channel region does not contain the rare-gas element. The atomic weight of the rare-gas element is greater than that of the element to be a donor or an acceptor. The concentration of the rare-gas element in the at least one region as measured in the thickness direction thereof decreases continuously from the upper surface of the at least one region toward its lower surface.

Abstract: An epitaxial structure having a low defect density includes: a base layer; a first epitaxial layer having a plurality of concentrated defect groups, and an epitaxial surface that has a plurality of first recesses corresponding in position to the concentrated defect groups, the sizes of the first recesses being close to each other; and a plurality of defect-termination blocks respectively and filling the first recesses and having polished surfaces. The defect-termination blocks are made of a material which is different in removal rate from that of the first epitaxial layer.

Abstract: There is provided a nitride semiconductor substrate. The nitride semiconductor substrate comprises a substrate, a patterned epitaxy layer, a protective layer and a gallium nitride semiconductor layer. The patterned epitaxy layer is disposed on the substrate, wherein the patterned epitaxy layer comprises a pier structure and the patterned epitaxy layer has an upper surface and a lower surface opposite to the upper surface and the lower surface faces to the substrate. The protective layer covers a portion of the upper surface of the patterned epitaxy layer to expose a top surface of the pier structure. The gallium nitride (GaN) semiconductor layer extends substantially across an entire area above the patterned epitaxy layer and connected to the exposed top surface of the pier structure.

Abstract: A package structure is described. A light emitting element and a light sensing element are disposed on a substrate, and are both wrapped by a package layer. Meanwhile, the light emitting element and the light sensing element are separated by a trench of the package layer, such that lights generated by the light emitting element are blocked, thereby reducing the noise interference on the light sensing element and improving the sensing precision of the light sensing element.

Abstract: The present invention discloses an light emitting diode (LED) light source and an interface for providing power to the LED. The LED light source includes an LED unit and a second coupling unit. The LED unit includes a base, one or more LED, and a first coupling unit. The LED are attached to the base. The joining of the first and second coupling units provides a mechanical support and electricity to the LED. The LED, are connected with independent circuit loops and controlled by controller to change the brightness of the LED. This structure allows the second coupling unit to be applied to any luminaries or replacement of a traditional light source, thus making the LED unit a universal LED light source for mass production and cost reduction. With the use of various types of LED and electric current control, modulation of brightness, color, and color temperature may be achieved.

Abstract: A light emitting apparatus including a light emitting element of a gallium nitride based semiconductor and a light converter absorbing a part of primary light emitted from the light emitting element to emit secondary light with a longer wavelength than the primary light, the light converter includes, as a red light emitting phosphor, divalent europium activated nitride red light emitting phosphor substantially represented by (MI1-aEua)MIISiN3 and includes, as a green or yellow light emitting phosphor, any selected from divalent europium activated oxynitride green light emitting phosphor substantially represented by EubSicAldOeNf, divalent europium activated oxynitride yellow light emitting phosphor substantially represented by MIIIgEuhSiiAljOkNl and trivalent cerium activated silicate green light emitting phosphor substantially represented by MIV3(MV1-mCem)2(SiO4)3, and forward current applied to the light emitting element is 25 mA or more.

Abstract: An LED is provided comprising two or more light-emitting Type II interfaces wherein at least two of the Type II interfaces differ in transition energy by at least 5%, or more typically by at least 10%, and wherein at least one of the Type II interfaces is within a pn junction. Alternately, an LED is provided comprising two or more light-emitting Type II interfaces wherein at least two of the Type II interfaces differ in transition energy by at least 5%, or more typically by at least 10%. The Type II interfaces may include interfaces from a layer which is an electron quantum well and not a hole quantum well, interfaces to a layer which is a hole quantum well and not an electron quantum well; and interfaces that satisfy both conditions simultaneously. The Type II interfaces may be within a pn or pin junction or not within a pn or pin junction. In the later case, emission from the Type II interfaces may be photopumped by a nearby light source. The LED may be a white or near-white light LED.

Abstract: A light emitting device comprises: a package (low temperature co-fired ceramic) having a plurality of recesses (cups) in which each recess houses at least one LED chip and at least one phosphor material applied as coating to the light emitting light surface of the LED chips, wherein the phosphor material coating is conformal in form. In another arrangement a light emitting device comprises: a planar substrate (metal core printed circuit board); a plurality of light emitting diode chips mounted on, and electrically connected to, the substrate; a conformal coating of at least one phosphor material on each light emitting diode chip; and a lens formed over each light emitting diode chip.

Abstract: A radiation-emitting semiconductor chip is specified, comprising a semiconductor body (3) having an n-conducting region (4) and a p-conducting region (5), the semiconductor body having a hole barrier layer containing a material from the material system InyGa1-x-yAlxN.

Abstract: A light emitting device includes a stack of semiconductor layers defining a light emitting pn junction and a dielectric layer disposed over the stack of semiconductor layers. The dielectric layer has a refractive index substantially matching a refractive index of the stack of semiconductor layers. The dielectric layer has a principal surface distal from the stack of semiconductor layers. The distal principal surface includes patterning, roughening, or texturing configured to promote extraction of light generated in the stack of semiconductor layers.

Abstract: The invention relates to an illumination system with a material having a low or negative thermal expansion coefficient in order to compensate for the thermal expansion of the further materials present in the illumination system.

Abstract: A light emitting device That includes a first photonic crystal structure having a reflective layer and non-metal pattern elements on the reflective layer, a second conductive semiconductor layer on both the reflective layer and the non-metal pattern elements, an active layer on the second conductive semiconductor layer, and a first conductive semiconductor layer on the active layer.

Abstract: A LED (light emitting diode) packaging structure includes a base, a LED chip, a gel-blocking structure and a phosphor layer. The LED chip disposed on the base and electrically connected to the base. The LED chip having a substrate and a semiconductor layer formed on the substrate. The gel-blocking structure is disposed on the substrate of the LED chip and surrounding the semiconductor layer. The phosphor layer is filled within a space defined by the gel-blocking structure, the substrate and the semiconductor layer. The present invention also discloses a fabricating method of the LED packaging structure.

Abstract: Disclosed is a semiconductor light emitting device. The semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer disposed therebetween, and a surface plasmon layer disposed between the active layer and at least one of the n-type and p-type semiconductor layers, including metallic particles and an insulating material, and including a conductive via for electrical connection between the active layer and the at least one of the n-type and p-type semiconductor layers, wherein the metallic particles are enclosed by the insulating material to be insulated from the at least one of the n-type and p-type semiconductor layers. The semiconductor light emitting device can achieve enhanced emission efficiency by using surface plasmon resonance. Using the semiconductor light emitting device, the diffusion of a metal employed for surface plasmon resonance into the active layer can be minimized.

Abstract: The invention provides a chip package structure and method for fabricating the same. The chip package structure includes a carrier substrate. A plurality of isolated conductive layers is disposed on the carrier substrate. At least one chip is disposed on the carrier substrate, wherein the chip has a plurality of electrodes. The electrodes are electrically connected to the conductive layers. A conductive path is disposed in the carrier substrate, electrically connected to the electrodes through the conductive layers, wherein the conductive path comprises a plurality of laminating holes.

Abstract: The invention provides a light-emitting diode illuminating apparatus. The light-emitting diode illuminating apparatus includes a carrier, a substrate, a light-emitting diode die, and a micro-lens assembly. The carrier includes a top surface and a bottom surface. A first recess is formed on the top surface of the carrier. A second recess is formed on the bottom surface of the carrier. The first recess is connected to the second recess. The substrate is embedded into the second recess. The light-emitting diode die is disposed on the substrate. The micro-lens assembly is disposed above the light-emitting diode die.

Abstract: An object of this invention is to provide an LED illumination device that can substitute for a fluorescent light and obtain uniform light with high efficiency. The LED illumination device comprises an LED with a thin-plate-shaped semiconductor element body transmitting the light generated in a PN junction area in a thickness direction and emits it from the surface, a surface electrode that covers the surface of the semiconductor element body, and columnar dielectric antennas that penetrate the surface electrode in the thickness direction and that condense the light transmitted in a body of the semiconductor element and emit it outside, a diffraction member that is arranged on a luminous surface side of the LED and that diffracts and disperses the light emitted by the LED, and a diffusion member that is arranged outside the diffraction member and that diffuses the light dispersed by the diffraction member and emits it outside.

Abstract: A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction.

Abstract: A LED chip package including a two-phase-flow heat transfer device, at least one LED chip, a metal lead frame and a package material. The two-phase-flow heat transfer device has at least one flat surface. The LED chip is directly or indirectly bonded or adhered to the flat surface of the two-phase-flow heat transfer device. Heat generated by the LED chip can be easily conducted away from the LED chip by the two-phase-flow heat transfer device such as a heat pipe, a vapor chamber and the like so as to prevent heat from accumulating in the LED chip thereby extending the service duration of the LED chip and to prevent the LED chip from deterioration of the light emitting performance caused by the accumulation of heat.

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The semiconductor device extends into a cavity in the adhesive, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The heat spreader includes a post and a base. The post extends upwardly from the base into an opening in the adhesive and is located below the cavity, and the base extends laterally from the post. The cavity extends to the post. The adhesive extends between the cavity and the conductive trace and between the base and the conductive trace. The conductive trace is located outside the cavity and provides signal routing between a pad and a terminal.

Abstract: The present invention aims to enhance the light extraction efficiency of the Group III nitride semiconductor light-emitting device. The inventive Group III nitride semiconductor light-emitting device comprises a substrate; and a Group III nitride semiconductor layer including a light-emitting layer, stacked on the substrate, wherein the side face of the Group III nitride semiconductor layer is tilted with respect to the normal line of the major surface of the substrate.

Abstract: A high voltage horizontal IGBT, which is an aspect of a semiconductor device relating to the present invention, has a buffer region formed in an SOI substrate and extending from a surface of the SOI substrate to a surface of a buried oxide film. An interface between the buffer region and a drift region is positioned equally in a vicinity of a bottom of the buffer region and in a vicinity of a surface of the buffer region or shifted toward a body region in the vicinity of the bottom of the buffer region compared to that in the vicinity of the surface of the buffer region. With this structure, a concentration of electric field in the vicinity of the bottom of the buffer region is moderated, whereby a collector-emitter breakdown voltage can further be increased.

Abstract: A protection device of programmable semiconductor surge suppressor having deep-well structure is provided comprising one, two or four protection units, each of which is composed of a PN-junction diode, a PNPN-type thyristor and a NPN-type triode connected with each other. It is characterized in that in the diode area on the frontal side of the N-type semiconductor base is formed a PN junction with impurity concentration changed gradiently from top to bottom according to the order of P+, P, N and N+; and a group of deep-wells with P-type impurities are positioned at the interface of the PN junction, making the PN junction form a concave-convex type interface. The present invention can be used in the program-controlled switchboard to protect the Subscriber Line Interface Circuit (SLIC) board. The above improvement can further improve the anti-lightning and anti-surge performance and the energy discharge capability of the whole device.

Abstract: Etch block layers having an etching rate smaller than that of a first semiconductor forming a semiconductor substrate are formed on the sidewalls of device isolation grooves by applying oblique ion implantation of Ox, N, or C to the semiconductor substrate including the first semiconductor. Embedded layers including a second semiconductor are selectively formed in recesses by epitaxial-growing the second semiconductor having a lattice constant larger than that of the first semiconductor in the recesses.

Abstract: A semiconductor device includes a substrate, a gate formed over the substrate, a gate spacer provided against first and second sidewalls of the gate, and a source/drain region formed in the substrate proximate to the gate spacer.

Abstract: A method of designing integrated circuits includes providing a first chip and a second chip identical to each other. Each of the first chip and the second chip includes a base layer including a Logic Transistor Unit (LTU) array. The LTU array includes LTUs identical to each other and arranged in rows and columns. The method further includes connecting the base layer of the first chip to form a first application chip; and connecting the base layer of the second chip to form a second application chip different from the first application chip.

Abstract: A semiconductor structure, comprising: a substrate; a seed layer over an upper surface of the substrate; a semiconductor layer disposed over the seed layer; a transistor device in the semiconductor layer; wherein the substrate has an aperture therein, such aperture extending from a bottom surface of the substrate and terminating on a bottom surface of the seed layer; and an opto-electric structure disposed on the bottom surface of the seed layer.

Abstract: Disclosed is a solid-state image sensor including a photoelectric converter, a charge detector, and a transfer transistor. The photoelectric converter stores a signal charge that is subjected to photoelectric conversion. The charge detector detects the signal charge. The transfer transistor transfers the signal charge from the photoelectric converter to the charge detector. In the solid-state image sensor, the transfer transistor includes a gate insulating film, a gate electrode formed on the gate insulating film, a first spacer formed on a sidewall of the gate electrode on a side of the photoelectric converter, and a second spacer formed on another sidewall of the gate electrode on a side of the charge detector. The first spacer is longer than the second spacer.

Abstract: In one embodiment, a metal-semiconductor field effect transistor (MESFET) comprises a first silicon layer, an insulator layer formed on the first silicon layer, and a second silicon layer formed on the insulator layer. A gate region, a source region, and a drain region are formed in the second silicon layer. A first partial trench is formed in the second silicon layer between at least a portion of the gate region and at least a portion of the source region, wherein the first partial trench stops short of the insulator layer. A second partial trench formed in the second silicon layer between at least a portion of the gate region and at least a portion of the drain region, wherein the second partial trench stops short of the insulator layer. First and second oxide spacers are formed in the first and second partial trenches. The first and second oxide spacers and the source region, gate region, and the drain region are substantially planar.

Abstract: A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array.

Abstract: Provided is a data storage device. The data storage device includes an interface, a buffer controller, a memory controller, a non-volatile memory, and a self-powered semiconductor device adjacent to and electrically connected to the buffer controller. The self-powered semiconductor device includes a semiconductor chip and a rechargeable micro-battery attached to the semiconductor chip. The rechargeable micro-battery includes a first current collector and a second current collector, which face each other, a first polarizing electrode in contact with the first current collector and facing the second current collector, a second polarizing electrode in contact with the second current collector and facing the first polarizing electrode, and an electrolyte layer formed between the first and second polarizing electrodes.

Abstract: Provided is a semiconductor device having a high switching speed. A semiconductor device (20) is provided with an n-type epitaxial layer (2) having a plurality of trenches (3) arranged at prescribed intervals (b); an embedded electrode (5) formed on an inner surface of the trench (3) through a silicon oxide film (4) to embed each trench (3); and a metal layer (7), which is capacitively coupled with the embedded electrode (5) by being arranged above the embedded electrode (5) through a silicon oxide film (6). In the semiconductor device (20), a region between the adjacent trenches (3) operates as a channel (current path)(11). A current flowing in the channel (11) is interrupted by covering the region with a depletion layer formed at the periphery of the trenches (3), and the current is permitted to flow through the channel (11) by eliminating the depletion layer at the periphery of the trenches (3).