CHIP PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME
The invention provides a chip package structure and method for fabricating the same. The chip package structure includes a carrier substrate. A plurality of isolated conductive layers is disposed on the carrier substrate. At least one chip is disposed on the carrier substrate, wherein the chip has a plurality of electrodes. The electrodes are electrically connected to the conductive layers. A conductive path is disposed in the carrier substrate, electrically connected to the electrodes through the conductive layers, wherein the conductive path comprises a plurality of laminating holes.
The present invention relates to a chip package structure and method for forming the same, and in particular relates to a light emitted chip package structure and method for forming the same.
DESCRIPTION OF THE RELATED ARTThe chip packaging process is one of the important processes for forming chips. A chip package structure, not only provides an interface for connecting chips to electronic elements, but also provides protection for chips from environmental contaminants, along with other functions.
With increasing development of the semiconductor fabrication process, chips are being formed in smaller and smaller dimensions. However, due to the ever-decreasing size and the ever-increasing density of the chips, number and density of the input/output (I/O) connections of chips have increased. Therefore, the chip area for conductive paths between chips and outside features formation is not enough. The fabrication cost can not be reduced due to a huge amount of the golden wires using as I/O connections between chip arrays and outside features, especially in package structure composed by optoelectronic chips.
Thus, a novel package structure for improving the package structure of chips and method for forming the same is desired.
BRIEF SUMMARY OF THE INVENTIONAn exemplary embodiment of a method for fabricating a chip package structure is provided. The chip package structure comprises a carrier substrate having a cavity. A plurality of isolated conductive layers is disposed on the carrier substrate; at least one chip disposed in the cavity of the carrier substrate, wherein the chip has a plurality of electrodes to electrically connect to the conductive layers. A conductive path is disposed in the carrier substrate, electrically connected to the electrodes through the conductive layers, wherein the conductive path comprises a plurality of laminated holes.
An exemplary embodiment of a method for fabricating a chip package structure is provided. The method for fabricating a chip package structure comprises providing a carrier substrate. A first hole is formed from a first surface of the carrier substrate. A second hole is formed from a second surface of the carrier substrate, connected and disposed corresponding to the first hole. A cavity is formed on the second surface of the carrier substrate. A conductive path is formed in the first hole and the second hole. A plurality of conductive layers is formed isolated from each other, electrically connected to the conductive path. At least one chip is disposed in the cavity of the carrier substrate, wherein the chip has a plurality of electrodes to electrically connect to the conductive layers.
DETAILED DESCRIPTION OF THE INVENTIONThe following description is of a mode for carrying out the invention. Wherever possible, the same reference numbers are used in the drawings and the descriptions to refer the same or like parts. In the drawings, the size of some of the elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual dimensions to practice of the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense.
Embodiments of the package structure for chips of the invention packaged by a wafer level packaging (WLP) process may be applied to active or passive devices, or electronic components with digital or analog circuits, such as optoelectronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, and physical sensors for detecting heat, light, or pressure. Particularly, a wafer level packaging (WLP) process may be applied to package semiconductor chips, such as image sensor devices, light-emitting diodes (LEDs), solar cells, RF circuits, accelerators, gyroscopes, micro actuators, surface acoustic wave devices, pressure sensors, or ink printer heads. The wafer level packaging process herein mainly means that after the packaging process is accomplished during a wafer stage, a wafer with chips is cut to obtain separate independent packages. However, in an embodiment of the invention, separate independent chips may be redistributed overlying a supporting wafer and then be packaged, which may also be referred to as a wafer level packaging process. In addition, the wafer level packaging process may also be adapted to form electronic device packages of multi-layered integrated circuit devices by stacking a plurality of wafers having integrated circuits together.
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Next, filling layers 208a″ and 208b″ are selectively formed on the hole conducting layers 206a″ and 206b″ in the holes 202a″ and 202b″. The filling layers 208a″ and 208b″ may have the same materials and formation processes as the filling layers 208a′ and 208b′.
In this embodiment, the vertically laminated holes 202a′ and 202a″ and the hole conducting layers 206a′ and 206a″ on the sidewalls of the holes 202a′ and 202a″ may construct a first conductive path 320a. Similarly, the vertically laminated holes 202b′ and 202b″ and the hole conducting layers 206b′ and 206b″ on the sidewalls of the holes 202b′ and 202b″ may construct a second conductive path 320b. Additionally, in one embodiment as shown in
Embodiments of the invention may further have many other variations. For example, the hole conducting layers of the first conductive path 320a and the second conductive path 320b may substantially fill the holes. A lateral conductive layer may be between the two laminated holes to electrically connect to the hole conducting layers. The other variations are dependant upon application and fabrication processes.
In this embodiment, the formation of the laminated holes comprise forming the upper holes and the upper conductive layers and then forming the lower holes and the lower conductive layers, but the invention is not limited thereto. Alternatively, the formation of the laminated holes may comprise forming lower holes and the lower conductive layers and then forming the upper holes and the upper conductive layers. Additionally, the cavity for the chip disposed thereon and the upper holes may be formed at the same step.
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The exemplary embodiments of the chip package structure 500 have the following advantages. For example, the chip package structure is fabricated by a wafer level package process to package the chip array. Therefore, the chip package structure has much smaller dimensions than that of the conventional wire-bonding type chip package structure. When the chip package structure is arranged in a pixel array for illumination or display, an exemplary embodiment of the chip package structure may allow the pixel array to have a smaller pitch between each light emitting device. Therefore, improving pixel continuity and visual effect. Additionally, the conductive path is constructed by laminated the upper and lower holes, wherein the upper and lower holes further comprise a lateral conductive layer therebetween to increase conductive area of the hole conducting layers.
While the invention has been described by way of example and in terms of the embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
BRIEF DESCRIPTION OF THE DRAWINGS
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- 500˜chip package structure;
- 200˜carrier substrate;
- 200a, 200b˜surface;
- 202a′, 202b′, 202a″, 202b″˜hole;
- 203˜cavity;
- 204a′, 204b′, 204a″, 204b″˜insulating layer;
- 206a′, 206b′, 206a″, 206b″, 206c″˜hole conducting layer;
- 208a′, 208b′, 208a″, 208b″˜filling layer;
- 301˜chip array;
- 302a, 302b˜chip;
- 310a, 311a˜first electrode;
- 310b, 311b˜second electrode;
- 320a˜first conductive path;
- 320b˜second conductive path;
- 324˜adhesive layer;
- 336˜fluorescent layer;
- 338˜lens structure.
Claims
1. A chip package structure, comprising:
- a carrier substrate having a cavity;
- a plurality of isolated conductive layers disposed on the carrier substrate;
- at least one chip disposed in the cavity of the carrier substrate, wherein the chip has a plurality of electrodes to electrically connect to the conductive layers; and
- a conductive path disposed in the carrier substrate, electrically connected to the electrodes through the conductive layers, wherein the conductive path comprises a plurality of laminated holes.
2. The chip package structure as claimed in claim 1, further comprising an insulating layer isolating the conductive layers and the carrier substrate or the conductive path and the carrier substrate from each other.
3. The chip package structure as claimed in claim 1, wherein the conductive layers are conformably disposed on sidewalls and a bottom portion of the cavity.
4. The chip package structure as claimed in claim 1, wherein the carrier substrate is a silicon substrate.
5. The chip package structure as claimed in claim 1, further comprising a reflection layer disposed on sidewalls and a bottom portion of the cavity.
6. The chip package structure as claimed in claim 1, wherein the conductive path passes through the carrier substrate.
7. The chip package structure as claimed in claim 6, wherein the conductive path comprises a plurality of vertically laminated holes and the conductive layers extend on a sidewall of the cavity.
8. The chip package structure as claimed in claim 7, wherein a plurality of the vertically laminated holes comprises a first hole and a second hole, wherein the first hole and the second hole comprise a lateral conductive plate therebetween, wherein the lateral conductive plate electrically connects to the conductive layers extended on the sidewall of the cavity.
9. The chip package structure as claimed in claim 7, wherein a plurality of the vertically laminated holes comprises a first hole and a second hole, wherein a surface of the first hole adjacent to the second hole is larger than a surface of the second hole adjacent to the first hole.
10. The chip package structure as claimed in claim 7, wherein a plurality of the vertically laminated holes comprises a first hole and a second hole, wherein a surface of the first hole adjacent to the second hole is larger than a surface of the second hole adjacent to the first hole, wherein the first hole and the second hole comprise a lateral conductive plate therebetween, wherein the lateral conductive plate electrically connects to the conductive layers extending on the sidewall of the cavity.
11. The chip package structure as claimed in claim 10, wherein the first hole is a lower-level hole and the second hole is an upper-level hole.
12. The chip package structure as claimed in claim 11, wherein a depth of the upper-level hole is the same to that of the cavity.
13. A method for fabricating a chip package structure, comprising:
- providing a carrier substrate;
- forming a first hole from a first surface of the carrier substrate;
- forming a second hole from a second surface of the carrier substrate, connected and disposed corresponding to the first hole;
- forming a cavity on the second surface of the carrier substrate;
- forming a conductive path in the first hole and the second hole and forming a plurality of conductive layers isolated from each other, electrically connected to the conductive path; and
- disposing at least one chip in the cavity of the carrier substrate, wherein the chip has a plurality of electrodes to electrically connect to the conductive layers.
14. The method for fabricating a chip package structure as claimed in claim 13, further comprising forming an insulating layer on the carrier substrate to isolate the conductive layers from the conductive path.
15. The method for fabricating a chip package structure as claimed in claim 14, wherein the first hole and the second hole comprise a lateral conductive plate therebetween.
16. The method for fabricating a chip package structure as claimed in claim 14, wherein a surface of the first hole adjacent to the second hole is larger than a surface of the second hole adjacent to the first hole.
17. The method for fabricating a chip package structure as claimed in claim 14, wherein the first hole and the second hole comprise a lateral conductive plate therebetween, and a surface of the first hole adjacent to the second hole is larger than a surface of the second hole adjacent to the first hole.
18. The method for fabricating a chip package structure as claimed in claim 14, wherein the first hole is a lower-level hole and the second hole is an upper-level hole.
19. The method for fabricating a chip package structure as claimed in claim 18, wherein the upper-level hole and the cavity are formed in the same step.
20. The method for fabricating a chip package structure as claimed in claim 19, wherein the upper-level hole and the lower-level hole are formed at different steps.
Type: Application
Filed: Dec 11, 2009
Publication Date: Jul 22, 2010
Inventors: Tien-Hao HUANG (Zhongli City), Shang-Yi WU (Hsinchu City), Chia-Lun TSAI (Tainan City)
Application Number: 12/636,657
International Classification: H01L 33/62 (20100101); H01L 21/50 (20060101);