Abstract: Methods and related systems are described for making an electromagnetic induction survey of a formation surrounding a cased section of a borehole. An electromagnetic transmitter and/or receiver is deployed into the cased section of the borehole. Electromagnetic survey measurements and impedance measurements relating to impedance of the transmitter and/or receiver are made while deployed in the section of the borehole. Compensation is made for the attenuation amplitude and/or phase in the electromagnetic survey measurements due to the conductive casing. The compensation is based on the impedance measurements and equivalent circuit parameters. The impedance measurements are correlated with numerical modeling results of a purely inductive electromagnetic transducer, and calculated equivalent circuit parameters are combined with the numerical modeling results.

Abstract: Disclosed herein is a very low noise fundamental mode orthogonal fluxgate magnetometer. Also disclosed is a method of measuring a magnetic field, and an integrated magnetotelluric station that can measure X, Y, and Z components of a magnetic field.

Abstract: A device and method for measuring electromagnetic signals that can be used to take measurements at or near the sea floor. The device comprises a central housing, a data management system located within the housing and at least two arms extending outwards from the housing. Each arm comprises a flexible elongate sheath attached to the housing, a sensor head, a flexible electrical cable attached to the sheath and connecting the sensor head to the data management system and a rod which is removeably locatable within the sheath. The rod is connectable relative to the housing at one end and connectable relative to the sensor head at the end remote from the housing.

Abstract: A marine electromagnetic sensor system includes a sensor cable having at least one electromagnetic sensor thereon. A first calibration electrode is disposed on the cable on one side of the sensor. A second calibration electrode is disposed on the cable on an opposite side of the sensor. A calibration power supply is coupled to the first and second calibration electrodes. A measuring circuit is coupled to the sensor. A method for calibrating marine electromagnetic survey electrodes includes imparting electric current between calibration electrodes disposed at spaced apart locations on a cable deployed in the water. Voltages impressed across a pair of electrodes disposed on the cable between the calibration electrodes are detected in response to the current. A change in sensitivity of the at least one pair of electrodes is determined using the detected voltages.

Abstract: An apparatus and method for minimizing the effects of a common mode voltage signal in downhole logging tools utilized to determine the resistivity of an adjacent portion of a borehole wall. Two current electrodes are energized by an excitation source to create an oscillatory electric field in a borehole wall. A voltage drop across a segment of the borehole wall is measured by two voltage electrodes, and the differential voltage is used in combination with a measured current flow to determine a resistivity value for the borehole wall. A common mode voltage in front of the two voltage electrodes is measured and minimized by controlling the excitation source, thereby reducing the resistivity measurement error.

Abstract: A control unit (16) of a replacement determination device charges one or more battery modules (10) as determination targets, and measures the voltage change value of the battery module (10) in a predetermined period of time from the time of stoppage of charge by using a voltage measuring device (14). If the voltage change value becomes equal to or more than a reference voltage change value consecutively a predetermined number of times which is equal to or more than one, the control unit determines that the battery module (10) needs to be replaced.

Abstract: A reliability evaluation system comprises a reliability evaluation circuit and a reliability evaluation control circuit. The reliability evaluation circuit includes a stress device array and a stress voltage generating block configured to receive a control voltage, generate stress voltages generated by using two reference voltages, and apply the stress voltages to the unit devices in a stress mode via first I/O lines according to the control voltage. The stress device array includes the unit devices that are matrix-arrayed. Each of the unit devices has a first terminal connected to one of the first I/O lines and a second terminal connected to one of second I/O lines. The reliability evaluation control circuit is configured to generate the control voltage and the two reference voltages, and test reliability of the unit devices by using the first I/O lines and the second I/O lines.

Abstract: The present invention provides an electric cable comprising a conductor element, and successively around said conductor element: an electrically-insulating layer; a metal screen; and an outer protective sheath; the cable further comprising an extruded outer layer surrounding the outer protective sheath, said extruded outer layer being directly in contact with said outer protective sheath, and being obtained from a composition containing more than 50.0 parts by weight of apolar polymer per 100 parts by weight of polymer in the composition, together with an electrically-conductive filler.

Abstract: A method and system for measuring and compensating for a leakage current in a high voltage transformer. Such a method and/or system include the use of a primary winding and a secondary winding, which can be provided on a core of a soft-magnetic material. A current transformer can be placed about the leads to both the terminals of the primary winding. The current transformer can be utilized to reliably measure the leakage current flowing from the secondary winding to the primary winding through one or more amplifiers to a ground terminal. The leakage current flows back to the transformer secondary winding through a low-side current sense resistor. The total current monitor signal can be generated by the low-side current sense resistor and the leakage current measured by the current transformer is vector-subtracted from the total current monitor signal. The result is a current monitor signal fully representative of the high voltage transformer's actual load current.

Abstract: An apparatus and method for preventing access to calibration controls includes a primary cover including a connection device, an access opening and a first through hole. The primary cover is configured to exclude access to an underlying area. The access opening is located on the primary cover to permit access to the underlying area when securing the primary cover. A shield is configured to fit over the primary cover and prevent access to the access opening. The shield includes a latch portion configured to latch on a first end portion of the primary cover and a second through hole located at a second end portion and corresponding to the first through hole of the primary cover. A security mechanism is configured to be received in the first and second through holes such that the security mechanism shows signs of tampering when unauthorized access to the underlying area is attempted.

Abstract: A method for calibrating apparatuses for determining the moisture content of products based on capacitive measurements comprises the following operating steps: Inserting a device (1) for simulating the dielectric properties of products in a measuring area of an apparatus (2) to be calibrated; taking a capacitive measurement with the apparatus (2) while the device (1) is inserted in the measuring area; modifying the device (1) settings at least once and taking the capacitive measurement again, for each different setting value; comparing each capacitive measurement taken this way with a corresponding known reference capacitive measurement; calibrating the apparatus (2) based on this comparison.

Abstract: Systems and methods to stir an electromagnetic (EM) field of an EM reverberation chamber are disclosed. A particular system includes an EM reverberation chamber. The system also includes a transmit antenna and a receive antenna operable to generate an EM field within the EM reverberation chamber. The system further includes a variable charged particle source to stir the EM field by varying introduction of charged particles into the EM field.

Abstract: An apparatus configured for built in self test (BIST) jitter measurement is described. The apparatus includes a time-to-voltage converter. The time-to-voltage converter generates a voltage signal proportional to timing jitter present in a clock/data signal input. The apparatus also includes feedback circuitry for the time-to-voltage converter. The feedback circuitry provides a ramp slope for the time-to-voltage converter. The apparatus further includes a calibration controller. The calibration controller provides control signals to the time-to-voltage converter for process-independent calibration. The apparatus also includes a sample-and-hold (S/H) circuit. The S/H circuit provides a set bias voltage to the time-to-voltage converter once calibration is complete.

Abstract: A device for detecting polarization direction of a ferroelectric is provided. From a measurement signal provided through a probe disposed in contact with or near the surface of a ferroelectric, a demodulation means generates a detection signal having a signal level corresponding to a capacitance change of the ferroelectric due to application of an alternating electric field to a capacitor component formed in the ferroelectric directly below the probe. A synchronous detection means performs synchronous detection of the detection signal based on a synchronous signal and generates a polarization direction detection signal corresponding to the polarization direction of the ferroelectric. A pseudo-noise signal generation means generates a pseudo-noise signal with the same frequency as that of the electric field signal and a different phase and amplitude therefrom.

Abstract: A resonance electric current detection apparatus is disclosed. The above apparatus comprises a detection unit which detects an electric current by a resonance of an inductor L and a capacitor C and outputs to a control unit, and a control unit which controls an electric current detected by the detection unit. With the above construction, It is possible to easily perform a LC resonance electric current control, a speaker network resonance control, an automatic gain control and a LED control by forming the detected resonance electric current as a load circuit or controlling a surge voltage which is generated in a non-load state.

Abstract: An integrated RF circuit is disclosed having an RF input port and an RF output port. The RF output port is for being coupled with a known impedance to an external circuit element such as an antenna. At least an RF circuit element is disposed along a propagation path between the RF input port and the RF output port. The RF circuit element has a first input port and a first output port and is for affecting a signal received at the first input port and providing the affected signal to the first output port. The integrated RF circuit also has a VSWR detector circuit for measuring a ratio of a characteristic of RF signals at the first input port and a same characteristic of the RF signals at the first output port and for providing an indication of the ratio at a VSWR output port. The measured ratio of the characteristic is affected by an impedance of the coupling thereby providing an indication relating to the coupling.

Abstract: The electronic circuit (1) with a capacitive sensor (2) is used for measuring a physical parameter, such as an acceleration. The sensor includes two capacitors mounted in differential, whose common electrode (Cm) can move relative to each fixed electrode of the two capacitors to alter the capacitive value of each capacitor. The electronic circuit has an interface connected to the capacitive sensor, which includes a charge transfer amplifier unit (4) connected to the common electrode (Cm), an integrator unit (5) for integrating the charges supplied by the charge transfer amplifier unit, and an excitation unit (3) arranged between the output of the first integrator unit and the sensor to polarise each fixed electrode of the sensor capacitors at a determined voltage value. A compensation capacitor (Cc) is connected to the input of the integrator unit.

Abstract: A proximity sensor for determining an approaching direction of an object is provided. Relative detection sensitivity is established in a first detection unit and a second detection unit such that a detection level of the first detection unit is greater than a detection level of the second detection unit when the object approaches from a first electrode in a direction of arranging the first electrode and a second electrode, and that the detection level of the second detection unit is greater than the first detection unit when the object approaches from a direction perpendicular to the direction of arranging the first electrode and the second electrode. A proximity position determining section is adapted to determine the approaching direction of the object based on the detection level of the first detection unit and the detection level of the second detection unit.

Abstract: A capaciatance detector is provided, which outputs an electric signal dependent on the capacitance present on an object to be measured. The capaciatance detector includes a measurement terminal to be disposed in contact with or in proximity to the object being measured; an impedance conversion circuit connected to the measurement terminal to form a resonant circuit; a reference phase oscillator for supplying a reference phase signal at a constant frequency to the resonant circuit; phase comparison means for outputting, as a capacitance detected signal, a phase difference signal indicative of the phase difference between a resonant signal, which is extracted from the resonant circuit in response to the reference phase signal being applied to the resonant circuit, and the reference phase signal; and resonance frequency regulation means for regulating the resonance frequency of the resonant circuit based on the phase difference signal.

Abstract: A device for detecting a variation in the capacitance of a variable capacitive structure, wherein the device generates voltage pulses, charges the variable capacitive structure using the voltage pulses, discharges the variable capacitive structure toward a reference capacitor, detects a voltage threshold across the terminals of the reference capacitor, determines a number of charges and/or discharges of the variable capacitive structure corresponding to the voltage threshold, and detects a variation in the number of charges and/or discharges with respect to a number of charges and/or discharges previously obtained.

Abstract: A capacitance measurement system precharges first terminals (21-0 . . . 21-k . . . 21-n) of a plurality of capacitors (25-0 . . . 25-k . . . 25), respectively, of a CDAC (capacitor digital-to-analog converter) (23) included in a SAR (successive approximation register) converter (17) to a first voltage (VDD) and pre-charges a first terminal (3-j) of a capacitor (CSENj) to a second voltage (GND). The first terminals are coupled to the first terminal of the capacitor to redistribute charges therebetween so as to generate a first voltage on the first terminals and the first terminal of the capacitor, the first voltage being representative of a capacitance of the first capacitor (CSENj). A SAR converter converts the first voltage to a digital representation (DATA) of the capacitor. The capacitance can be a touch screen capacitance.

Abstract: This invention provides for an apparatus and a method for detecting the presence of pathogenic agents with sensors containing functionalized nanostructures integrated into circuits on silicon chips. The nanostructures are functionalized with molecular transducers that recognize and bind targeted analytes which are diagnostic of the pathogenic agent of interest. The molecular transducer includes a receptor portion, which binds the analyte, and an anchor portion that attaches to the nanostructure. Upon binding of the analyte, a change in molecular configuration represented by the newly formed receptor-analyte complex creates a force that is transmitted to the nanostructure via the anchor portion of the transducer. The effect of the force transmitted to the nanostructure is to alter its conductivity. The change in conductivity of the nanotube thus represents a signal that indicates the presence of the pathogenic agent of interest.

Abstract: An electrode holder comprising a deck member with handle supporting a pair of penetrating electrodes to which a hypodermic syringe or needles may be connected and which may act as electrodes in a BIA system and/or in connection with making other electrical measurements.

Abstract: A method and apparatus for measuring the percentage of fat trim and of saleable yield of cattle and their carcasses including providing power to a transmitting circuit to transmit a signal to electrodes resulting in a potential difference across the electrodes causing a flow of current between the electrodes reflecting the impedance encountered and sending a signal reflecting such information to receiving circuits which pass that data to processing circuits which process that data with other external inputs to produce an output display reflecting an indication of the state of hydration of the animal, comprising: means for providing a voltage difference across two or more penetrating electrodes; means for maintaining said electrodes in a fixed spatial relation and in good electrical contact with the tissue on which said measurements are to be made; means for measuring the impedance in the region of or between the electrodes; means for transmitting the measured data to processing circuits which process that

Abstract: A sensing device (10) is provided for sensing whether an electrically-conductive fluid (14) has reached a predetermined level within a container (12). In this device (10), a first electrode (22) is electrically connected to a source (20) and a second electrode (24) is electrically connected to ground. When the electrode gap (26) is filled with the fluid (14), the sensing circuitry causes the electrodes (22, 24) to switch roles as the anode depending upon whether a positive voltage pulse or negative voltage pulse is being received from the source (20).

Abstract: A sensor apparatus for detecting a positional relationship includes a first electrode, an applying unit applying a charging signal with a first cycle period to the first electrode, a second electrode, a selecting unit selecting the first or second cycle period which have overlapped segment periods, an output unit outputting electrical signals supplied from the second electrode with the first cycle period, if the first cycle period is selected, and parts of the electrical signals during the segment periods, if the second cycle period is selected, a comparator comparing an amplitude of the electrical signals with a threshold value and generating a first or second comparison signal and a controller generating a proximity and non-proximity signal in response to the first and second comparison signal, respectively, so that the selecting unit selects the first and second cycle period in response to the proximity and non-proximity signal, respectively.

Abstract: The present invention relates to an electrical specific resistivity probing robot, and it is directed to automatically measuring a three-dimensional electrical specific resistivity structure of an underground shallow region by installing a plurality of probing electrodes at regular intervals along a robot-moving caterpillar to measure difference of potentials of the electrodes at a ground plane. The electrical specific resistivity probing robot of the present invention includes a frame (10); a driving means (20) installed under the frame; a pair of insulating caterpillars (30, 31) installed to both sides of a lower portion of the frame and driven by the driving means; a plurality of probing electrodes (40) installed along track (31) circumferences of the caterpillars at regular intervals; a slip ring (50) electrically slip-connected to the probing electrodes one by one; and a cable (60) electrically connected to the slip ring.

Abstract: An apparatus for testing electric characteristics of a test object including first connection terminals on a bottom surface and second connection terminals on a top surface, the apparatus comprises a test board comprising first pads on a predetermined surface; a socket configured to electrically connect the test object to the test board; and a handler configured to transport the test object to the socket. The socket comprises a first connection unit configured to be electrically connected to the first connection terminals of the test object and a second connection unit configured to be electrically connected to the second connection terminals of the test object.

Abstract: A probe head assembly for testing a device under test includes a plurality of test probes and a probe head structure. The probe head structure includes a guide plate and a template and supports a plurality of test probes that each includes a tip portion with a tip end for making electrical contact with a device under test, a curved compliant body portion and a tail portion with a tail end for making electrical contact with the space transformer. Embodiments of the invention include offsetting the position of the tail portions of the test probes with respect to the tip portions of the test probes so that the tip portions of the test probes are biased within the apertures of the guide plate, using hard stop features to help maintain the position of the test probes with respect to the guide plate and probe ramp features to improve scrubbing behavior.

Abstract: In one embodiment, a channel board-to-DIB junction multi-module is provided which includes performance critical channel electronics modules within an enclosure encasing the plurality of performance critical channel electronics modules. A coolant distribution apparatus is provided within the enclosure to provide cooling within the enclosure. A channel board connection apparatus is located at a channel board end of the channel board-to-DIB junction multi-module and a cable-less connection apparatus is located at a DIB end of the channel board-to-DIB junction multi-module.

Abstract: The terminals of a device under test are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane that includes a top contact plate facing the device under test, a bottom contact plate facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The top and bottom pins contact each other at an interface that is inclined with respect to the membrane surface normal. When compressed longitudinally, the pins translate toward each other by sliding along the interface. The sliding is largely longitudinal, with a small and desirable lateral component determined by the inclination of the interface.

Abstract: An integrated circuit (200) comprises a functional block (130) conductively coupled to a supply rail (110) via one or more switches (115). The IC further comprises selection means (220) responsive to a test enable signal for activating the one or more switches (115) in a test mode of the IC and evaluation means such as a comparator (230) having a first input coupled to a reference signal source (215) and having a second input coupled to a node (225) between the one or more switches (115) and the functional block (130) for evaluating the behaviour of the one or more switches (115) based on the reference signal and a signal from the node (225). Thus, the present invention provides a design for testability solution for testing power switches.

Abstract: The magnitude of an amplitude waveform of an electromagnetic wave generated when irradiating a pulse laser beam to a structure A including diffusion regions provided in the structure of a semiconductor device to be inspected is compared with the magnitude of an amplitude waveform of an electromagnetic wave radiated when irradiating the pulse laser beam to a structure A of a reference device measured in advance, and the detection sensitivity of the electromagnetic wave is corrected (S14). Thereafter, measurement errors caused by variations in the detection sensitivity of electromagnetic waves of an inspecting apparatus are eliminated by inspecting the semiconductor device as an inspection target, so that the quality of the semiconductor device is precisely determined (S16).

Abstract: A method for configuring a combinational switching matrix comprises the steps of setting a first switching module and a second switching module, coupling at least one of the output ports of the first switching module with at least one of the input ports of the second switching module to form the combinational switching matrix, building a connection mapping table based on the coupling relationship between the output port of the first switching module and the input port of the second switching module, and displaying a channel switching interface showing the input terminals, the output terminals, and the on/off states of the virtual switching devices of the combinational switching matrix.

Abstract: A power gating circuit includes a logic circuit, a switching element and a retention flip-flop. The logic circuit is coupled between a first power rail and a virtual power rail. The switching element selectively couples the virtual power rail to a second power rail in response to a mode control signal indicating an active mode or a standby mode. The retention flip-flop selectively performs a flip-flop operation or a data retention operation in response to a voltage of the virtual power rail.

Abstract: A cell based design layout of an application specific integrated circuit (ASIC) having a function has reduceddecreased power leakage because functionally unconnected additional cells or spare cells of the integrated design layout are unconnected to the power supplies Vdd and Vss.

Abstract: A low voltage electronic module interface, with a low voltage interface for an electronic module receiving a constant current from a body control module, the interface including a reverse current protection circuit 152; and a switch 154 operably connected in series with the reverse current protection circuit 152, the switch 154 being responsive to a status signal 144. The reverse current protection circuit 152 and the switch 154 form a low voltage electronic module interface circuit 150 having a resistance; and the resistance is selected so voltage across the low voltage electronic module interface circuit 150 is less than 2.70 Volts when the switch 154 is closed and the constant current 124 flows through the low voltage electronic module interface circuit 150.

Abstract: A semiconductor integrated circuit includes logic circuits connected in a plurality of stages, a voltage-level inverting unit that is inserted in a signal transmission path of the logic circuits and inverts a voltage level input to the logic circuits, and an inversion-timing control unit that controls inversion timing for the voltage level inverted by the voltage-level inverting unit.

Abstract: A logic circuit includes a logic gate unit, an inverter, and a switching circuit. The logic gate unit receives a power supply voltage and an input signal to output a first signal. The inverter receives the first signal to output a second signal. The switching circuit provides one of first and second power supply voltages as the power supply voltage of the logic gate unit in response to the first and second signals. The first power supply voltage and the second power supply voltage have different voltage levels, thus enabling stable level shifting.

Abstract: A receiver for receiving a reduced swing signal from a transmission channel is disclosed, in which the swing of the reduced swing signal is less than the power supply of the receiver and possibly is less than the power supply of the transmitter. The receiver comprises a level shifter for offsetting the reduced swing signal, and an amplifier which receives both the reduced swing signal and its offset to produce a full swing signal output referenced to the power supply of the receiver. The full swing signal can thereafter be buffered, and eventually can be captured by a clock. Optionally, the disclosed reduced swing receiver also contains calibration circuitry for improving the integrity of the full swing signal output, and in particular for countering the effects of process, and in some embodiments temperature, variations, which alter the characteristics of the transistors which make up the receiver circuitry.

Abstract: A computer readable storage medium includes executable instructions to receive a specification of a combinational logic circuit. The specification of the combinational logic circuit is converted to a Single-Rail un-encoded circuit and a Dual-Rail encoded circuit, which periodically encodes a null value, a first valid state and a second valid state on two wires. A logic operation of the Single-Rail un-encoded circuit transpires during processing of a null value by the Dual-Rail encoded circuit.

Abstract: An address decoder that sets an address of a module connected to a bus includes a level comparator, an edge detector, and an output decoder. The level comparator compares an SDA signal, which is input to an SDA terminal, with an address selection signal, which is input to an ADDR terminal, and outputs a comparison result. When the two signals match, the comparison is repeated until slave addresses are all received. When the two signals do not match, subsequent comparisons are not performed. The edge detector detects an edge of the address selection signal input to the ADDR terminal. The output decoder sets an address corresponding to the connected destination of the ADDR terminal to determine an address of a slave module connected to the address decoder.

Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor, and an n-type transistor. The p-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The n-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection.

Abstract: A clock detector is provided. The clock detector generally comprises a filter, a first branch, a second branch, a latch, and logic. The filter is adapted to receive a clock signal and is coupled to a low threshold inverter in the first branch and a high threshold inverter in the second branch. The latch is adapted to receive the clock signal and is coupled to the first branch, while the logic is coupled to the node between the first branch and the latch, an output of the latch, and the second branch so that it can output a clock detection signal.

Abstract: A method of detecting a minimum operational frequency includes: generating a signal that becomes an oscillating signal at a first predetermined frequency; and generating a logic signal to provide a level transition when a frequency of the oscillating signal reaches a second predetermined frequency corresponding to the minimum operational frequency. The logic signal is generated by: providing a transistor that is activated at the second predetermined frequency; providing a capacitor; storing charges in the capacitor when the oscillating signal is below the second predetermined frequency; discharging the capacitor when the transistor is activated by the oscillating signal; and outputting the logic signal when the capacitor discharges.

Abstract: The present invention provides a system and a method for driving a differential signal which includes a differential data input, a plurality of switches coupled to a current source for steering current depending on the differential data input, a first differential output and a second differential output and a coupled to at least two of the plurality of switches and a first source follower and a second source follower coupled to the first differential output for controlling output impedance. This architecture prevents the common mode noise reflected from the driver from becoming a differential signal and meets the requirements of the LVDS and SubLVDS standard down till 1.62V. Also this architecture is capable of operating in Gbps range making it a high-speed differential driver with very low power.

Abstract: In an embodiment, an integrated circuit comprises core circuitry and at least one driver circuit. The core circuitry is powered by a first supply voltage during use, and comprises a control circuit configured to generate a pull up control signal, a pull down control signal, and at least one reference voltage. The driver circuit is powered by a second supply voltage during use, the second supply voltage having a greater magnitude than the first supply voltage. The driver circuit is connected to a pad to be connected to a pin on a package of the integrated circuit. The driver circuit comprises a cascode connection of a first transistor and a second transistor, and a capacitor coupled between a first gate terminal of the first transistor and a second gate terminal of the second transistor. The first gate terminal is coupled to receive the pull down control signal.

Abstract: A low voltage differential signalling driver is provided in which a first output node and a second output node provide a differential signal. First differential steering switch circuitry is switched in dependence on a differential input signal to selectively connect the first output node to a voltage supply via a current source, whilst second differential steering circuitry is switched in dependence on an inverse version of the differential input signal to connect the second output node to the voltage supply via the current source. Slew control circuitry is provided, configured to establish a current discharge path for the current source during the polarity transition of the differential input signal, thus maintaining a symmetric slew rate of the output signals at the first output node and second output node.

Abstract: A drive circuit wherein any abnormality of a semiconductor element is prevented from being erroneously sensed in a case where a gate “ON” command has entered in a state in which a gate voltage of the semiconductor element has not lowered fully. A detection process for a controlled variable of the semiconductor element is permitted only within a period which corresponds to a controlled variable of the semiconductor element at the time when an “ON” signal has been inputted to a control circuit, and a detected controlled variable which is detected within the period and a comparison controlled variable which is set in correspondence with the controlled variable are compared so as to output an abnormality signal, whereby the semiconductor element is turn-off at a speed lower than in normal turn-off.

Abstract: A high-side transistor and a low-side transistor each has gate electrodes configured so as to allow signals to be input and output via a driving contact and a detection contact provided at different positions. When a control signal is at a first level and a signal output from the detection contact on the low-side transistor side is at a low level, the high-side driver applies a low-level signal to the driving contact on the high-side transistor side. When the control signal is at a second level and a signal output from the detection contact on the high-side transistor side is at a high level, the low-side driver applies a high-level signal to the driving contact on the low-side transistor side.