Abstract: The present invention provides a circuit for driving a display panel using a driving capacitor, comprising an analog-to-digital converter receiving an analog input signal to generate a digital signal, a driving capacitor receiving the digital signal to generate a driving signal for the display panel, and a switching circuit in response to a switching signal, selectively coupling the analog-to-digital converter to the driving capacitor for transmission of the digital signal and coupling the driving capacitor to the display panel for transmission of the driving signal. Thus, the circuit area needed for a source driver processing images of large bit number is reduced, which decreases the cost. Further, the power system of the display having a large dynamic range of voltage can be also simplified.

Abstract: A buck-boost power converter includes a power stage to convert an input voltage to an output voltage, an error amplifier to generate an error signal according to a reference voltage and a feedback signal proportional to the output voltage, a ramp generator to provide two ramp signals, and two comparators to generate two control signals according to the error signal and the two ramp signals to drive the power stage. By using feed-forward technique, one of the two ramp signals has a peak varying with the input voltage and the other ramp signal has a valley varying with the input voltage, so that the power converter has fast line response.

Abstract: A semiconductor device has a first MOS transistor being connected between a signal terminal and a first power supply line and having a gate connected to a second power supply line; a first capacitive element connected between the signal terminal and the second power supply line; a second MOS transistor being connected between the signal terminal and the second power supply line and having a gate connected to a first terminal; a third MOS transistor being connected between the first power supply line and the first terminal and having a gate connected to the second power supply line; a fourth MOS transistor being connected between the first terminal and a second terminal and having a gate connected to the second power supply line; a second capacitive element connected between the first power supply line and the second terminal; and a fifth MOS transistor being connected between the second terminal and the second power supply line.

Abstract: A data outputting apparatus of a semiconductor integrated circuit if presented for use in standardizing output timing brought about by different electrical output path lengths. The apparatus includes a data clock signal generating section and a data output section. The data clock signal generating section is configured to use an external clock signal in order to generate a plurality of data clock signals in which output timings of the data clock signals vary depending on a data output mode. The data output section is configured to be controlled by the plurality of data clock signals to output inputted data to the outside through a plurality of data input/output pads that have different path lengths.

Abstract: A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an operation timing of the data input/output circuit. The DLL circuit has a first mode for controlling a phase of the internal clock in a precise manner and a second mode for operating with low power consumption. When the data input/output circuit does not perform an ODT operation, the DLL circuit operates in the first mode, and when the data input/output circuit performs the ODT operation, the DLL circuit operates in the second mode. In this manner, the operation mode of the DLL circuit is switched over depending on the ODT operation, so that the power consumption in the CDT operation in which strict phase control is not required can be reduced.

Abstract: A digital electronic device is provided with a first and second sequential logic unit (SS1, SS2), each for receiving an input signal (D) and for outputting a first and second output signal (Q, QF), respectively. The electronic device furthermore comprises a comparator unit (C) for comparing the first and second output signals (Q, QF) and an adaptive clock generator unit (ACG) for generating a first and second internal clock (CK, CKF) for the first and second sequential logic unit (SS1, SS2), respectively. In a self-tuning mode, the adaptive clock generator unit (ACG) is adapted to delay the first and second internal clock signals (CK, CKF) with respect to the other internal clock signal (CKF). The delay induced by the adaptive control generator unit (ACG) is dependent on the result of the comparison unit (C). In a normal operation mode the adaptive control generator unit (ACG) is adapted to maintain the delay between the first and second internal clock signals constant.

Abstract: In a synchronous semiconductor device (250), an input/output control circuit is formed of a clock input I/O (260), a clock control signal input I/O (270) and a signal change detection circuit (280). The clock input I/O (260) includes a first input buffer (264) having a large threshold, a second input buffer (266) having a small threshold and an input selector (268). The signal change detection circuit (280) controls the input selector (268) so that a first input from the first input buffer (264) is normally selected and a second input from the second input buffer (266) is temporarily selected only when the signal change detection circuit (280) detects that a logic level of a clock control signal (279) is changed from a non-activated level to an activated level.

Abstract: A bipolar pulse generator is implemented in a simple structure while providing a high efficiency design having a relatively low total size, while still allowing access by fibers used to control a photoconductive switch that activates the generator. The bipolar pulse generator includes a stacked Blumlein generator structure with an additional transmission line connected to a load at its near end and short-circuited at its distal end. An extra transmission line is positioned between the Blumlein generator's structure and the load provides specified limited gap between positive and negative sub-pulses. The bipolar pulse generator further includes a bended Blumlein generator structure, in which an existing intrinsic “stray” transmission line is used to provide the bipolar pulse. Still further, bipolar pulse generator includes stepped transmission lines, with additional switches positioned between steps, which are charged by different voltages.

Abstract: A phase shift generation circuit has an edge detector, which receives an input pulse signal and outputs a first and a second edge signal denoting the time of occurrence of the first and second edges of the input pulse signal. The circuit also has a divide by N circuit, which receives a first clock signal and a group of signals representing a number N, and outputs a second clock signal, said a second clock signal having a frequency equal to the frequency of said first clock signal divided by the number N. The circuit further comprises a pulse counter, which receives the first edge signal and the second clock signal, and outputs a group of signals representing the number of the second clock pulses between occurrences of the first edge signal. The circuit has a first recycling timer, which receives the number of second clock pulses, the first edge signal and the first clock signal, and outputs a group of pulses approximating a uniformly spaced group across the time duration of the period of the input pulse.

Abstract: A delay cell structure that inversely responds to temperature is provided. A first current mirror includes first and second transistors having sources commonly connected to a power supply terminal. A second current mirror includes third and fourth transistors having drains connected to the channels of the first and second transistors and sources commonly connected to a ground terminal. A resistor is connected between the drains of the first and second transistors. An inverter is provided between the drains of the second and fourth transistors so as to face the resistor and outputting a delay signal that is later than input signal by a delay time proportional to the threshold voltages of the first and third transistors which vary as a function of temperature.

Abstract: In a method of generating clock signals for a level-sensitive scan design latch, at least one test input signal is transmitted to a plurality of splitter leaves. Once the test input signal is stabilized at each of the splitter leaves, generating a shaped oscillator clock signal having a predetermined pattern of pulses from a central root is generated. At the plurality of splitter leaves, the test input signal is logically combined with the shaped oscillator clock signal, thereby generating a first latch clock signal and a second latch clock signal. The logically combining action includes applying a delay of less than one clock cycle to the shaped oscillator clock signal to generate a delayed oscillator clock signal; logically combining the delayed oscillator clock signal with a second signal so as to generate the first latch clock signal; and logically combining the shaped oscillator clock signal with a third signal so as to generate the second latch clock signal.

Abstract: In a particular embodiment, a method of generating an advanced gating cell clock tree includes determining a timing margin for a path between a clock gating cell and a digital data storage element such as a latch or flip flop. The circuit contains a clock source and when the timing margin for the path meets a predetermined threshold, the clock gating cell is automatically moved closer to the clock source. In a particular embodiment, the timing margin is automatically determined. A clock tree synthesis is performed to insert one or more buffers into the path and create an advanced gating cell clock tree.

Abstract: The present invention relates to a method and an apparatus, during a phase switching process, for choosing all of outputted phases upon the clock phases devoid of phase switching so as to avoid glitches during clock switching. Compared with the conventional approach for removing glitches by controlling a clock switching sequence, an improvement of a phase rotator is further disclosed in the present invention, which eliminates the glitches of the outputted phase clock so as to realize a glitch-less phase switching in a phase interpolation circuit.

Abstract: Dynamic grounding including monitoring the floating DC outputs of a power amplifier, detecting an imbalance in the floating DC outputs, generating a compensation signal in response to a detected imbalance, and adjusting the power amplifier to re-balance the floating DC outputs and suppress transients.

Abstract: An MIPI interface is connected to two sensor sources that each may be transferring both high and low speed information, typically video information in the high speed state. The clock signals are monitored and when one of the clock signals exceed a threshold, an analog switch between the MIPI interface and the sensors, may connect the other source to the MIPI interface.

Abstract: The invention relates to a method for obtaining temperature values from at least two thermal sensors arranged on resources within a three-dimensional die structure determining at least a partial three-dimensional temperature distribution for said die structure and controlling activity of said resources of said dies in response to said three-dimensional temperature distribution.

Abstract: To compensate for changes in temperature, a pair of bipolar transistors is connected to a voltage divider and receives a differential voltage that varies with temperature. The voltage divider includes a set of resistors placed in parallel. The set of resistors has a resistance that changes with temperature. As the resistance changes with temperature, the differential voltage provided by the voltage divider changes in proportion to a change in thermal voltage.

Abstract: The present invention relates to a LIN receiver having sleep/wake-up functionality, which has an input (LINI) to a LIN bus (LIN), an output (RXDO), terminals for at least one supply voltage (BVDD), and transistors (M1 through M17), the transistors (M1 through M17) being switched to activate the receiver in the recessive state of the LIN bus via a state change on the LIN bus into an active state of the receiver. In particular, the input (LINI) is connected between components of a voltage-to-current converter (SSW), in particular between a first and a second resistors, (R2, R2).

Abstract: A CMOS bias circuit includes a starter circuits and a started circuit part which supplies a current to the outside. The starter circuits has a connection node (first terminal) between it and the started circuit part. The starter circuits includes a first MOS transistor connected at its drain to the first terminal, a first current supply circuit which supplies a starter current to the started circuit via the first MOS transistor, and a circuit which supplies a second current in a direction that interrupts a current flowing through the first MOS transistor to a node between the first MOS transistor and the first current supply circuit in accordance with a potential at the first terminal. The starter circuits has a function of preventing a current flowing between the drain and source of the first MOS transistor in the opposite direction by increasing or decreasing a gate bias of the first MOS transistor in accordance with a value of the second current.

Abstract: A measurement device independent of an integrated circuit including a transistor is disclosed. A current supply provides a first current and a second current. A switching unit transmits the first or the second current to the transistor. A current detection unit generates a first voltage and a second voltage according to a first base current of the transistor and the first current and generates a third voltage and a fourth voltage according to a second base current of the transistor and the second current. A voltage processing unit processes the first and the second voltages to generate a first differential value and processes the third and the fourth voltages to generate a second difference value. A calculation unit divides the second differential value by the first differential value to obtain a current ratio and adjusts at least one of the first and the second currents according to the current ratio.

Abstract: A power supply which supplies power to a circuit board includes a support unit, an electricity output unit and a voltage converting module. The circuit board, the electricity output unit and the voltage converting module are electrically connected to the support unit. The voltage converting module can convert an output voltage of the electricity output unit to a working voltage of the circuit board. The power supply has a low manufacturing cost and can support an electricity output unit with different voltage.

Abstract: The present invention provides a solution to avoid the robustness problems of sub-threshold circuits by switching small parts of circuits to nominal-voltage only when they are being used, and switching them back to sub-threshold levels when the operation finishes. Such “hybrid sub-threshold” approach is capable of supporting ultra-low power operation without the disadvantages of sub-threshold circuits. Hybrid power saving mode for logic circuits provide significant power saving and fast recovery time without performance degradation.

Abstract: A type-A demodulator comprising a first rectifier configured to rectify a radio frequency (RF) signal received through an antenna and output a first voltage, a second rectifier configured to rectify the voltage of the RF signal received through the antenna and output a second voltage having a different voltage level than the first voltage, and a pause data detector configured to compare the first voltage with the second voltage and detect received pause data.

Abstract: Signal processing circuit for voltage signals from electrodes of a magneto-inductive, flow measuring device, wherein two measuring electrodes are connected with a fully differentially working amplifier having two inputs and two outputs.

Abstract: An electronic circuit includes a transimpedance amplifier, a bypass circuit that allows a part of an input signal to be applied to the transimpedance amplifier to flow through the bypass circuit so as to bypass the transimpedance amplifier on the basis of a control signal, and a control signal circuit that includes a hold circuit having a time constant that is variable on the basis of a time constant control signal and generates the control signal.

Abstract: A system and method are provided for delivering power to a dynamic load. The system includes a power supply providing DC power having a substantially constant power open loop response, a power amplifier for converting the DC power to RF power, a sensor for measuring voltage, current and phase angle between voltage and current vectors associated with the RF power, an electrically controllable impedance matching system to modify the impedance of the power amplifier to at least a substantially matched impedance of a dynamic load, and a controller for controlling the electrically controllable impedance matching system. The system further includes a sensor calibration measuring module for determining power delivered by the power amplifier, an electronic matching system calibration module for determining power delivered to a dynamic load, and a power dissipation module for calculating power dissipated in the electrically controllable impedance matching system.

Abstract: The present invention relates to an electronic device that includes an integrated power comparator circuit (1) for a self-oscillating class D system (100). The integrated power comparator circuit (1) has a modulation stage (10), wherein the modulation stage (10) comprises a compensation circuit (40) for providing a compensation signal to the modulation stage, which is dimensioned for compensating a variation of a process parameter for smoothing initialization of the self-oscillating class D system (100).

Abstract: A class D amplifier circuit for generating a pulse signal whose pulse width is modulated in response to an input signal, the class D amplifier circuit includes first to fifth switching elements, a first capacitance element and a control section. The control section controls transition between a conduction state and a non-conduction state of each of the first to fifth switching elements to control a current direction flowing into a load having a first end electrically connected to the output end and a second end set to the reference potential, so that the current flows from the first end of the load to the second end of the load at a first timing and the current flows from the second end of the load to the first end of the load at a second timing.

Abstract: A method and system for providing automatic gain control for a differential amplifier are provided. An impedance network is set to have a first impedance that corresponds to a first gain for a differential amplifier, which amplifies an input signal by the first gain. Once the amplified input signal is greater than a first threshold voltage, the impedance network is set to have a second impedance that corresponds to a second gain for the differential amplifier, which amplifies the input signal. Once amplified input signal is greater than a second threshold voltage and a predetermined period has lapsed, the impedance network is reset to have the first impedance that corresponds to a first gain for the differential amplifier.

Abstract: A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving differential input signals and generating differential internal signals as biased in response to an averaging of the differential internal signals. The input buffer further includes a second stage coupled to the differential internal signals and configured to generate differential output signals. A memory device includes a memory array with the respective input buffer. Differential input signals are received and differential internal signals are generated as biased in response to an averaging of the differential internal signals. Differential output signals are generated in a second stage from the differential internal signals.

Abstract: An amplifier circuit, comprising a differential input stage (M1, M2), two cross-coupled current mirrors (M3, M4; M5, M6) coupled to respective outputs of the differential input stage (M1, M2), and a minimum selector circuit (M11, M12, M13, M14) coupled to outputs of the current mirrors.

Abstract: An amplification circuit includes a semiconductor amplification element, a current feedback circuit that is connected to a terminal close to a ground side of the semiconductor amplification element and can control gain reduction, and a voltage feedback circuit that is connected between an input terminal and an output terminal of the semiconductor amplification element and can control feedback voltage. The feedback voltage of the voltage feedback circuit may be varied according to the gain reduction controlled by the current feedback circuit.

Abstract: Aspects of a system for a power amplifier with an on-package matching transformer may include a DC/DC converter that enables generation of a bias voltage level within an IC die based on an amplitude of an input signal to a PA circuit within the IC die. The bias voltage level may be applied to a transformer, which is external to the IC die but internal to an IC package containing the IC die and/or a circuit board containing the IC package. One or more amplifier bias voltage levels, derived from the bias voltage level applied to the transformer, may be applied to the PA circuit.

Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.

Abstract: A semiconductor device for transmitting-signal amplification which has a fine resolution, a high dynamic range, a small occupied area, and low power consumption, is realized. An input signal amplitude is reduced every one half by a ladder network, and a transconductance amplifier stage is arranged corresponding to each node of the ladder network. An output of the transconductance amplifier stage is coupled to an output signal line in common. According to a control word WC<21:0>, the transconductance amplifier stage is enabled selectively, and the output current which appears in the output signal line is added.

Abstract: A method and system for modulating logic clock oscillator frequency based on voltage supply. The system comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation. The device is configured to use supply voltage as an independent variable to optimize device parameters for voltage variations. The invention is also directed to a design structure on which a circuit resides.

Abstract: A radio circuit may be driven by a high frequency oscillator such as a crystal oscillator that may have sleep and wake time intervals. The sleep time interval length may be adjusted. A low frequency oscillator or low power oscillator (LPO) that may experience frequency drift may regulate the sleep and/or wake time intervals. The frequency drift may be detected based on two or more LPO calibrations and/or one or more clock adjustments. The LPO frequency drift may be detected based on an LPO frequency sampled after a first LPO calibration and a corresponding LPO clock adjustment, a second LPO frequency sampled after a second LPO calibration and a time interval between the two frequency samples. The LPO may be calibrated based on the HFCXO output. Sleep time intervals may be adjusted by adding and/or subtracting a time interval to an expected time to wake the radio circuit.

Abstract: A surface acoustic wave (“SAW”) sensor includes; a first signal generator which generates a first signal having a predetermined frequency bandwidth using a pseudo random sequence, a second signal generator which generates a second signal with a predetermined frequency, a signal blender which blends the first signal with the second signal to generate a blended signal having the predetermined frequency bandwidth with the predetermined frequency as a center frequency, a wave generator which generates a surface acoustic wave using the blended signal, which converts the surface acoustic wave into a third signal after the surface acoustic wave travels a predetermined distance, and which outputs the third signal, and a signal detector which detects a change in the third signal from the wave generator to sense a substance bound to the wave generator.

Abstract: A constant-temperature type crystal oscillator includes: a surface-mount crystal unit, in which a crystal element is housed in a case main body to hermetically encapsulate the crystal element with a metal cover, and which includes a crystal terminal serving as a mounting terminal that is electrically connected to at least the crystal element on an outer bottom face of the case main body; a thermistor that detects an operational temperature of the surface-mount crystal unit; and a circuit substrate, on which elements forming an oscillator circuit and elements forming a temperature control circuit along with the thermistor are installed. The thermistor includes a first and second terminal electrode and a temperature detecting electrode that is electrically independent of the first and second terminal electrode. The temperature detecting electrode is electrically connected to the crystal terminal of the surface-mount crystal unit through a circuit pattern formed on the circuit substrate.

Abstract: A mixed-mode PLL is disclosed. The mixed-mode PLL comprises a digital sigma-delta modulator, a low pass filter, and a digital controlled oscillator. The digital sigma-delta modulator receives a fractional bit signal. The low pass filter is coupled to the digital sigma-delta modulator. The low pass filter receives an output signal of the digital sigma-delta modulator and converts the output signal to an analog control signal. The digital controlled oscillator comprises a varactor dynamically coupled to the low pass filter and receiving the analog control signal.

Abstract: In one embodiment, a system for generating an oscillating signal includes a transconductance amplifier comprising a single-ended output and a differential input. The system also includes only one feedback loop coupled to the transconductance amplifier. The feedback loop includes a low pass filter configured to receive the output of the transconductance amplifier. Also, the feedback loop includes a high pass filter configured to receive the output of the first low pass filter and output a signal to only one terminal of the differential input of the transconductance amplifier.

Abstract: An oscillator arrangement is specified, in which a relaxation oscillator is refined to the extent that the comparator (2) to be used for comparing the voltage across a charge storage device (1) with a switching threshold (VTH) is a current comparator with two current branches (5, 6). One of these two current branches is used in the present case for guiding a charging or discharging current of the charge storage device (1). In this way, a current branch is eliminated, so that the proposed principle is preferably suitable for so-called ultra low power applications.

Abstract: A self-excited oscillation circuit of the invention includes a turn-OFF transistor that turns OFF a transistor, a turn-OFF capacitor that outputs a voltage to the base of the turn-OFF transistor, and a bias resistance that charges the turn-OFF capacitor with a voltage in magnitude corresponding to a drain current that flows when the transistor turns ON. A resistance is connected between the turn-OFF capacitor and a power supply portion. Accordingly, charges are accumulated in the turn-OFF capacitor so that the voltage will not drop to or below a bias voltage. It thus becomes possible to make the bias resistance smaller, which can in turn reduce an energy loss at the bias resistance.

Abstract: The present invention relates in general to transferring the envelope information of a polar modulated signal to a varying pulsewidth signal, while the phase modulation is direct transferred to the phase modulation of this PWM signal. Accordingly, the resultant signal is a PWM-PPM-signal. Such a signal can efficiently amplified by use of switching amplifying stages. By the present invention four pre-distorted baseband signals are applied basically to 4 linear RF mixers and a two adders, which are, the only needed external RF building blocks to build the modulator according to the invention. That is, the basic idea of the invention resides in the way of modulation of the four baseband signals and the way of combining of the RF modulated signals.

Abstract: An apparatus for phase modulation includes a delay locked loop configured to generate from a reference signal a plurality of phase shifted signals, each of the phase shifted signals being locked to the reference signal and having a different phase shift from the other phase shifted signals with respect to the reference signal, and a multiplexer configured to select one of the phase shifted signals.

Abstract: A hybrid Marchand/back-wave balun includes a first pair of coupled sections having a first primary section and first secondary section; a second pair of coupled sections having a second primary section and second secondary section; a first reactance interconnecting the first and second primary sections and a second reactance interconnecting the first and second secondary sections; one of the reactances being open at high frequency and shorted at low frequency, the other reactance being shorted at high frequency and open at low frequency for selectively providing low frequency Marchand/high frequency back-wave function and high frequency Marchand/low frequency back-wave function; and a double balanced mixer using same.

Abstract: A semiconductor die has an RF coupler and balun integrated on a common substrate. The RF coupler includes first and second conductive traces formed in close proximity. The RF coupler further includes a resistor. The balun includes a primary coil and two secondary coils. A first capacitor is coupled between first and second terminals of the semiconductor die. A second capacitor is coupled between a third terminal of the semiconductor die and a ground terminal. A third capacitor is coupled between a fourth terminal of the semiconductor die and the ground terminal. A fourth capacitor is coupled between the high side and low side of the primary coil. The integration of the RF coupler and balun on the common substrate offers flexible coupling strength and signal directivity, and further improves electrical performance due to short lead lengths, reduces form factor, and increases manufacturing yield.

Abstract: A bipolar pulse generator includes two, two-conductor transmission lines coupled together with a load positioned between the two transmission lines. Two segments of one transmission line are charged and switchably coupled to two segments of the other transmission line to produce a bipolar pulse on the matched load. The generator may include two transmission line structures coupled together with a load positioned between each transmission line structures. The first transmission line structure may include a stepped transmission line and an embedded transmission line segment. A switch is coupled between the embedded transmission line segment and another segment of the transmission line structure. During operation, the first transmission line structure is charged to a potential with the switch in the open position and, when the switch is closed, the charge on the first transmission line structure together with the second transmission line structure generates a bipolar pulse on the matched load.

Abstract: An apparatus including: a first transistor including a first port configured for connection to an antenna having a first impedance at a first frequency band, and a second port configured for connection to radio circuitry, the first port of the first transistor being configured to have an impedance at the first frequency band substantially equal to the complex conjugate of the first impedance.

Abstract: Disclosed herein is a semiconductor device including: a semiconductor circuit element configured to process an electrical signal having a predetermined frequency; and a transmission line configured to be connected to the semiconductor circuit element via a wire and transmit the electrical signal. An impedance matching pattern having a symmetric shape with respect to a direction of the transmission line is provided in the transmission line.