Patents Issued in October 12, 2010
  • Patent number: 7812336
    Abstract: At least one non-volatile device is coupled to a first Coulomb island. The floating gates of these non-volatile devices are connected to the island and can charge the Coulomb islands. One device can charge the island positively while a second device can be used to charge the island negatively. The Coulomb island can have a small probe opening where a charge can be introduced by using mechanical means such as an external probe or a MEMS switch. A fully charged capacitor formed in a first substrate can provide additional energy to a levitated substrate if the first substrate is connected to the levitated substrate. Bonding wires can be attached to a substrate that is attached to a mother substrate. Then, Coulomb forces can levitate the substrate from the mother substrate and the bonding wires can provide a source of power to the levitated substrate.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: October 12, 2010
    Assignee: Metamems Corp.
    Inventor: Thaddeus John Gabara
  • Patent number: 7812337
    Abstract: A nitride semiconductor light emitting device includes a first nitride semiconductor layer, a first Al-doped nitride semiconductor layer formed on the first semiconductor layer, an activation layer formed on the first Al-doped nitride semiconductor buffer layer, and a second nitride semiconductor layer formed on the activation layer. Another nitride semiconductor light emitting device includes a first nitride semiconductor layer, an activation layer formed on the first nitride semiconductor layer, a second Al-doped nitride semiconductor buffer layer formed on the activation layer, and a second nitride semiconductor layer formed on the second Al-doped nitride semiconductor buffer layer.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: October 12, 2010
    Assignee: LG Innotek Co., Ltd.
    Inventor: Suk Hun Lee
  • Patent number: 7812338
    Abstract: A semiconductor light emitting device may include an n-type contact layer on a substrate. An active layer may be on the n-type contact layer and/or include two or more quantum well layers and two or more barrier layers. A p-type contact layer may be on the active layer. Energy band gaps of the quantum well layers may be larger as the quantum well layers are closer to the n-type contact layer from the p-type contact layer, thicknesses of the quantum well layers may be smaller as the quantum well layers are closer to the n-type contact layer from the p-type contact layer, and/or energy band gaps of the barrier layers may be larger as the barrier layers are closer to the n-type contact layer from the p-type contact layer.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: October 12, 2010
    Assignee: Samsung Led Co., Ltd.
    Inventor: Han-youl Ryu
  • Patent number: 7812339
    Abstract: A semiconductor device may include a semiconductor substrate having a surface, a shallow trench isolation (STI) region in the semiconductor substrate and extending above the surface thereof, and a superlattice layer adjacent the surface of the semiconductor substrate and comprising a plurality of stacked groups of layers. More particularly, each group of layers of the superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, at least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: October 12, 2010
    Assignee: Mears Technologies, Inc.
    Inventors: Robert J. Mears, Kalipatnam Vivek Rao
  • Patent number: 7812340
    Abstract: A method of forming a semiconductor structure (and the resulting structure), includes straining a free-standing semiconductor, and fixing the strained, free-standing semiconductor to a substrate.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: October 12, 2010
    Assignee: International Business Machines Corporation
    Inventors: Guy Moshe Cohen, Patricia May Mooney
  • Patent number: 7812341
    Abstract: The present invention relates to a compound having an oxadiazole ring structure having a substituted pyridyl group connected thereto, represented by the following general formula (1). According to the present invention, it becomes possible to provide an organic compound having excellent characteristic of high stability in a thin film state, and the emission efficiency and durability of conventional organic EL devices can be remarkably improved.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: October 12, 2010
    Assignee: Hodogaya Chemical Co., Ltd.
    Inventors: Tetsuzo Miki, Makoto Nagaoka, Shuichi Hayashi, Yoshio Taniguchi, Musubu Ichikawa
  • Patent number: 7812342
    Abstract: Provided are a nano semiconductor sheet, a thin film transistor (TFT) using the nano semiconductor sheet, and a flat panel display using nano semiconductor sheet. The nano semiconductor sheet has excellent characteristics, can be manufactured at room temperature, and has good flexibility. The nano semiconductor sheet includes: a first film and a second film disposed on at least one side of or inside of the first film, and includes a plurality of nano particles arranged substantially in parallel to each other. In addition, provided are a method of manufacturing a nano semiconductor sheet and methods of manufacturing a TFT and a flat panel display using the nano semiconductor sheet. The method of manufacturing a nano semiconductor sheet, includes: forming first polymer micro-fibers having a plurality of nano particles arranged substantially in parallel; preparing a first film; and arranging a plurality of the first micro-fibers on at least one side of or inside of the first film.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: October 12, 2010
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Sang-Min Lee, Nam-Choul Yang
  • Patent number: 7812343
    Abstract: A multilayer composite body has an electronic function, in particular, an electronic subassembly comprising a plurality of organic electronic components, such as transistors, diodes, capacitors and so on, having at least one common layer, e.g., a semiconductor layer and/or insulation layer, wherein the common layer may be superfluous in one or more of the components. There thus is provided a structure of an entire subassembly such as an RFID tag, wherein the entire tag with all of its components is implemented in one production process.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: October 12, 2010
    Assignee: PolyIC GmbH & Co. KG
    Inventors: Andreas Ullmann, Alexander Knobloch, Merlin Welker, Walter Fix
  • Patent number: 7812344
    Abstract: A thin film transistor is provided. The thin film transistor includes a gate, at least one inorganic material layer, at least one dielectric layer, a source, a drain and an active layer. The gate is disposed on the substrate. The inorganic material layer covers the gate. The dielectric layer including at least one organic material covers the substrate and has an opening exposing the inorganic material layer on the gate. The source and the drain are disposed on the dielectric layer and a part of the inorganic layer exposed by the opening respectively. A channel region exists between the source and the drain. The active layer is disposed on the channel region.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: October 12, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Jing-Yi Yan, Liang-Hsiang Chen
  • Patent number: 7812345
    Abstract: The present invention relates to an organic EL display panel having an organic light emitting layer having a uniform film thickness. The organic EL display panel of the present invention includes: a substrate; linear banks placed on the substrate and defining a linear region on the substrate; and at least two organic EL elements aligned in a row each linear region, and, each of the organic EL elements includes: an anode placed on the substrate; a hole injection layer formed with an metallic oxide and placed on the anode; an organic light emitting layer placed on the hole injection layer; and a cathode placed on the organic light emitting layer. The hole injection layer is concavely curved or convexly curved, the hole injection layer is partly placed under the banks; and the organic light emitting layer is formed by applying an organic light emitting material in the linear region.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: October 12, 2010
    Assignee: Panasonic Corporation
    Inventors: Hidehiro Yoshida, Kenji Okumoto, Keisei Yamamuro
  • Patent number: 7812346
    Abstract: A fabrication method is used in conjunction with a semiconductor device having a metal oxide active layer less than 100 nm thick and the upper major surface and the lower major surface have material in abutting engagement to form underlying interfaces and overlying interfaces. The method of fabrication includes controlling interfacial interactions in the underlying interfaces and the overlying interfaces to adjust the carrier density in the adjacent metal oxide by selecting a metal oxide for the metal oxide active layer and by selecting a specific material for the material in abutting engagement. The method also includes one or both steps of controlling interactions in underlying interfaces by surface treatment of an underlying material forming a component of the underlying interface and controlling interactions in overlying interfaces by surface treatment of the metal oxide film performed prior to deposition of material on the metal oxide layer.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: October 12, 2010
    Assignee: Cbrite, Inc.
    Inventors: Chan-Long Shieh, Gang Yu
  • Patent number: 7812347
    Abstract: A method for measuring an integrated circuit (IC) structure by measuring an imprint of the structure, a method for preparing a test site for the above measuring, and IC so formed. The method for preparing the test site includes incrementally removing the structure from the substrate so as to reveal an imprint of the removed bottom surface of the structure in a top surface of the substrate. The imprint can then be imaged using an atomic force microscope (AFM). The image can be used to measure the bottom surface of the structure.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: October 12, 2010
    Assignee: International Business Machines Corporation
    Inventors: George W. Banke, Jr., Andrew Deering, Philip V. Kaszuba, Leon Moszkowicz, James Robert, James A. Slinkman
  • Patent number: 7812348
    Abstract: A thin-film transistor in which problems with ON-state current and OFF-state current are solved, and a thin-film transistor capable of high-speed operation. The thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions, provided with a space therebetween so as to be overlapped with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of semiconductor layers in which an impurity element which serves as an acceptor is added, overlapped over the gate insulating layers with the gate electrode and the impurity semiconductor layers, and disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer being in contact with the gate insulating layer and the pair of semiconductor layers and extended between the pair of semiconductor layers.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: October 12, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Dairiki, Hidekazu Miyairi, Yoshiyuki Kurokawa, Shunpei Yamazaki, Hiromichi Godo, Daisuke Kawae, Satoshi Kobayashi
  • Patent number: 7812349
    Abstract: An image display apparatus includes a display unit and a voltage source, with the display unit having display devices and pixel circuits. Each of the pixel circuits is provided with a drive transistor which has a first primary electrode connected to one terminal of each of the display devices, a second primary electrode connected to a first common electrode, and a control electrode for controlling by an electric potential the magnitude of a drive current supplied to the display devices. In addition, and a control transistor has a source electrode and a drain electrode connected to the control electrode and the first primary electrode, respectively, and a gate electrode to which a signal switching between an on-state and an off-state is supplied, with an electric potential of the control electrode being set up at the on-state. The voltage source can adjust a voltage applied between the first common electrode and a second common electrode with another terminal of the display device being connected thereto.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: October 12, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Osamu Yuki, Yoshinori Nakajima, Shigeki Kondo
  • Patent number: 7812350
    Abstract: An image sensor and a method for manufacturing the same are provided. A photodiode region and transistor region are vertically-integrated to improve the fill factor and resolution of the image sensor. Unit pixels can be isolated by a metal isolation layer arranged between adjacent photodiode areas.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: October 12, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Tae Gyu Kim
  • Patent number: 7812351
    Abstract: A semiconductor thin film is formed having a lateral growth region which is a collection of columnar or needle-like crystals extending generally parallel with a substrate. The semiconductor thin film is illuminated with laser light or strong light having equivalent energy. As a result, adjacent columnar or needle-like crystals are joined together to form a region having substantially no grain boundaries, i.e., a monodomain region which can substantially be regarded as a single crystal. A semiconductor device is formed by using the monodomain region as an active layer.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: October 12, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Jun Koyama, Takeshi Fukunaga
  • Patent number: 7812352
    Abstract: A TFT array substrate is disclosed. In the pixel structure of the TFT array substrate, patterned transparent conductive layers are disposed under a first metal layer (M1) and a second metal layer (M2) and most areas of the M1 and M2 are substituted by the patterned transparent conductive layers. So, the pixel structure has high aperture ratio and large storage capacitance. Besides, a scan bonding pad on the TFT array substrate includes a first patterned transparent conductive layer (T1), the M1 and a third patterned transparent conductive layer (T3). The M1 is disposed on the T1, and the T3 is electrically connected to the T1 via a contact hole in the M1. So, the contact resistance of the scan bonding pad is small. The data bonding pad on the TFT array substrate has similar design. Moreover, fabricating methods of TFT array substrates are also provided.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: October 12, 2010
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Yao-Hong Chien, Chih-Chieh Wang, Xuan-Yu Liu, Li-Shan Chen
  • Patent number: 7812353
    Abstract: This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: October 12, 2010
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Hao-Chih Yuan, Guogong Wang, Mark A. Eriksson, Paul G. Evans, Max G. Lagally, Zhenqiang Ma
  • Patent number: 7812354
    Abstract: A light emitting diode is disclosed that is formed in the Group III nitride material system. The diode includes respective n-type and p-type layers for current injection and light emission. At least one n-type Group III nitride layer in the diode has dopants selected from the group consisting of elements with a larger atomic radius than silicon and elements with a larger covalent radius than silicon, with germanium and tellurium being exemplary.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: October 12, 2010
    Assignee: Cree, Inc.
    Inventor: David T. Emerson
  • Patent number: 7812355
    Abstract: An object of the present invention is to provide a method for manufacturing a semiconductor device having a semiconductor element capable of reducing a cost and improving a throughput with a minute structure, and further, a method for manufacturing a liquid crystal television and an EL television. According to one feature of the invention, a method for manufacturing a semiconductor device comprises the steps of: forming a light absorption layer over a substrate, forming a first region over the light absorption layer by using a solution, generating heat by irradiating the light absorption layer with laser light, and forming a first film pattern by heating the first region with the heat.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: October 12, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroko Shiroguchi, Yoshiaki Yamamoto
  • Patent number: 7812356
    Abstract: Methods of forming integrated circuit packages having an LED molded into the package, and the integrated circuit package formed thereby. An integrated circuit including one or more semiconductor die, passive components and an LED may be assembled on a panel. The one or more semiconductor die, passive components and LED may all then be encapsulated in a molding compound, and the integrated circuits then singularized to form individual integrated circuit packages. The integrated circuits are cut from the panel so that a portion of the lens of the LED is severed during the singularization process, and an end of the lens remaining within the package lies flush with an edge of the package to emit light outside of the package.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: October 12, 2010
    Assignee: SanDisk Corporation
    Inventors: Hem Takiar, Suresh Upadhyayula
  • Patent number: 7812357
    Abstract: A light emitting diode (LED) having a vertical structure and a method for fabricating the same. The light emitting diode (LED) having a vertical structure includes a support layer; a first electrode formed on the support layer; a plurality of semiconductor layers formed on the first electrode; a conductive semiconductor layer formed on the plurality of semiconductor layer and provided with an outer surface having a tilt angle of a designated degree; and a second electrode formed on the conductive semiconductor layer.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: October 12, 2010
    Assignees: LG Electronics Inc., LG Innotek Co., Ltd.
    Inventors: Jong Wook Kim, Jae Wan Choi, Hyun Kyong Cho, Jong Ho Na, Jun Ho Jang
  • Patent number: 7812358
    Abstract: A light-emitting device is provided in a light-emitting element with a bonding wire that is a fine metallic wire formed mainly of gold or copper and coated at least partly with a substance capable of heightening a reflection coefficient of a wavelength of light emitted from the light-emitting element.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: October 12, 2010
    Assignee: Showa Denko K.K.
    Inventor: Takaki Yasuda
  • Patent number: 7812359
    Abstract: An organic electroluminescent device comprises a first electrode, an organic color conversion layer, a carrier transport layer, an emissive layer, and a second electrode. The organic color conversion layer is disposed over the first electrode. The carrier transport layer is disposed over the organic color conversion layer. The emissive layer is disposed over the carrier transport layer. The second electrode is disposed over the emissive layer.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: October 12, 2010
    Assignee: AU Optronics Corp.
    Inventor: Chung-Chun Lee
  • Patent number: 7812360
    Abstract: A light emitting apparatus 11 comprises: an aluminum nitride co-fired substrate 13; at least one light emitting device 15 mounted on a front surface of the co-fired substrate 13 through a flip-tip method; and a reflector 16 having an inclined surface 14 for reflecting a light emitted from the light emitting device 15 to a front side direction, the reflector 16 is bonded to a surface of the aluminum nitride co-fired substrate 13 so as to surround a circumference of the light emitting device 15. This configuration can simplify the process of manufacturing the apparatus and can provide light emitting apparatus that are excellent in heat radiation performance, allow a larger current to pass therethrough, and can have a significantly increased luminance with a high luminous efficiency.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: October 12, 2010
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Materials Co., Ltd.
    Inventor: Keiichi Yano
  • Patent number: 7812361
    Abstract: A light emitting diode includes a substrate, a reflecting layer, an active layer, a transparent electrode, a first photonic crystal structure, and a second photonic crystal structure. The reflecting layer is disposed on the substrate. The active layer is disposed on the reflecting layer. The transparent electrode is disposed on the active layer and includes an upper surface and a lower surface. The lower surface of the transparent electrode combines with the active layer. The first photonic crystal structure is formed on the upper surface of the transparent electrode. The second photonic crystal structure formed in the active layer.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: October 12, 2010
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Zhen-Feng Xu, Guo-Fan Jin
  • Patent number: 7812362
    Abstract: Provided is a white LED including a reflector cup; an LED chip mounted on the bottom surface of the reflector cup; transparent resin surrounding the LED chip; a phosphor layer formed above the transparent resin; and a reflecting film interposed between the transparent resin and the phosphor layer, the reflecting film reflecting phosphorescence, which is directed downward from the phosphor layer, in the upward direction.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: October 12, 2010
    Assignee: Samsung LED Co., Ltd.
    Inventors: Sergiy Shylo, Dong Ik Shin
  • Patent number: 7812363
    Abstract: A light emitting device module is provided. The light emitting device module includes a plurality of light emitting devices; a submount on which the light emitting devices are mounted; and a heat-radiant substrate to which the submount is fixed. The submount includes a positive front surface electrode; a negative front surface electrode; at least one relay front surface electrode, wherein the plurality of light emitting devices are electrically coupled to each other in series via the at least one relay front surface electrode; a plurality of through electrodes; a positive back surface electrode coupled to the positive front surface electrode via a through electrode; a negative back surface electrode coupled to the negative front surface electrode via a through electrode; and at least one relay back surface electrode which is coupled to the at least one relay front surface electrode via a through electrode.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: October 12, 2010
    Assignee: Koito Manufacturing Co., Ltd.
    Inventor: Yuji Higashi
  • Patent number: 7812364
    Abstract: A semiconductor light emitting device has an outer lead disposed along an outer wall of a mold resin portion perpendicular to a light-emitting plane of a light emitting diode. An outer lead is also disposed at an outer wall of the mold resin portion parallel to and opposite to the light-emitting plane. The outer wall of the resin mold where the outer lead is disposed is taken as a mount face. Each outer wall of the mold resin portion constituting a mount face includes at least one outer lead for an anode and a cathode. According to the present configuration, there is provided a semiconductor light emitting device that allows selection of side-emission mounting or top-emission mounting with the same components on a mount substrate.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: October 12, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Seko, Hisayuki Shinohara
  • Patent number: 7812365
    Abstract: A heat dissipation member includes a first plate-shaped member and a second plate-shaped member. The first plate-shaped member has a first surface thermally connectable with a heat generating element and a second surface. The second plate-shaped member is thermally connected with the second surface of the first plate-shaped member. The first plate-shaped member and the second plate-shaped member form a laminated-plate-shaped member. The laminated-plate-shaped member defines an inlet for admission of a fluid and an outlet communicating with the inlet for ejection of the fluid. The second surface of the first plate-shaped member forms asperities thereon.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: October 12, 2010
    Assignee: Nichia Corporation
    Inventor: Takashi Murayama
  • Patent number: 7812366
    Abstract: An AlGaN composition is provided comprising a group III-Nitride active region layer, for use in an active region of a UV light emitting device, wherein light-generation occurs through radiative recombination of carriers in nanometer scale size, compositionally inhomogeneous regions having band-gap energy less than the surrounding material. Further, a semiconductor UV light emitting device having an active region layer comprised of the AlGaN composition above is provided, as well as a method of producing the AlGaN composition and semiconductor UV light emitting device, involving molecular beam epitaxy.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: October 12, 2010
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Anand Venktesh Sampath, Charles J. Collins, Gregory Alan Garrett, H. Paul Shen, Michael Wraback
  • Patent number: 7812367
    Abstract: In one embodiment, a two terminal multi-channel ESD device is configured to include a zener diode and a plurality of P-N diodes.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: October 12, 2010
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Ali Salih, Mingjiao Liu, Thomas Keena
  • Patent number: 7812368
    Abstract: The invention relates to a high-speed diode comprising a semiconductor body (1), in which a heavily n-doped zone (8), a weakly n-doped zone (7) and a weakly p-doped zone (6) are arranged successively in a vertical direction (v), between which a pn load junction (4) is formed. A number of heavily p-doped islands (51-57) spaced apart from one another are arranged in the weakly p-doped zone (6). In this case, it is provided that the cross-sectional area density of the heavily p-doped islands (51-57) is smaller in a first area region (100) near to the edge than in a second area region (200) remote from the edge.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: October 12, 2010
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Reiner Barthelmess
  • Patent number: 7812369
    Abstract: A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: October 12, 2010
    Assignee: The Regents of the University of California
    Inventors: Alessandro Chini, Umesh K. Mishra, Primit Parikh, Yifeng Wu
  • Patent number: 7812370
    Abstract: A semiconductor device and the methods of forming the same are provided. The semiconductor device includes a low energy band-gap layer comprising a semiconductor material; a gate dielectric on the low energy band-gap layer; a gate electrode over the gate dielectric; a first source/drain region adjacent the gate dielectric, wherein the first source/drain region is of a first conductivity type; and a second source/drain region adjacent the gate dielectric. The second source/drain region is of a second conductivity type opposite the first conductivity type. The low energy band-gap layer is located between the first and the second source/drain regions.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: October 12, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Krishna Kumar Bhuwalka, Ken-Ichi Goto
  • Patent number: 7812371
    Abstract: The field effect transistor includes a laminated structure in which a buffer layer, and an electron transporting layer (undoped GaN layer), and an electron supplying layer (undoped AlGaN layer) are laminated in sequence on a sapphire substrate. An npn laminated structure is formed on a source region of the electron supplying layer, and a source electrode is formed on the npn laminated structure. A drain electrode is formed in a drain region of the electron supplying layer, and an insulating film is formed in an opening region formed in the gate region. When a forward voltage greater than a threshold is applied to the gate electrode, an inversion layer is formed and the drain current flows. By changing a thickness and an impurity concentration of the p-type GaN layer, the threshold voltage can be controlled. The electrical field concentration between the gate electrode and the drain electrode is relaxed due to the drift layer, and voltage resistance improves.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: October 12, 2010
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Shusuke Kaya, Seikoh Yoshida, Masatoshi Ikeda, legal representative, Sadahiro Kato, Takehiko Nomura, Nariaki Ikeda, Masayuki Iwami, Yoshihiro Sato, Hiroshi Kambayashi, Yuki Niiyama
  • Patent number: 7812372
    Abstract: A semiconductor device includes a support substrate and a semiconductor layer formed on the underlying substrate. The support substrate has its metal part formed by plating and extending across its entire thickness, whilst it has the other region made of semiconductor part. In particular, the region of the support substrate lying immediately below an active region is the metal part formed by plating. The region of the support substrate lying immediately below the region other than the active region is an inactive region made of semiconductor. The semiconductor device thus suppresses warping of a substrate otherwise caused by stress in the metal part formed by plating, and heat evolved due to the current in operation of the semiconductor device may be dissipated over the shortest path through the metal part having a higher thermal conductivity.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: October 12, 2010
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hideyuki Okita
  • Patent number: 7812373
    Abstract: A circuit array includes a plurality cells, wherein each cell has at least one group of odd fins. The cells may be arranged in a repeating pattern that includes mirror images of the pattern. A plurality of fin forming regions are provided about which the fins are formed for the dual fin and single fin transistors.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: October 12, 2010
    Assignee: Infineon Technologies AG
    Inventors: Florian Bauer, Klaus von Arnim
  • Patent number: 7812374
    Abstract: A semiconductor device includes a first MIS transistor on a first active region of a semiconductor substrate, the first MIS transistor including: a first gate insulating film provided on the first active region; a first gate electrode provided on the first gate insulating film; a first stressor insulating film provided on an upper face and side faces facing in a gate length direction of the first gate electrode such that first stress acts on a channel of the first MIS transistor in the gate length direction; and a first base insulating film provided on side faces of the first gate electrode facing in a gate width direction, wherein the side faces of the first gate electrode facing in the gate width direction are not covered with the first stressor insulating film.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: October 12, 2010
    Assignee: Panasonic Corporation
    Inventors: Nobuyuki Tamura, Ken Suzuki, Katsuhiro Ootani
  • Patent number: 7812375
    Abstract: In the non-volatile memory device, a first isolation layer is formed to have a plurality of depressions each having a predetermined depth from an upper surface of the semiconductor substrate. A fin type first active region is defined by the first isolation layer and has one or more inflected portions at its sidewalls exposed from the first isolation layer, where the first active region is divided into an upper part and a lower part by the inflected portions and a width of the upper part is narrower than that of the lower part. A tunneling insulation layer is formed on the first active region. A storage node layer is formed on the tunneling insulation layer. Also, a blocking insulation layer is formed on the storage node layer, and a control gate electrode is formed on the blocking insulation layer.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: October 12, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Hyun Lee, Tea-Kwang Yu, Jong-Sun Sel, Ju-Hyung Kim, Byeong-In Choe
  • Patent number: 7812376
    Abstract: Provided are a nonvolatile memory device and methods of fabricating and operating the same. The memory device may include a substrate, at least a first and a second electrode on the substrate to be spaced a distance from each other, a conductive nanotube between the first and second electrodes and selectively coming into contact with the first electrode or the second electrode due to an electrostatic force and a support supporting the conductive nanotube. The memory device may be an erasable nonvolatile memory device which may retain information even when no power is supplied and may ensure relatively high operating speed and relatively high integration density. Because the memory device writes and erases information in units of bits, the memory device may be applied to a large number of fields.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: October 12, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Gyoo Yoo, Soo-Il Lee
  • Patent number: 7812377
    Abstract: In the semiconductor device, a gate region is formed in a mesh pattern having first polygonal shapes and second polygonal shapes the area of which is smaller than that of the first polygonal shapes, and drain regions and source regions are disposed within the first polygonal shapes and the second polygonal shapes, respectively. With this configuration, the forward transfer admittance gm can be increased as compared with a structure in which gate regions are disposed in a stripe pattern. Furthermore, compared with a case in which a gate region is disposed in a grid pattern, deterioration in forward transfer characteristics (amplification characteristics) due to an increase in input capacitance Ciss can be minimized while a predetermined withstand voltage is maintained.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: October 12, 2010
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Yoshiaki Matsumiya, Mitsuo Hatamoto
  • Patent number: 7812378
    Abstract: A semiconductor device includes a first MOS type capacitor having a first insulating film and a first electrode that are formed on a semiconductor substrate, and a second MOS type capacitor having a second insulating film and a second electrode that are formed on the semiconductor substrate. The first electrode has a first concentration difference as a difference when an impurity concentration in an interface region with the first insulating film is subtracted from an impurity concentration in a top portion of the first electrode. The second electrode has a second concentration difference as a difference when an impurity concentration in an interface region with the second insulating film is subtracted from an impurity concentration in a top portion of the second electrode. The second concentration difference is larger than the first concentration difference.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: October 12, 2010
    Assignee: Panasonic Corporation
    Inventor: Yoshiyuki Shibata
  • Patent number: 7812379
    Abstract: Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: October 12, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Long Cheng, Kong-Beng Thei, Sheng-Chen Chung, Tzung-Chi Lee, Harry Chuang
  • Patent number: 7812380
    Abstract: A solid-state imaging device of the present invention includes: a semiconductor substrate including a first region of a first conductivity type; a signal accumulation region of a second conductivity type formed within the first region; a gate electrode formed above the first region; a drain region of a second conductivity type formed on the first region; an isolation region having insulation properties, which is formed to surround a region where the signal accumulation region, the gate electrode, and the drain region are formed; a first conductivity type dopant doping region formed in contact with a side face and a bottom face of the isolation region, the first conductivity type dopant doping region having a higher dopant concentration than the first region; and a second conductivity type dopant doping region formed in the first region, under an end of the gate electrode in a gate width direction.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: October 12, 2010
    Assignee: Panasonic Corporation
    Inventors: Tatsuya Hirata, Motonari Katsuno
  • Patent number: 7812381
    Abstract: There is provided a CMOS image sensor and an electronic product using the same. The CMOS image sensor includes a plurality of pixels for embodying colors having different wavelengths. Each of pixels includes a buried barrier layer disposed in a semiconductor substrate and having a barrier potential energy of a conduction band thereof at an equilibrium state, a first layer disposed at a main surface of the semiconductor substrate separated from the buried barrier layer in a vertical direction and having a first potential energy of a conduction band thereof at the equilibrium state, and a second layer disposed between the first region and the buried barrier layer having a second potential energy of a conduction band thereof at the equilibrium state. The second potential energy is higher than the first potential energy and the barrier potential energy and a thickness of the second layer is thicker as the wavelength is longer.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: October 12, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Hoon Park
  • Patent number: 7812382
    Abstract: An image sensing apparatus includes an image sensing region where a plurality of pixels are two-dimensionally arrayed. Each pixel includes a photoelectric conversion unit, and a semiconductor region arranged below an element isolation region having an insulation film to isolate the photoelectric conversion unit from an adjacent pixel. The semiconductor region includes a plurality of diffusion layers. The offset amount of at least one diffusion layer in the semiconductor region with respect to the normal line is larger in a pixel arranged at the peripheral portion of the image sensing region than a pixel arranged at the center of the image sensing region.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: October 12, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventor: Satoko Iida
  • Patent number: 7812383
    Abstract: A spin memory includes a magneto-resistance element having a first ferromagnetic layer in which a magnetization direction is pinned, a second ferromagnetic layer in which a magnetization direction changes, and a first nonmagnetic layer between the first and second ferromagnetic layers, a lower electrode and an upper electrode extending in a direction between 45 degrees and 90 degrees relative to an axis of hard magnetization of the second ferromagnetic layer, and sandwiching the magneto-resistance element at one end in a longitudinal direction, a switching element connected to another end in a longitudinal direction of the lower electrode, and a bit line connected to another end in a longitudinal direction of the upper electrode, wherein writing is carried out by supplying spin-polarized electrons to the second ferromagnetic layer and applying a magnetic field from the lower electrode and the upper electrode to the second ferromagnetic layer.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: October 12, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoaki Inokuchi, Yoshiaki Saito, Hideyuki Sugiyama
  • Patent number: 7812384
    Abstract: According to an aspect of the present invention, there is provided a semiconductor device including: a transistor including: a source, a drain and a gate; first and second plugs on the source and the drain; a third plug on the gate to have a top face higher than that of the first plug; an interlayer insulating film covering the transistor and the first to the third plugs; a ferroelectric capacitor on the interlayer insulating film, one electrode thereof being connected to the first plug; a barrier film covering surfaces of the ferroelectric capacitor and the interlayer insulating film to prevent a substance affecting the ferroelectric capacitor from entering therethrough; and fourth and fifth plugs disposed on the second and the third plugs and connected thereto through connection holes formed in the barrier film.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: October 12, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tohru Ozaki
  • Patent number: 7812385
    Abstract: A semiconductor device includes: a ferroelectric capacitor that is provided above a base substrate and includes a first electrode, a ferroelectric film provided on the first electrode and a second electrode provided on the ferroelectric film; a stopper film that covers a top surface of the second electrode of the ferroelectric capacitor; a hydrogen barrier film that covers a top surface and a side surface of the stopper film and a side surface of the ferroelectric capacitor; an interlayer dielectric film that covers the hydrogen barrier film and the base substrate; a contact hole that penetrates the interlayer dielectric film, the hydrogen barrier film and the stopper film and exposes the second electrode; a barrier metal that covers the second electrode exposed in the contact hole and an inner wall surface of the contact hole and is composed of a conductive material having hydrogen barrier property; and a plug conductive section that is embedded in the contact hole and conductively connects to the barrier me
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: October 12, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Takafumi Noda